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228 lines
6.7 KiB
228 lines
6.7 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Linux performance counter support for ARC |
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* |
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* Copyright (C) 2014-2015 Synopsys, Inc. (www.synopsys.com) |
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* Copyright (C) 2011-2013 Synopsys, Inc. (www.synopsys.com) |
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*/ |
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#ifndef __ASM_PERF_EVENT_H |
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#define __ASM_PERF_EVENT_H |
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/* Max number of counters that PCT block may ever have */ |
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#define ARC_PERF_MAX_COUNTERS 32 |
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#define ARC_REG_CC_BUILD 0xF6 |
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#define ARC_REG_CC_INDEX 0x240 |
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#define ARC_REG_CC_NAME0 0x241 |
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#define ARC_REG_CC_NAME1 0x242 |
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#define ARC_REG_PCT_BUILD 0xF5 |
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#define ARC_REG_PCT_COUNTL 0x250 |
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#define ARC_REG_PCT_COUNTH 0x251 |
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#define ARC_REG_PCT_SNAPL 0x252 |
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#define ARC_REG_PCT_SNAPH 0x253 |
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#define ARC_REG_PCT_CONFIG 0x254 |
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#define ARC_REG_PCT_CONTROL 0x255 |
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#define ARC_REG_PCT_INDEX 0x256 |
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#define ARC_REG_PCT_INT_CNTL 0x25C |
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#define ARC_REG_PCT_INT_CNTH 0x25D |
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#define ARC_REG_PCT_INT_CTRL 0x25E |
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#define ARC_REG_PCT_INT_ACT 0x25F |
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#define ARC_REG_PCT_CONFIG_USER (1 << 18) /* count in user mode */ |
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#define ARC_REG_PCT_CONFIG_KERN (1 << 19) /* count in kernel mode */ |
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#define ARC_REG_PCT_CONTROL_CC (1 << 16) /* clear counts */ |
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#define ARC_REG_PCT_CONTROL_SN (1 << 17) /* snapshot */ |
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struct arc_reg_pct_build { |
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#ifdef CONFIG_CPU_BIG_ENDIAN |
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unsigned int m:8, c:8, r:5, i:1, s:2, v:8; |
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#else |
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unsigned int v:8, s:2, i:1, r:5, c:8, m:8; |
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#endif |
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}; |
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struct arc_reg_cc_build { |
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#ifdef CONFIG_CPU_BIG_ENDIAN |
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unsigned int c:16, r:8, v:8; |
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#else |
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unsigned int v:8, r:8, c:16; |
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#endif |
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}; |
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#define PERF_COUNT_ARC_DCLM (PERF_COUNT_HW_MAX + 0) |
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#define PERF_COUNT_ARC_DCSM (PERF_COUNT_HW_MAX + 1) |
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#define PERF_COUNT_ARC_ICM (PERF_COUNT_HW_MAX + 2) |
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#define PERF_COUNT_ARC_BPOK (PERF_COUNT_HW_MAX + 3) |
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#define PERF_COUNT_ARC_EDTLB (PERF_COUNT_HW_MAX + 4) |
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#define PERF_COUNT_ARC_EITLB (PERF_COUNT_HW_MAX + 5) |
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#define PERF_COUNT_ARC_LDC (PERF_COUNT_HW_MAX + 6) |
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#define PERF_COUNT_ARC_STC (PERF_COUNT_HW_MAX + 7) |
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#define PERF_COUNT_ARC_HW_MAX (PERF_COUNT_HW_MAX + 8) |
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/* |
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* Some ARC pct quirks: |
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* |
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* PERF_COUNT_HW_STALLED_CYCLES_BACKEND |
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* PERF_COUNT_HW_STALLED_CYCLES_FRONTEND |
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* The ARC 700 can either measure stalls per pipeline stage, or all stalls |
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* combined; for now we assign all stalls to STALLED_CYCLES_BACKEND |
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* and all pipeline flushes (e.g. caused by mispredicts, etc.) to |
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* STALLED_CYCLES_FRONTEND. |
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* |
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* We could start multiple performance counters and combine everything |
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* afterwards, but that makes it complicated. |
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* |
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* Note that I$ cache misses aren't counted by either of the two! |
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*/ |
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/* |
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* ARC PCT has hardware conditions with fixed "names" but variable "indexes" |
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* (based on a specific RTL build) |
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* Below is the static map between perf generic/arc specific event_id and |
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* h/w condition names. |
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* At the time of probe, we loop thru each index and find it's name to |
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* complete the mapping of perf event_id to h/w index as latter is needed |
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* to program the counter really |
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*/ |
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static const char * const arc_pmu_ev_hw_map[] = { |
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/* count cycles */ |
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[PERF_COUNT_HW_CPU_CYCLES] = "crun", |
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[PERF_COUNT_HW_REF_CPU_CYCLES] = "crun", |
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[PERF_COUNT_HW_BUS_CYCLES] = "crun", |
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = "bflush", |
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[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall", |
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/* counts condition */ |
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[PERF_COUNT_HW_INSTRUCTIONS] = "iall", |
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/* All jump instructions that are taken */ |
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmptak", |
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#ifdef CONFIG_ISA_ARCV2 |
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[PERF_COUNT_HW_BRANCH_MISSES] = "bpmp", |
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#else |
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[PERF_COUNT_ARC_BPOK] = "bpok", /* NP-NT, PT-T, PNT-NT */ |
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[PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */ |
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#endif |
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[PERF_COUNT_ARC_LDC] = "imemrdc", /* Instr: mem read cached */ |
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[PERF_COUNT_ARC_STC] = "imemwrc", /* Instr: mem write cached */ |
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[PERF_COUNT_ARC_DCLM] = "dclm", /* D-cache Load Miss */ |
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[PERF_COUNT_ARC_DCSM] = "dcsm", /* D-cache Store Miss */ |
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[PERF_COUNT_ARC_ICM] = "icm", /* I-cache Miss */ |
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[PERF_COUNT_ARC_EDTLB] = "edtlb", /* D-TLB Miss */ |
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[PERF_COUNT_ARC_EITLB] = "eitlb", /* I-TLB Miss */ |
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[PERF_COUNT_HW_CACHE_REFERENCES] = "imemrdc", /* Instr: mem read cached */ |
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[PERF_COUNT_HW_CACHE_MISSES] = "dclm", /* D-cache Load Miss */ |
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}; |
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#define C(_x) PERF_COUNT_HW_CACHE_##_x |
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#define CACHE_OP_UNSUPPORTED 0xffff |
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static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { |
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[C(L1D)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC, |
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[C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC, |
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[C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
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}, |
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}, |
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[C(L1I)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = PERF_COUNT_HW_INSTRUCTIONS, |
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[C(RESULT_MISS)] = PERF_COUNT_ARC_ICM, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
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}, |
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}, |
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[C(LL)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
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}, |
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}, |
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[C(DTLB)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC, |
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[C(RESULT_MISS)] = PERF_COUNT_ARC_EDTLB, |
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}, |
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/* DTLB LD/ST Miss not segregated by h/w*/ |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
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}, |
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}, |
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[C(ITLB)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |
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[C(RESULT_MISS)] = PERF_COUNT_ARC_EITLB, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
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}, |
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}, |
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[C(BPU)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS, |
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[C(RESULT_MISS)] = PERF_COUNT_HW_BRANCH_MISSES, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
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}, |
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}, |
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[C(NODE)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, |
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}, |
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}, |
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}; |
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#endif /* __ASM_PERF_EVENT_H */
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