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132 lines
3.7 KiB
132 lines
3.7 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
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*/ |
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#ifndef __ARC_ASM_CACHE_H |
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#define __ARC_ASM_CACHE_H |
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/* In case $$ not config, setup a dummy number for rest of kernel */ |
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#ifndef CONFIG_ARC_CACHE_LINE_SHIFT |
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#define L1_CACHE_SHIFT 6 |
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#else |
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#define L1_CACHE_SHIFT CONFIG_ARC_CACHE_LINE_SHIFT |
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#endif |
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) |
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#define CACHE_LINE_MASK (~(L1_CACHE_BYTES - 1)) |
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/* |
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* ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF) |
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* Ideal for wiring memory mapped peripherals as we don't need to do |
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* explicit uncached accesses (LD.di/ST.di) hence more portable drivers |
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*/ |
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#define ARC_UNCACHED_ADDR_SPACE 0xc0000000 |
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#ifndef __ASSEMBLY__ |
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#include <linux/build_bug.h> |
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/* Uncached access macros */ |
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#define arc_read_uncached_32(ptr) \ |
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({ \ |
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unsigned int __ret; \ |
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__asm__ __volatile__( \ |
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" ld.di %0, [%1] \n" \ |
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: "=r"(__ret) \ |
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: "r"(ptr)); \ |
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__ret; \ |
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}) |
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#define arc_write_uncached_32(ptr, data)\ |
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({ \ |
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__asm__ __volatile__( \ |
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" st.di %0, [%1] \n" \ |
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: \ |
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: "r"(data), "r"(ptr)); \ |
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}) |
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/* Largest line length for either L1 or L2 is 128 bytes */ |
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#define SMP_CACHE_BYTES 128 |
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#define cache_line_size() SMP_CACHE_BYTES |
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#define ARCH_DMA_MINALIGN SMP_CACHE_BYTES |
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/* |
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* Make sure slab-allocated buffers are 64-bit aligned when atomic64_t uses |
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* ARCv2 64-bit atomics (LLOCKD/SCONDD). This guarantess runtime 64-bit |
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* alignment for any atomic64_t embedded in buffer. |
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* Default ARCH_SLAB_MINALIGN is __alignof__(long long) which has a relaxed |
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* value of 4 (and not 8) in ARC ABI. |
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*/ |
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#if defined(CONFIG_ARC_HAS_LL64) && defined(CONFIG_ARC_HAS_LLSC) |
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#define ARCH_SLAB_MINALIGN 8 |
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#endif |
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extern void arc_cache_init(void); |
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extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len); |
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extern void read_decode_cache_bcr(void); |
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extern int ioc_enable; |
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extern unsigned long perip_base, perip_end; |
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#endif /* !__ASSEMBLY__ */ |
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/* Instruction cache related Auxiliary registers */ |
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#define ARC_REG_IC_BCR 0x77 /* Build Config reg */ |
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#define ARC_REG_IC_IVIC 0x10 |
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#define ARC_REG_IC_CTRL 0x11 |
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#define ARC_REG_IC_IVIR 0x16 |
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#define ARC_REG_IC_ENDR 0x17 |
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#define ARC_REG_IC_IVIL 0x19 |
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#define ARC_REG_IC_PTAG 0x1E |
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#define ARC_REG_IC_PTAG_HI 0x1F |
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/* Bit val in IC_CTRL */ |
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#define IC_CTRL_DIS 0x1 |
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/* Data cache related Auxiliary registers */ |
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#define ARC_REG_DC_BCR 0x72 /* Build Config reg */ |
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#define ARC_REG_DC_IVDC 0x47 |
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#define ARC_REG_DC_CTRL 0x48 |
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#define ARC_REG_DC_IVDL 0x4A |
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#define ARC_REG_DC_FLSH 0x4B |
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#define ARC_REG_DC_FLDL 0x4C |
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#define ARC_REG_DC_STARTR 0x4D |
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#define ARC_REG_DC_ENDR 0x4E |
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#define ARC_REG_DC_PTAG 0x5C |
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#define ARC_REG_DC_PTAG_HI 0x5F |
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/* Bit val in DC_CTRL */ |
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#define DC_CTRL_DIS 0x001 |
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#define DC_CTRL_INV_MODE_FLUSH 0x040 |
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#define DC_CTRL_FLUSH_STATUS 0x100 |
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#define DC_CTRL_RGN_OP_INV 0x200 |
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#define DC_CTRL_RGN_OP_MSK 0x200 |
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/*System-level cache (L2 cache) related Auxiliary registers */ |
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#define ARC_REG_SLC_CFG 0x901 |
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#define ARC_REG_SLC_CTRL 0x903 |
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#define ARC_REG_SLC_FLUSH 0x904 |
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#define ARC_REG_SLC_INVALIDATE 0x905 |
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#define ARC_AUX_SLC_IVDL 0x910 |
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#define ARC_AUX_SLC_FLDL 0x912 |
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#define ARC_REG_SLC_RGN_START 0x914 |
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#define ARC_REG_SLC_RGN_START1 0x915 |
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#define ARC_REG_SLC_RGN_END 0x916 |
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#define ARC_REG_SLC_RGN_END1 0x917 |
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/* Bit val in SLC_CONTROL */ |
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#define SLC_CTRL_DIS 0x001 |
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#define SLC_CTRL_IM 0x040 |
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#define SLC_CTRL_BUSY 0x100 |
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#define SLC_CTRL_RGN_OP_INV 0x200 |
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/* IO coherency related Auxiliary registers */ |
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#define ARC_REG_IO_COH_ENABLE 0x500 |
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#define ARC_IO_COH_ENABLE_BIT BIT(0) |
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#define ARC_REG_IO_COH_PARTIAL 0x501 |
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#define ARC_IO_COH_PARTIAL_BIT BIT(0) |
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#define ARC_REG_IO_COH_AP0_BASE 0x508 |
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#define ARC_REG_IO_COH_AP0_SIZE 0x509 |
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#endif /* _ASM_CACHE_H */
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