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609 lines
15 KiB
609 lines
15 KiB
# SPDX-License-Identifier: GPL-2.0-only |
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# |
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# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
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# |
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config ARC |
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def_bool y |
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select ARC_TIMERS |
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select ARCH_HAS_DEBUG_VM_PGTABLE |
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select ARCH_HAS_DMA_PREP_COHERENT |
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select ARCH_HAS_PTE_SPECIAL |
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select ARCH_HAS_SETUP_DMA_OPS |
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select ARCH_HAS_SYNC_DMA_FOR_CPU |
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE |
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select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC |
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select ARCH_32BIT_OFF_T |
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select BUILDTIME_TABLE_SORT |
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select CLONE_BACKWARDS |
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select COMMON_CLK |
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select DMA_DIRECT_REMAP |
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select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) |
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select GENERIC_FIND_FIRST_BIT |
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# for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP |
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select GENERIC_IRQ_SHOW |
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select GENERIC_PCI_IOMAP |
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select GENERIC_PENDING_IRQ if SMP |
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select GENERIC_SCHED_CLOCK |
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select GENERIC_SMP_IDLE_THREAD |
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select HAVE_ARCH_KGDB |
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select HAVE_ARCH_TRACEHOOK |
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select HAVE_DEBUG_STACKOVERFLOW |
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select HAVE_DEBUG_KMEMLEAK |
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select HAVE_FUTEX_CMPXCHG if FUTEX |
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select HAVE_IOREMAP_PROT |
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select HAVE_KERNEL_GZIP |
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select HAVE_KERNEL_LZMA |
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select HAVE_KPROBES |
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select HAVE_KRETPROBES |
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select HAVE_MOD_ARCH_SPECIFIC |
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select HAVE_PERF_EVENTS |
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select HANDLE_DOMAIN_IRQ |
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select IRQ_DOMAIN |
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select MODULES_USE_ELF_RELA |
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select OF |
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select OF_EARLY_FLATTREE |
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select PCI_SYSCALL if PCI |
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select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING |
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select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32 |
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select SET_FS |
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config ARCH_HAS_CACHE_LINE_SIZE |
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def_bool y |
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config TRACE_IRQFLAGS_SUPPORT |
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def_bool y |
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config LOCKDEP_SUPPORT |
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def_bool y |
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config SCHED_OMIT_FRAME_POINTER |
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def_bool y |
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config GENERIC_CSUM |
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def_bool y |
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config ARCH_DISCONTIGMEM_ENABLE |
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def_bool n |
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depends on BROKEN |
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config ARCH_FLATMEM_ENABLE |
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def_bool y |
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config MMU |
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def_bool y |
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config NO_IOPORT_MAP |
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def_bool y |
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config GENERIC_CALIBRATE_DELAY |
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def_bool y |
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config GENERIC_HWEIGHT |
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def_bool y |
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config STACKTRACE_SUPPORT |
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def_bool y |
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select STACKTRACE |
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config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
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def_bool y |
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depends on ARC_MMU_V4 |
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menu "ARC Architecture Configuration" |
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menu "ARC Platform/SoC/Board" |
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source "arch/arc/plat-tb10x/Kconfig" |
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source "arch/arc/plat-axs10x/Kconfig" |
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source "arch/arc/plat-hsdk/Kconfig" |
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endmenu |
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choice |
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prompt "ARC Instruction Set" |
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default ISA_ARCV2 |
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config ISA_ARCOMPACT |
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bool "ARCompact ISA" |
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select CPU_NO_EFFICIENT_FFS |
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help |
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The original ARC ISA of ARC600/700 cores |
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config ISA_ARCV2 |
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bool "ARC ISA v2" |
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select ARC_TIMERS_64BIT |
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help |
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ISA for the Next Generation ARC-HS cores |
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endchoice |
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menu "ARC CPU Configuration" |
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choice |
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prompt "ARC Core" |
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default ARC_CPU_770 if ISA_ARCOMPACT |
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default ARC_CPU_HS if ISA_ARCV2 |
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if ISA_ARCOMPACT |
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config ARC_CPU_750D |
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bool "ARC750D" |
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select ARC_CANT_LLSC |
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help |
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Support for ARC750 core |
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config ARC_CPU_770 |
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bool "ARC770" |
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select ARC_HAS_SWAPE |
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help |
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Support for ARC770 core introduced with Rel 4.10 (Summer 2011) |
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This core has a bunch of cool new features: |
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-MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) |
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Shared Address Spaces (for sharing TLB entries in MMU) |
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-Caches: New Prog Model, Region Flush |
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-Insns: endian swap, load-locked/store-conditional, time-stamp-ctr |
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endif #ISA_ARCOMPACT |
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config ARC_CPU_HS |
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bool "ARC-HS" |
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depends on ISA_ARCV2 |
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help |
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Support for ARC HS38x Cores based on ARCv2 ISA |
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The notable features are: |
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- SMP configurations of up to 4 cores with coherency |
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- Optional L2 Cache and IO-Coherency |
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- Revised Interrupt Architecture (multiple priorites, reg banks, |
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auto stack switch, auto regfile save/restore) |
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- MMUv4 (PIPT dcache, Huge Pages) |
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- Instructions for |
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* 64bit load/store: LDD, STD |
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* Hardware assisted divide/remainder: DIV, REM |
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* Function prologue/epilogue: ENTER_S, LEAVE_S |
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* IRQ enable/disable: CLRI, SETI |
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* pop count: FFS, FLS |
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* SETcc, BMSKN, XBFU... |
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endchoice |
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config ARC_TUNE_MCPU |
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string "Override default -mcpu compiler flag" |
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default "" |
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help |
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Override default -mcpu=xxx compiler flag (which is set depending on |
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the ISA version) with the specified value. |
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NOTE: If specified flag isn't supported by current compiler the |
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ISA default value will be used as a fallback. |
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config CPU_BIG_ENDIAN |
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bool "Enable Big Endian Mode" |
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help |
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Build kernel for Big Endian Mode of ARC CPU |
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config SMP |
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bool "Symmetric Multi-Processing" |
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select ARC_MCIP if ISA_ARCV2 |
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help |
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This enables support for systems with more than one CPU. |
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if SMP |
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config NR_CPUS |
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int "Maximum number of CPUs (2-4096)" |
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range 2 4096 |
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default "4" |
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config ARC_SMP_HALT_ON_RESET |
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bool "Enable Halt-on-reset boot mode" |
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help |
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In SMP configuration cores can be configured as Halt-on-reset |
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or they could all start at same time. For Halt-on-reset, non |
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masters are parked until Master kicks them so they can start off |
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at designated entry point. For other case, all jump to common |
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entry point and spin wait for Master's signal. |
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endif #SMP |
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config ARC_MCIP |
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bool "ARConnect Multicore IP (MCIP) Support " |
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depends on ISA_ARCV2 |
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default y if SMP |
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help |
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This IP block enables SMP in ARC-HS38 cores. |
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It provides for cross-core interrupts, multi-core debug |
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hardware semaphores, shared memory,.... |
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menuconfig ARC_CACHE |
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bool "Enable Cache Support" |
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default y |
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if ARC_CACHE |
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config ARC_CACHE_LINE_SHIFT |
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int "Cache Line Length (as power of 2)" |
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range 5 7 |
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default "6" |
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help |
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Starting with ARC700 4.9, Cache line length is configurable, |
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This option specifies "N", with Line-len = 2 power N |
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So line lengths of 32, 64, 128 are specified by 5,6,7, respectively |
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Linux only supports same line lengths for I and D caches. |
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config ARC_HAS_ICACHE |
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bool "Use Instruction Cache" |
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default y |
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config ARC_HAS_DCACHE |
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bool "Use Data Cache" |
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default y |
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config ARC_CACHE_PAGES |
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bool "Per Page Cache Control" |
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default y |
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depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE |
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help |
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This can be used to over-ride the global I/D Cache Enable on a |
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per-page basis (but only for pages accessed via MMU such as |
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Kernel Virtual address or User Virtual Address) |
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TLB entries have a per-page Cache Enable Bit. |
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Note that Global I/D ENABLE + Per Page DISABLE works but corollary |
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Global DISABLE + Per Page ENABLE won't work |
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config ARC_CACHE_VIPT_ALIASING |
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bool "Support VIPT Aliasing D$" |
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depends on ARC_HAS_DCACHE && ISA_ARCOMPACT |
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endif #ARC_CACHE |
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config ARC_HAS_ICCM |
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bool "Use ICCM" |
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help |
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Single Cycle RAMS to store Fast Path Code |
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config ARC_ICCM_SZ |
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int "ICCM Size in KB" |
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default "64" |
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depends on ARC_HAS_ICCM |
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config ARC_HAS_DCCM |
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bool "Use DCCM" |
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help |
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Single Cycle RAMS to store Fast Path Data |
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config ARC_DCCM_SZ |
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int "DCCM Size in KB" |
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default "64" |
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depends on ARC_HAS_DCCM |
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config ARC_DCCM_BASE |
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hex "DCCM map address" |
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default "0xA0000000" |
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depends on ARC_HAS_DCCM |
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choice |
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prompt "MMU Version" |
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default ARC_MMU_V3 if ARC_CPU_770 |
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default ARC_MMU_V2 if ARC_CPU_750D |
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default ARC_MMU_V4 if ARC_CPU_HS |
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if ISA_ARCOMPACT |
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config ARC_MMU_V1 |
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bool "MMU v1" |
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help |
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Orig ARC700 MMU |
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config ARC_MMU_V2 |
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bool "MMU v2" |
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help |
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Fixed the deficiency of v1 - possible thrashing in memcpy scenario |
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when 2 D-TLB and 1 I-TLB entries index into same 2way set. |
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config ARC_MMU_V3 |
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bool "MMU v3" |
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depends on ARC_CPU_770 |
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help |
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Introduced with ARC700 4.10: New Features |
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Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) |
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Shared Address Spaces (SASID) |
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endif |
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config ARC_MMU_V4 |
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bool "MMU v4" |
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depends on ISA_ARCV2 |
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endchoice |
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choice |
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prompt "MMU Page Size" |
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default ARC_PAGE_SIZE_8K |
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config ARC_PAGE_SIZE_8K |
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bool "8KB" |
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help |
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Choose between 8k vs 16k |
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config ARC_PAGE_SIZE_16K |
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bool "16KB" |
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depends on ARC_MMU_V3 || ARC_MMU_V4 |
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config ARC_PAGE_SIZE_4K |
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bool "4KB" |
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depends on ARC_MMU_V3 || ARC_MMU_V4 |
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endchoice |
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choice |
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prompt "MMU Super Page Size" |
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depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE |
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default ARC_HUGEPAGE_2M |
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config ARC_HUGEPAGE_2M |
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bool "2MB" |
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config ARC_HUGEPAGE_16M |
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bool "16MB" |
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endchoice |
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config NODES_SHIFT |
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int "Maximum NUMA Nodes (as a power of 2)" |
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default "0" if !DISCONTIGMEM |
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default "1" if DISCONTIGMEM |
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depends on NEED_MULTIPLE_NODES |
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help |
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Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory |
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zones. |
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config ARC_COMPACT_IRQ_LEVELS |
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depends on ISA_ARCOMPACT |
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bool "Setup Timer IRQ as high Priority" |
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# if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy |
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depends on !SMP |
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config ARC_FPU_SAVE_RESTORE |
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bool "Enable FPU state persistence across context switch" |
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help |
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ARCompact FPU has internal registers to assist with Double precision |
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Floating Point operations. There are control and stauts registers |
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for floating point exceptions and rounding modes. These are |
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preserved across task context switch when enabled. |
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config ARC_CANT_LLSC |
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def_bool n |
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config ARC_HAS_LLSC |
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bool "Insn: LLOCK/SCOND (efficient atomic ops)" |
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default y |
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depends on !ARC_CANT_LLSC |
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config ARC_HAS_SWAPE |
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bool "Insn: SWAPE (endian-swap)" |
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default y |
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if ISA_ARCV2 |
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config ARC_USE_UNALIGNED_MEM_ACCESS |
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bool "Enable unaligned access in HW" |
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default y |
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select HAVE_EFFICIENT_UNALIGNED_ACCESS |
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help |
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The ARC HS architecture supports unaligned memory access |
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which is disabled by default. Enable unaligned access in |
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hardware and use software to use it |
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config ARC_HAS_LL64 |
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bool "Insn: 64bit LDD/STD" |
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help |
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Enable gcc to generate 64-bit load/store instructions |
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ISA mandates even/odd registers to allow encoding of two |
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dest operands with 2 possible source operands. |
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default y |
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config ARC_HAS_DIV_REM |
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bool "Insn: div, divu, rem, remu" |
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default y |
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config ARC_HAS_ACCL_REGS |
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bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)" |
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default y |
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help |
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Depending on the configuration, CPU can contain accumulator reg-pair |
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(also referred to as r58:r59). These can also be used by gcc as GPR so |
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kernel needs to save/restore per process |
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config ARC_DSP_HANDLED |
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def_bool n |
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config ARC_DSP_SAVE_RESTORE_REGS |
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def_bool n |
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choice |
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prompt "DSP support" |
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default ARC_DSP_NONE |
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help |
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Depending on the configuration, CPU can contain DSP registers |
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(ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL). |
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Bellow is options describing how to handle these registers in |
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interrupt entry / exit and in context switch. |
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config ARC_DSP_NONE |
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bool "No DSP extension presence in HW" |
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help |
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No DSP extension presence in HW |
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config ARC_DSP_KERNEL |
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bool "DSP extension in HW, no support for userspace" |
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select ARC_HAS_ACCL_REGS |
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select ARC_DSP_HANDLED |
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help |
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DSP extension presence in HW, no support for DSP-enabled userspace |
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applications. We don't save / restore DSP registers and only do |
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some minimal preparations so userspace won't be able to break kernel |
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config ARC_DSP_USERSPACE |
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bool "Support DSP for userspace apps" |
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select ARC_HAS_ACCL_REGS |
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select ARC_DSP_HANDLED |
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select ARC_DSP_SAVE_RESTORE_REGS |
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help |
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DSP extension presence in HW, support save / restore DSP registers to |
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run DSP-enabled userspace applications |
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config ARC_DSP_AGU_USERSPACE |
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bool "Support DSP with AGU for userspace apps" |
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select ARC_HAS_ACCL_REGS |
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select ARC_DSP_HANDLED |
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select ARC_DSP_SAVE_RESTORE_REGS |
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help |
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DSP and AGU extensions presence in HW, support save / restore DSP |
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and AGU registers to run DSP-enabled userspace applications |
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endchoice |
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config ARC_IRQ_NO_AUTOSAVE |
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bool "Disable hardware autosave regfile on interrupts" |
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default n |
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help |
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On HS cores, taken interrupt auto saves the regfile on stack. |
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This is programmable and can be optionally disabled in which case |
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software INTERRUPT_PROLOGUE/EPILGUE do the needed work |
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config ARC_LPB_DISABLE |
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bool "Disable loop buffer (LPB)" |
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help |
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On HS cores, loop buffer (LPB) is programmable in runtime and can |
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be optionally disabled. |
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endif # ISA_ARCV2 |
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endmenu # "ARC CPU Configuration" |
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config LINUX_LINK_BASE |
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hex "Kernel link address" |
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default "0x80000000" |
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help |
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ARC700 divides the 32 bit phy address space into two equal halves |
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-Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU |
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-Upper 2G (0x8000_0000 onwards) is untranslated, for kernel |
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Typically Linux kernel is linked at the start of untransalted addr, |
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hence the default value of 0x8zs. |
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However some customers have peripherals mapped at this addr, so |
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Linux needs to be scooted a bit. |
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If you don't know what the above means, leave this setting alone. |
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This needs to match memory start address specified in Device Tree |
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config LINUX_RAM_BASE |
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hex "RAM base address" |
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default LINUX_LINK_BASE |
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help |
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By default Linux is linked at base of RAM. However in some special |
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cases (such as HSDK), Linux can't be linked at start of DDR, hence |
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this option. |
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config HIGHMEM |
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bool "High Memory Support" |
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select HAVE_ARCH_PFN_VALID |
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select KMAP_LOCAL |
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help |
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With ARC 2G:2G address split, only upper 2G is directly addressable by |
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kernel. Enable this to potentially allow access to rest of 2G and PAE |
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in future |
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config ARC_HAS_PAE40 |
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bool "Support for the 40-bit Physical Address Extension" |
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depends on ISA_ARCV2 |
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select HIGHMEM |
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select PHYS_ADDR_T_64BIT |
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help |
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Enable access to physical memory beyond 4G, only supported on |
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ARC cores with 40 bit Physical Addressing support |
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config ARC_KVADDR_SIZE |
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int "Kernel Virtual Address Space size (MB)" |
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range 0 512 |
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default "256" |
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help |
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The kernel address space is carved out of 256MB of translated address |
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space for catering to vmalloc, modules, pkmap, fixmap. This however may |
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not suffice vmalloc requirements of a 4K CPU EZChip system. So allow |
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this to be stretched to 512 MB (by extending into the reserved |
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kernel-user gutter) |
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config ARC_CURR_IN_REG |
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bool "Dedicate Register r25 for current_task pointer" |
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default y |
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help |
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This reserved Register R25 to point to Current Task in |
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kernel mode. This saves memory access for each such access |
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config ARC_EMUL_UNALIGNED |
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bool "Emulate unaligned memory access (userspace only)" |
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select SYSCTL_ARCH_UNALIGN_NO_WARN |
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select SYSCTL_ARCH_UNALIGN_ALLOW |
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depends on ISA_ARCOMPACT |
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help |
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This enables misaligned 16 & 32 bit memory access from user space. |
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Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide |
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potential bugs in code |
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config HZ |
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int "Timer Frequency" |
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default 100 |
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config ARC_METAWARE_HLINK |
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bool "Support for Metaware debugger assisted Host access" |
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help |
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This options allows a Linux userland apps to directly access |
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host file system (open/creat/read/write etc) with help from |
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Metaware Debugger. This can come in handy for Linux-host communication |
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when there is no real usable peripheral such as EMAC. |
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menuconfig ARC_DBG |
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bool "ARC debugging" |
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default y |
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if ARC_DBG |
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config ARC_DW2_UNWIND |
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bool "Enable DWARF specific kernel stack unwind" |
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default y |
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select KALLSYMS |
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help |
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Compiles the kernel with DWARF unwind information and can be used |
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to get stack backtraces. |
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If you say Y here the resulting kernel image will be slightly larger |
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but not slower, and it will give very useful debugging information. |
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If you don't debug the kernel, you can say N, but we may not be able |
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to solve problems without frame unwind information |
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config ARC_DBG_TLB_PARANOIA |
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bool "Paranoia Checks in Low Level TLB Handlers" |
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config ARC_DBG_JUMP_LABEL |
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bool "Paranoid checks in Static Keys (jump labels) code" |
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depends on JUMP_LABEL |
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default y if STATIC_KEYS_SELFTEST |
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help |
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Enable paranoid checks and self-test of both ARC-specific and generic |
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part of static keys (jump labels) related code. |
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endif |
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config ARC_BUILTIN_DTB_NAME |
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string "Built in DTB" |
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help |
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Set the name of the DTB to embed in the vmlinux binary |
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Leaving it blank selects the minimal "skeleton" dtb |
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endmenu # "ARC Architecture Configuration" |
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config FORCE_MAX_ZONEORDER |
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int "Maximum zone order" |
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default "12" if ARC_HUGEPAGE_16M |
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default "11" |
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source "kernel/power/Kconfig"
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