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// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* linux/arch/alpha/kernel/sys_titan.c |
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* |
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* Copyright (C) 1995 David A Rusling |
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* Copyright (C) 1996, 1999 Jay A Estabrook |
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* Copyright (C) 1998, 1999 Richard Henderson |
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* Copyright (C) 1999, 2000 Jeff Wiedemeier |
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* |
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* Code supporting TITAN systems (EV6+TITAN), currently: |
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* Privateer |
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* Falcon |
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* Granite |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/mm.h> |
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#include <linux/sched.h> |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/bitops.h> |
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#include <asm/ptrace.h> |
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#include <asm/dma.h> |
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#include <asm/irq.h> |
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#include <asm/mmu_context.h> |
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#include <asm/io.h> |
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#include <asm/core_titan.h> |
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#include <asm/hwrpb.h> |
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#include <asm/tlbflush.h> |
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#include "proto.h" |
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#include "irq_impl.h" |
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#include "pci_impl.h" |
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#include "machvec_impl.h" |
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#include "err_impl.h" |
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/* |
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* Titan generic |
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*/ |
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/* |
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* Titan supports up to 4 CPUs |
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*/ |
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static unsigned long titan_cpu_irq_affinity[4] = { ~0UL, ~0UL, ~0UL, ~0UL }; |
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/* |
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* Mask is set (1) if enabled |
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*/ |
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static unsigned long titan_cached_irq_mask; |
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/* |
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* Need SMP-safe access to interrupt CSRs |
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*/ |
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DEFINE_SPINLOCK(titan_irq_lock); |
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static void |
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titan_update_irq_hw(unsigned long mask) |
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{ |
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register titan_cchip *cchip = TITAN_cchip; |
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unsigned long isa_enable = 1UL << 55; |
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register int bcpu = boot_cpuid; |
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#ifdef CONFIG_SMP |
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cpumask_t cpm; |
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volatile unsigned long *dim0, *dim1, *dim2, *dim3; |
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unsigned long mask0, mask1, mask2, mask3, dummy; |
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cpumask_copy(&cpm, cpu_present_mask); |
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mask &= ~isa_enable; |
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mask0 = mask & titan_cpu_irq_affinity[0]; |
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mask1 = mask & titan_cpu_irq_affinity[1]; |
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mask2 = mask & titan_cpu_irq_affinity[2]; |
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mask3 = mask & titan_cpu_irq_affinity[3]; |
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if (bcpu == 0) mask0 |= isa_enable; |
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else if (bcpu == 1) mask1 |= isa_enable; |
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else if (bcpu == 2) mask2 |= isa_enable; |
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else mask3 |= isa_enable; |
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dim0 = &cchip->dim0.csr; |
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dim1 = &cchip->dim1.csr; |
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dim2 = &cchip->dim2.csr; |
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dim3 = &cchip->dim3.csr; |
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if (!cpumask_test_cpu(0, &cpm)) dim0 = &dummy; |
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if (!cpumask_test_cpu(1, &cpm)) dim1 = &dummy; |
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if (!cpumask_test_cpu(2, &cpm)) dim2 = &dummy; |
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if (!cpumask_test_cpu(3, &cpm)) dim3 = &dummy; |
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*dim0 = mask0; |
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*dim1 = mask1; |
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*dim2 = mask2; |
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*dim3 = mask3; |
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mb(); |
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*dim0; |
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*dim1; |
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*dim2; |
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*dim3; |
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#else |
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volatile unsigned long *dimB; |
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dimB = &cchip->dim0.csr; |
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if (bcpu == 1) dimB = &cchip->dim1.csr; |
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else if (bcpu == 2) dimB = &cchip->dim2.csr; |
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else if (bcpu == 3) dimB = &cchip->dim3.csr; |
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*dimB = mask | isa_enable; |
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mb(); |
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*dimB; |
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#endif |
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} |
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static inline void |
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titan_enable_irq(struct irq_data *d) |
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{ |
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unsigned int irq = d->irq; |
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spin_lock(&titan_irq_lock); |
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titan_cached_irq_mask |= 1UL << (irq - 16); |
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titan_update_irq_hw(titan_cached_irq_mask); |
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spin_unlock(&titan_irq_lock); |
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} |
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static inline void |
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titan_disable_irq(struct irq_data *d) |
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{ |
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unsigned int irq = d->irq; |
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spin_lock(&titan_irq_lock); |
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titan_cached_irq_mask &= ~(1UL << (irq - 16)); |
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titan_update_irq_hw(titan_cached_irq_mask); |
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spin_unlock(&titan_irq_lock); |
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} |
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static void |
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titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity) |
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{ |
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int cpu; |
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for (cpu = 0; cpu < 4; cpu++) { |
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if (cpumask_test_cpu(cpu, &affinity)) |
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titan_cpu_irq_affinity[cpu] |= 1UL << irq; |
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else |
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titan_cpu_irq_affinity[cpu] &= ~(1UL << irq); |
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} |
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} |
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static int |
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titan_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, |
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bool force) |
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{ |
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unsigned int irq = d->irq; |
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spin_lock(&titan_irq_lock); |
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titan_cpu_set_irq_affinity(irq - 16, *affinity); |
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titan_update_irq_hw(titan_cached_irq_mask); |
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spin_unlock(&titan_irq_lock); |
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return 0; |
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} |
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static void |
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titan_device_interrupt(unsigned long vector) |
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{ |
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printk("titan_device_interrupt: NOT IMPLEMENTED YET!!\n"); |
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} |
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static void |
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titan_srm_device_interrupt(unsigned long vector) |
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{ |
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int irq; |
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irq = (vector - 0x800) >> 4; |
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handle_irq(irq); |
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} |
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static void __init |
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init_titan_irqs(struct irq_chip * ops, int imin, int imax) |
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{ |
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long i; |
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for (i = imin; i <= imax; ++i) { |
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irq_set_chip_and_handler(i, ops, handle_level_irq); |
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irq_set_status_flags(i, IRQ_LEVEL); |
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} |
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} |
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static struct irq_chip titan_irq_type = { |
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.name = "TITAN", |
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.irq_unmask = titan_enable_irq, |
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.irq_mask = titan_disable_irq, |
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.irq_mask_ack = titan_disable_irq, |
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.irq_set_affinity = titan_set_irq_affinity, |
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}; |
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static irqreturn_t |
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titan_intr_nop(int irq, void *dev_id) |
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{ |
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/* |
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* This is a NOP interrupt handler for the purposes of |
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* event counting -- just return. |
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*/ |
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return IRQ_HANDLED; |
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} |
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static void __init |
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titan_init_irq(void) |
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{ |
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if (alpha_using_srm && !alpha_mv.device_interrupt) |
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alpha_mv.device_interrupt = titan_srm_device_interrupt; |
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if (!alpha_mv.device_interrupt) |
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alpha_mv.device_interrupt = titan_device_interrupt; |
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titan_update_irq_hw(0); |
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init_titan_irqs(&titan_irq_type, 16, 63 + 16); |
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} |
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static void __init |
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titan_legacy_init_irq(void) |
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{ |
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/* init the legacy dma controller */ |
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outb(0, DMA1_RESET_REG); |
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outb(0, DMA2_RESET_REG); |
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outb(DMA_MODE_CASCADE, DMA2_MODE_REG); |
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outb(0, DMA2_MASK_REG); |
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/* init the legacy irq controller */ |
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init_i8259a_irqs(); |
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/* init the titan irqs */ |
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titan_init_irq(); |
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} |
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void |
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titan_dispatch_irqs(u64 mask) |
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{ |
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unsigned long vector; |
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/* |
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* Mask down to those interrupts which are enable on this processor |
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*/ |
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mask &= titan_cpu_irq_affinity[smp_processor_id()]; |
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/* |
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* Dispatch all requested interrupts |
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*/ |
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while (mask) { |
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/* convert to SRM vector... priority is <63> -> <0> */ |
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vector = 63 - __kernel_ctlz(mask); |
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mask &= ~(1UL << vector); /* clear it out */ |
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vector = 0x900 + (vector << 4); /* convert to SRM vector */ |
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/* dispatch it */ |
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alpha_mv.device_interrupt(vector); |
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} |
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} |
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/* |
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* Titan Family |
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*/ |
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static void __init |
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titan_request_irq(unsigned int irq, irq_handler_t handler, |
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unsigned long irqflags, const char *devname, |
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void *dev_id) |
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{ |
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int err; |
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err = request_irq(irq, handler, irqflags, devname, dev_id); |
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if (err) { |
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printk("titan_request_irq for IRQ %d returned %d; ignoring\n", |
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irq, err); |
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} |
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} |
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static void __init |
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titan_late_init(void) |
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{ |
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/* |
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* Enable the system error interrupts. These interrupts are |
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* all reported to the kernel as machine checks, so the handler |
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* is a nop so it can be called to count the individual events. |
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*/ |
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titan_request_irq(63+16, titan_intr_nop, 0, |
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"CChip Error", NULL); |
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titan_request_irq(62+16, titan_intr_nop, 0, |
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"PChip 0 H_Error", NULL); |
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titan_request_irq(61+16, titan_intr_nop, 0, |
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"PChip 1 H_Error", NULL); |
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titan_request_irq(60+16, titan_intr_nop, 0, |
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"PChip 0 C_Error", NULL); |
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titan_request_irq(59+16, titan_intr_nop, 0, |
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"PChip 1 C_Error", NULL); |
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/* |
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* Register our error handlers. |
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*/ |
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titan_register_error_handlers(); |
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/* |
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* Check if the console left us any error logs. |
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*/ |
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cdl_check_console_data_log(); |
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} |
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static int |
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titan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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u8 intline; |
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int irq; |
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/* Get the current intline. */ |
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pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline); |
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irq = intline; |
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/* Is it explicitly routed through ISA? */ |
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if ((irq & 0xF0) == 0xE0) |
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return irq; |
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/* Offset by 16 to make room for ISA interrupts 0 - 15. */ |
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return irq + 16; |
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} |
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static void __init |
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titan_init_pci(void) |
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{ |
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/* |
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* This isn't really the right place, but there's some init |
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* that needs to be done after everything is basically up. |
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*/ |
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titan_late_init(); |
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/* Indicate that we trust the console to configure things properly */ |
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pci_set_flags(PCI_PROBE_ONLY); |
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common_init_pci(); |
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SMC669_Init(0); |
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locate_and_init_vga(NULL); |
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} |
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/* |
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* Privateer |
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*/ |
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static void __init |
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privateer_init_pci(void) |
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{ |
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/* |
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* Hook a couple of extra err interrupts that the |
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* common titan code won't. |
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*/ |
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titan_request_irq(53+16, titan_intr_nop, 0, |
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"NMI", NULL); |
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titan_request_irq(50+16, titan_intr_nop, 0, |
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"Temperature Warning", NULL); |
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/* |
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* Finish with the common version. |
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*/ |
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return titan_init_pci(); |
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} |
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/* |
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* The System Vectors. |
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*/ |
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struct alpha_machine_vector titan_mv __initmv = { |
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.vector_name = "TITAN", |
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DO_EV6_MMU, |
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DO_DEFAULT_RTC, |
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DO_TITAN_IO, |
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.machine_check = titan_machine_check, |
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
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.min_io_address = DEFAULT_IO_BASE, |
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.min_mem_address = DEFAULT_MEM_BASE, |
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.pci_dac_offset = TITAN_DAC_OFFSET, |
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.nr_irqs = 80, /* 64 + 16 */ |
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/* device_interrupt will be filled in by titan_init_irq */ |
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.agp_info = titan_agp_info, |
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.init_arch = titan_init_arch, |
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.init_irq = titan_legacy_init_irq, |
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.init_rtc = common_init_rtc, |
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.init_pci = titan_init_pci, |
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.kill_arch = titan_kill_arch, |
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.pci_map_irq = titan_map_irq, |
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.pci_swizzle = common_swizzle, |
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}; |
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ALIAS_MV(titan) |
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struct alpha_machine_vector privateer_mv __initmv = { |
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.vector_name = "PRIVATEER", |
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DO_EV6_MMU, |
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DO_DEFAULT_RTC, |
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DO_TITAN_IO, |
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.machine_check = privateer_machine_check, |
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
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.min_io_address = DEFAULT_IO_BASE, |
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.min_mem_address = DEFAULT_MEM_BASE, |
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.pci_dac_offset = TITAN_DAC_OFFSET, |
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.nr_irqs = 80, /* 64 + 16 */ |
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/* device_interrupt will be filled in by titan_init_irq */ |
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.agp_info = titan_agp_info, |
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.init_arch = titan_init_arch, |
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.init_irq = titan_legacy_init_irq, |
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.init_rtc = common_init_rtc, |
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.init_pci = privateer_init_pci, |
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.kill_arch = titan_kill_arch, |
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.pci_map_irq = titan_map_irq, |
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.pci_swizzle = common_swizzle, |
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}; |
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/* No alpha_mv alias for privateer since we compile it |
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in unconditionally with titan; setup_arch knows how to cope. */
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