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336 lines
9.0 KiB
336 lines
9.0 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* linux/arch/alpha/kernel/sys_noritake.c |
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* |
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* Copyright (C) 1995 David A Rusling |
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* Copyright (C) 1996 Jay A Estabrook |
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* Copyright (C) 1998, 1999 Richard Henderson |
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* |
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* Code supporting the NORITAKE (AlphaServer 1000A), |
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* CORELLE (AlphaServer 800), and ALCOR Primo (AlphaStation 600A). |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/mm.h> |
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#include <linux/sched.h> |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/bitops.h> |
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#include <asm/ptrace.h> |
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#include <asm/mce.h> |
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#include <asm/dma.h> |
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#include <asm/irq.h> |
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#include <asm/mmu_context.h> |
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#include <asm/io.h> |
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#include <asm/core_apecs.h> |
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#include <asm/core_cia.h> |
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#include <asm/tlbflush.h> |
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#include "proto.h" |
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#include "irq_impl.h" |
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#include "pci_impl.h" |
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#include "machvec_impl.h" |
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/* Note mask bit is true for ENABLED irqs. */ |
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static int cached_irq_mask; |
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static inline void |
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noritake_update_irq_hw(int irq, int mask) |
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{ |
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int port = 0x54a; |
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if (irq >= 32) { |
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mask >>= 16; |
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port = 0x54c; |
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} |
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outw(mask, port); |
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} |
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static void |
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noritake_enable_irq(struct irq_data *d) |
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{ |
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noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16)); |
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} |
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static void |
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noritake_disable_irq(struct irq_data *d) |
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{ |
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noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16))); |
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} |
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static struct irq_chip noritake_irq_type = { |
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.name = "NORITAKE", |
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.irq_unmask = noritake_enable_irq, |
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.irq_mask = noritake_disable_irq, |
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.irq_mask_ack = noritake_disable_irq, |
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}; |
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static void |
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noritake_device_interrupt(unsigned long vector) |
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{ |
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unsigned long pld; |
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unsigned int i; |
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/* Read the interrupt summary registers of NORITAKE */ |
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pld = (((unsigned long) inw(0x54c) << 32) |
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| ((unsigned long) inw(0x54a) << 16) |
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| ((unsigned long) inb(0xa0) << 8) |
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| inb(0x20)); |
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/* |
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* Now for every possible bit set, work through them and call |
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* the appropriate interrupt handler. |
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*/ |
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while (pld) { |
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i = ffz(~pld); |
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pld &= pld - 1; /* clear least bit set */ |
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if (i < 16) { |
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isa_device_interrupt(vector); |
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} else { |
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handle_irq(i); |
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} |
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} |
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} |
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static void |
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noritake_srm_device_interrupt(unsigned long vector) |
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{ |
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int irq; |
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irq = (vector - 0x800) >> 4; |
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/* |
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* I really hate to do this, too, but the NORITAKE SRM console also |
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* reports PCI vectors *lower* than I expected from the bit numbers |
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* in the documentation. |
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* But I really don't want to change the fixup code for allocation |
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* of IRQs, nor the alpha_irq_mask maintenance stuff, both of which |
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* look nice and clean now. |
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* So, here's this additional grotty hack... :-( |
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*/ |
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if (irq >= 16) |
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irq = irq + 1; |
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handle_irq(irq); |
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} |
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static void __init |
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noritake_init_irq(void) |
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{ |
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long i; |
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if (alpha_using_srm) |
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alpha_mv.device_interrupt = noritake_srm_device_interrupt; |
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outw(0, 0x54a); |
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outw(0, 0x54c); |
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for (i = 16; i < 48; ++i) { |
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irq_set_chip_and_handler(i, &noritake_irq_type, |
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handle_level_irq); |
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irq_set_status_flags(i, IRQ_LEVEL); |
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} |
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init_i8259a_irqs(); |
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common_init_isa_dma(); |
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} |
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/* |
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* PCI Fixup configuration. |
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* |
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* Summary @ 0x542, summary register #1: |
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* Bit Meaning |
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* 0 All valid ints from summary regs 2 & 3 |
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* 1 QLOGIC ISP1020A SCSI |
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* 2 Interrupt Line A from slot 0 |
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* 3 Interrupt Line B from slot 0 |
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* 4 Interrupt Line A from slot 1 |
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* 5 Interrupt line B from slot 1 |
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* 6 Interrupt Line A from slot 2 |
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* 7 Interrupt Line B from slot 2 |
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* 8 Interrupt Line A from slot 3 |
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* 9 Interrupt Line B from slot 3 |
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*10 Interrupt Line A from slot 4 |
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*11 Interrupt Line B from slot 4 |
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*12 Interrupt Line A from slot 5 |
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*13 Interrupt Line B from slot 5 |
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*14 Interrupt Line A from slot 6 |
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*15 Interrupt Line B from slot 6 |
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* |
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* Summary @ 0x544, summary register #2: |
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* Bit Meaning |
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* 0 OR of all unmasked ints in SR #2 |
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* 1 OR of secondary bus ints |
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* 2 Interrupt Line C from slot 0 |
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* 3 Interrupt Line D from slot 0 |
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* 4 Interrupt Line C from slot 1 |
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* 5 Interrupt line D from slot 1 |
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* 6 Interrupt Line C from slot 2 |
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* 7 Interrupt Line D from slot 2 |
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* 8 Interrupt Line C from slot 3 |
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* 9 Interrupt Line D from slot 3 |
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*10 Interrupt Line C from slot 4 |
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*11 Interrupt Line D from slot 4 |
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*12 Interrupt Line C from slot 5 |
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*13 Interrupt Line D from slot 5 |
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*14 Interrupt Line C from slot 6 |
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*15 Interrupt Line D from slot 6 |
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* |
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* The device to slot mapping looks like: |
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* |
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* Slot Device |
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* 7 Intel PCI-EISA bridge chip |
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* 8 DEC PCI-PCI bridge chip |
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* 11 PCI on board slot 0 |
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* 12 PCI on board slot 1 |
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* 13 PCI on board slot 2 |
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* |
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* |
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* This two layered interrupt approach means that we allocate IRQ 16 and |
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* above for PCI interrupts. The IRQ relates to which bit the interrupt |
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* comes in on. This makes interrupt processing much easier. |
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*/ |
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static int |
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noritake_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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static char irq_tab[15][5] = { |
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/*INT INTA INTB INTC INTD */ |
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/* note: IDSELs 16, 17, and 25 are CORELLE only */ |
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{ 16+1, 16+1, 16+1, 16+1, 16+1}, /* IdSel 16, QLOGIC */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 17, S3 Trio64 */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 18, PCEB */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 19, PPB */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 20, ???? */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 21, ???? */ |
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{ 16+2, 16+2, 16+3, 32+2, 32+3}, /* IdSel 22, slot 0 */ |
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{ 16+4, 16+4, 16+5, 32+4, 32+5}, /* IdSel 23, slot 1 */ |
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{ 16+6, 16+6, 16+7, 32+6, 32+7}, /* IdSel 24, slot 2 */ |
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{ 16+8, 16+8, 16+9, 32+8, 32+9}, /* IdSel 25, slot 3 */ |
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/* The following 5 are actually on PCI bus 1, which is |
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across the built-in bridge of the NORITAKE only. */ |
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{ 16+1, 16+1, 16+1, 16+1, 16+1}, /* IdSel 16, QLOGIC */ |
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{ 16+8, 16+8, 16+9, 32+8, 32+9}, /* IdSel 17, slot 3 */ |
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{16+10, 16+10, 16+11, 32+10, 32+11}, /* IdSel 18, slot 4 */ |
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{16+12, 16+12, 16+13, 32+12, 32+13}, /* IdSel 19, slot 5 */ |
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{16+14, 16+14, 16+15, 32+14, 32+15}, /* IdSel 20, slot 6 */ |
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}; |
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const long min_idsel = 5, max_idsel = 19, irqs_per_slot = 5; |
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return COMMON_TABLE_LOOKUP; |
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} |
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static u8 |
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noritake_swizzle(struct pci_dev *dev, u8 *pinp) |
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{ |
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int slot, pin = *pinp; |
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if (dev->bus->number == 0) { |
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slot = PCI_SLOT(dev->devfn); |
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} |
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/* Check for the built-in bridge */ |
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else if (PCI_SLOT(dev->bus->self->devfn) == 8) { |
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slot = PCI_SLOT(dev->devfn) + 15; /* WAG! */ |
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} |
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else |
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{ |
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/* Must be a card-based bridge. */ |
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do { |
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if (PCI_SLOT(dev->bus->self->devfn) == 8) { |
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slot = PCI_SLOT(dev->devfn) + 15; |
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break; |
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} |
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pin = pci_swizzle_interrupt_pin(dev, pin); |
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/* Move up the chain of bridges. */ |
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dev = dev->bus->self; |
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/* Slot of the next bridge. */ |
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slot = PCI_SLOT(dev->devfn); |
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} while (dev->bus->self); |
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} |
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*pinp = pin; |
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return slot; |
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} |
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#if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO) |
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static void |
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noritake_apecs_machine_check(unsigned long vector, unsigned long la_ptr) |
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{ |
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#define MCHK_NO_DEVSEL 0x205U |
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#define MCHK_NO_TABT 0x204U |
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struct el_common *mchk_header; |
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unsigned int code; |
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mchk_header = (struct el_common *)la_ptr; |
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/* Clear the error before any reporting. */ |
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mb(); |
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mb(); /* magic */ |
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draina(); |
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apecs_pci_clr_err(); |
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wrmces(0x7); |
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mb(); |
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code = mchk_header->code; |
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process_mcheck_info(vector, la_ptr, "NORITAKE APECS", |
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(mcheck_expected(0) |
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&& (code == MCHK_NO_DEVSEL |
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|| code == MCHK_NO_TABT))); |
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} |
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#endif |
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/* |
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* The System Vectors |
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*/ |
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#if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO) |
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struct alpha_machine_vector noritake_mv __initmv = { |
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.vector_name = "Noritake", |
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DO_EV4_MMU, |
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DO_DEFAULT_RTC, |
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DO_APECS_IO, |
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.machine_check = noritake_apecs_machine_check, |
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
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.min_io_address = EISA_DEFAULT_IO_BASE, |
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.min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, |
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.nr_irqs = 48, |
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.device_interrupt = noritake_device_interrupt, |
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.init_arch = apecs_init_arch, |
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.init_irq = noritake_init_irq, |
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.init_rtc = common_init_rtc, |
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.init_pci = common_init_pci, |
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.pci_map_irq = noritake_map_irq, |
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.pci_swizzle = noritake_swizzle, |
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}; |
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ALIAS_MV(noritake) |
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#endif |
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO) |
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struct alpha_machine_vector noritake_primo_mv __initmv = { |
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.vector_name = "Noritake-Primo", |
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DO_EV5_MMU, |
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DO_DEFAULT_RTC, |
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DO_CIA_IO, |
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.machine_check = cia_machine_check, |
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
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.min_io_address = EISA_DEFAULT_IO_BASE, |
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.min_mem_address = CIA_DEFAULT_MEM_BASE, |
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.nr_irqs = 48, |
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.device_interrupt = noritake_device_interrupt, |
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.init_arch = cia_init_arch, |
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.init_irq = noritake_init_irq, |
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.init_rtc = common_init_rtc, |
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.init_pci = cia_init_pci, |
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.kill_arch = cia_kill_arch, |
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.pci_map_irq = noritake_map_irq, |
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.pci_swizzle = noritake_swizzle, |
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}; |
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ALIAS_MV(noritake_primo) |
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#endif
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