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// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* linux/arch/alpha/kernel/sys_marvel.c |
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* |
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* Marvel / IO7 support |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/mm.h> |
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#include <linux/sched.h> |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/bitops.h> |
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#include <asm/ptrace.h> |
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#include <asm/dma.h> |
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#include <asm/irq.h> |
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#include <asm/mmu_context.h> |
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#include <asm/io.h> |
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#include <asm/core_marvel.h> |
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#include <asm/hwrpb.h> |
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#include <asm/tlbflush.h> |
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#include <asm/vga.h> |
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#include "proto.h" |
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#include "err_impl.h" |
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#include "irq_impl.h" |
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#include "pci_impl.h" |
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#include "machvec_impl.h" |
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#if NR_IRQS < MARVEL_NR_IRQS |
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# error NR_IRQS < MARVEL_NR_IRQS !!! |
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#endif |
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/* |
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* Interrupt handling. |
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*/ |
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static void |
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io7_device_interrupt(unsigned long vector) |
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{ |
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unsigned int pid; |
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unsigned int irq; |
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/* |
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* Vector is 0x800 + (interrupt) |
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* |
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* where (interrupt) is: |
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* |
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* ...16|15 14|13 4|3 0 |
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* -----+-----+--------+--- |
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* PE | 0 | irq | 0 |
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* |
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* where (irq) is |
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* |
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* 0x0800 - 0x0ff0 - 0x0800 + (LSI id << 4) |
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* 0x1000 - 0x2ff0 - 0x1000 + (MSI_DAT<8:0> << 4) |
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*/ |
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pid = vector >> 16; |
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irq = ((vector & 0xffff) - 0x800) >> 4; |
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irq += 16; /* offset for legacy */ |
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irq &= MARVEL_IRQ_VEC_IRQ_MASK; /* not too many bits */ |
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irq |= pid << MARVEL_IRQ_VEC_PE_SHIFT; /* merge the pid */ |
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handle_irq(irq); |
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} |
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static volatile unsigned long * |
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io7_get_irq_ctl(unsigned int irq, struct io7 **pio7) |
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{ |
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volatile unsigned long *ctl; |
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unsigned int pid; |
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struct io7 *io7; |
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pid = irq >> MARVEL_IRQ_VEC_PE_SHIFT; |
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if (!(io7 = marvel_find_io7(pid))) { |
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printk(KERN_ERR |
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"%s for nonexistent io7 -- vec %x, pid %d\n", |
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__func__, irq, pid); |
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return NULL; |
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} |
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irq &= MARVEL_IRQ_VEC_IRQ_MASK; /* isolate the vector */ |
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irq -= 16; /* subtract legacy bias */ |
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if (irq >= 0x180) { |
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printk(KERN_ERR |
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"%s for invalid irq -- pid %d adjusted irq %x\n", |
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__func__, pid, irq); |
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return NULL; |
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} |
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ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ |
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if (irq >= 0x80) /* MSI */ |
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ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr; |
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if (pio7) *pio7 = io7; |
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return ctl; |
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} |
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static void |
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io7_enable_irq(struct irq_data *d) |
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{ |
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volatile unsigned long *ctl; |
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unsigned int irq = d->irq; |
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struct io7 *io7; |
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ctl = io7_get_irq_ctl(irq, &io7); |
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if (!ctl || !io7) { |
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printk(KERN_ERR "%s: get_ctl failed for irq %x\n", |
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__func__, irq); |
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return; |
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} |
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raw_spin_lock(&io7->irq_lock); |
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*ctl |= 1UL << 24; |
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mb(); |
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*ctl; |
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raw_spin_unlock(&io7->irq_lock); |
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} |
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static void |
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io7_disable_irq(struct irq_data *d) |
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{ |
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volatile unsigned long *ctl; |
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unsigned int irq = d->irq; |
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struct io7 *io7; |
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ctl = io7_get_irq_ctl(irq, &io7); |
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if (!ctl || !io7) { |
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printk(KERN_ERR "%s: get_ctl failed for irq %x\n", |
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__func__, irq); |
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return; |
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} |
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raw_spin_lock(&io7->irq_lock); |
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*ctl &= ~(1UL << 24); |
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mb(); |
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*ctl; |
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raw_spin_unlock(&io7->irq_lock); |
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} |
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static void |
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marvel_irq_noop(struct irq_data *d) |
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{ |
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return; |
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} |
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static struct irq_chip marvel_legacy_irq_type = { |
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.name = "LEGACY", |
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.irq_mask = marvel_irq_noop, |
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.irq_unmask = marvel_irq_noop, |
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}; |
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static struct irq_chip io7_lsi_irq_type = { |
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.name = "LSI", |
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.irq_unmask = io7_enable_irq, |
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.irq_mask = io7_disable_irq, |
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.irq_mask_ack = io7_disable_irq, |
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}; |
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static struct irq_chip io7_msi_irq_type = { |
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.name = "MSI", |
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.irq_unmask = io7_enable_irq, |
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.irq_mask = io7_disable_irq, |
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.irq_ack = marvel_irq_noop, |
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}; |
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static void |
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io7_redirect_irq(struct io7 *io7, |
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volatile unsigned long *csr, |
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unsigned int where) |
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{ |
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unsigned long val; |
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val = *csr; |
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val &= ~(0x1ffUL << 24); /* clear the target pid */ |
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val |= ((unsigned long)where << 24); /* set the new target pid */ |
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*csr = val; |
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mb(); |
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*csr; |
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} |
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static void |
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io7_redirect_one_lsi(struct io7 *io7, unsigned int which, unsigned int where) |
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{ |
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unsigned long val; |
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/* |
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* LSI_CTL has target PID @ 14 |
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*/ |
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val = io7->csrs->PO7_LSI_CTL[which].csr; |
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val &= ~(0x1ffUL << 14); /* clear the target pid */ |
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val |= ((unsigned long)where << 14); /* set the new target pid */ |
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io7->csrs->PO7_LSI_CTL[which].csr = val; |
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mb(); |
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io7->csrs->PO7_LSI_CTL[which].csr; |
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} |
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static void |
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io7_redirect_one_msi(struct io7 *io7, unsigned int which, unsigned int where) |
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{ |
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unsigned long val; |
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/* |
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* MSI_CTL has target PID @ 14 |
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*/ |
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val = io7->csrs->PO7_MSI_CTL[which].csr; |
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val &= ~(0x1ffUL << 14); /* clear the target pid */ |
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val |= ((unsigned long)where << 14); /* set the new target pid */ |
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io7->csrs->PO7_MSI_CTL[which].csr = val; |
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mb(); |
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io7->csrs->PO7_MSI_CTL[which].csr; |
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} |
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static void __init |
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init_one_io7_lsi(struct io7 *io7, unsigned int which, unsigned int where) |
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{ |
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/* |
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* LSI_CTL has target PID @ 14 |
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*/ |
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io7->csrs->PO7_LSI_CTL[which].csr = ((unsigned long)where << 14); |
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mb(); |
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io7->csrs->PO7_LSI_CTL[which].csr; |
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} |
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static void __init |
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init_one_io7_msi(struct io7 *io7, unsigned int which, unsigned int where) |
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{ |
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/* |
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* MSI_CTL has target PID @ 14 |
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*/ |
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io7->csrs->PO7_MSI_CTL[which].csr = ((unsigned long)where << 14); |
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mb(); |
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io7->csrs->PO7_MSI_CTL[which].csr; |
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} |
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static void __init |
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init_io7_irqs(struct io7 *io7, |
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struct irq_chip *lsi_ops, |
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struct irq_chip *msi_ops) |
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{ |
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long base = (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT) + 16; |
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long i; |
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printk("Initializing interrupts for IO7 at PE %u - base %lx\n", |
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io7->pe, base); |
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/* |
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* Where should interrupts from this IO7 go? |
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* |
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* They really should be sent to the local CPU to avoid having to |
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* traverse the mesh, but if it's not an SMP kernel, they have to |
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* go to the boot CPU. Send them all to the boot CPU for now, |
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* as each secondary starts, it can redirect it's local device |
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* interrupts. |
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*/ |
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printk(" Interrupts reported to CPU at PE %u\n", boot_cpuid); |
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raw_spin_lock(&io7->irq_lock); |
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/* set up the error irqs */ |
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io7_redirect_irq(io7, &io7->csrs->HLT_CTL.csr, boot_cpuid); |
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io7_redirect_irq(io7, &io7->csrs->HPI_CTL.csr, boot_cpuid); |
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io7_redirect_irq(io7, &io7->csrs->CRD_CTL.csr, boot_cpuid); |
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io7_redirect_irq(io7, &io7->csrs->STV_CTL.csr, boot_cpuid); |
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io7_redirect_irq(io7, &io7->csrs->HEI_CTL.csr, boot_cpuid); |
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/* Set up the lsi irqs. */ |
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for (i = 0; i < 128; ++i) { |
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irq_set_chip_and_handler(base + i, lsi_ops, handle_level_irq); |
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irq_set_status_flags(i, IRQ_LEVEL); |
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} |
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/* Disable the implemented irqs in hardware. */ |
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for (i = 0; i < 0x60; ++i) |
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init_one_io7_lsi(io7, i, boot_cpuid); |
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init_one_io7_lsi(io7, 0x74, boot_cpuid); |
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init_one_io7_lsi(io7, 0x75, boot_cpuid); |
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/* Set up the msi irqs. */ |
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for (i = 128; i < (128 + 512); ++i) { |
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irq_set_chip_and_handler(base + i, msi_ops, handle_level_irq); |
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irq_set_status_flags(i, IRQ_LEVEL); |
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} |
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for (i = 0; i < 16; ++i) |
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init_one_io7_msi(io7, i, boot_cpuid); |
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raw_spin_unlock(&io7->irq_lock); |
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} |
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static void __init |
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marvel_init_irq(void) |
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{ |
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int i; |
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struct io7 *io7 = NULL; |
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/* Reserve the legacy irqs. */ |
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for (i = 0; i < 16; ++i) { |
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irq_set_chip_and_handler(i, &marvel_legacy_irq_type, |
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handle_level_irq); |
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} |
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/* Init the io7 irqs. */ |
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for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; ) |
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init_io7_irqs(io7, &io7_lsi_irq_type, &io7_msi_irq_type); |
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} |
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static int |
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marvel_map_irq(const struct pci_dev *cdev, u8 slot, u8 pin) |
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{ |
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struct pci_dev *dev = (struct pci_dev *)cdev; |
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struct pci_controller *hose = dev->sysdata; |
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struct io7_port *io7_port = hose->sysdata; |
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struct io7 *io7 = io7_port->io7; |
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int msi_loc, msi_data_off; |
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u16 msg_ctl; |
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u16 msg_dat; |
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u8 intline; |
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int irq; |
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pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline); |
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irq = intline; |
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msi_loc = dev->msi_cap; |
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msg_ctl = 0; |
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if (msi_loc) |
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pci_read_config_word(dev, msi_loc + PCI_MSI_FLAGS, &msg_ctl); |
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if (msg_ctl & PCI_MSI_FLAGS_ENABLE) { |
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msi_data_off = PCI_MSI_DATA_32; |
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if (msg_ctl & PCI_MSI_FLAGS_64BIT) |
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msi_data_off = PCI_MSI_DATA_64; |
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pci_read_config_word(dev, msi_loc + msi_data_off, &msg_dat); |
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irq = msg_dat & 0x1ff; /* we use msg_data<8:0> */ |
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irq += 0x80; /* offset for lsi */ |
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#if 1 |
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printk("PCI:%d:%d:%d (hose %d) is using MSI\n", |
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dev->bus->number, |
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PCI_SLOT(dev->devfn), |
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PCI_FUNC(dev->devfn), |
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hose->index); |
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printk(" %d message(s) from 0x%04x\n", |
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1 << ((msg_ctl & PCI_MSI_FLAGS_QSIZE) >> 4), |
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msg_dat); |
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printk(" reporting on %d IRQ(s) from %d (0x%x)\n", |
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1 << ((msg_ctl & PCI_MSI_FLAGS_QSIZE) >> 4), |
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(irq + 16) | (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT), |
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(irq + 16) | (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT)); |
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#endif |
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#if 0 |
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pci_write_config_word(dev, msi_loc + PCI_MSI_FLAGS, |
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msg_ctl & ~PCI_MSI_FLAGS_ENABLE); |
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pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline); |
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irq = intline; |
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printk(" forcing LSI interrupt on irq %d [0x%x]\n", irq, irq); |
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#endif |
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} |
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irq += 16; /* offset for legacy */ |
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irq |= io7->pe << MARVEL_IRQ_VEC_PE_SHIFT; /* merge the pid */ |
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return irq; |
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} |
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static void __init |
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marvel_init_pci(void) |
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{ |
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struct io7 *io7; |
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marvel_register_error_handlers(); |
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/* Indicate that we trust the console to configure things properly */ |
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pci_set_flags(PCI_PROBE_ONLY); |
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common_init_pci(); |
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locate_and_init_vga(NULL); |
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/* Clear any io7 errors. */ |
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for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; ) |
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io7_clear_errors(io7); |
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} |
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static void __init |
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marvel_init_rtc(void) |
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{ |
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init_rtc_irq(NULL); |
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} |
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static void |
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marvel_smp_callin(void) |
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{ |
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int cpuid = hard_smp_processor_id(); |
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struct io7 *io7 = marvel_find_io7(cpuid); |
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unsigned int i; |
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if (!io7) |
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return; |
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/* |
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* There is a local IO7 - redirect all of its interrupts here. |
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*/ |
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printk("Redirecting IO7 interrupts to local CPU at PE %u\n", cpuid); |
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/* Redirect the error IRQS here. */ |
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io7_redirect_irq(io7, &io7->csrs->HLT_CTL.csr, cpuid); |
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io7_redirect_irq(io7, &io7->csrs->HPI_CTL.csr, cpuid); |
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io7_redirect_irq(io7, &io7->csrs->CRD_CTL.csr, cpuid); |
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io7_redirect_irq(io7, &io7->csrs->STV_CTL.csr, cpuid); |
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io7_redirect_irq(io7, &io7->csrs->HEI_CTL.csr, cpuid); |
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/* Redirect the implemented LSIs here. */ |
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for (i = 0; i < 0x60; ++i) |
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io7_redirect_one_lsi(io7, i, cpuid); |
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io7_redirect_one_lsi(io7, 0x74, cpuid); |
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io7_redirect_one_lsi(io7, 0x75, cpuid); |
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/* Redirect the MSIs here. */ |
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for (i = 0; i < 16; ++i) |
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io7_redirect_one_msi(io7, i, cpuid); |
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} |
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/* |
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* System Vectors |
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*/ |
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struct alpha_machine_vector marvel_ev7_mv __initmv = { |
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.vector_name = "MARVEL/EV7", |
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DO_EV7_MMU, |
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.rtc_port = 0x70, |
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.rtc_boot_cpu_only = 1, |
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DO_MARVEL_IO, |
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.machine_check = marvel_machine_check, |
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
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.min_io_address = DEFAULT_IO_BASE, |
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.min_mem_address = DEFAULT_MEM_BASE, |
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.pci_dac_offset = IO7_DAC_OFFSET, |
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.nr_irqs = MARVEL_NR_IRQS, |
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.device_interrupt = io7_device_interrupt, |
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.agp_info = marvel_agp_info, |
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.smp_callin = marvel_smp_callin, |
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.init_arch = marvel_init_arch, |
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.init_irq = marvel_init_irq, |
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.init_rtc = marvel_init_rtc, |
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.init_pci = marvel_init_pci, |
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.kill_arch = marvel_kill_arch, |
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.pci_map_irq = marvel_map_irq, |
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.pci_swizzle = common_swizzle, |
|
|
|
|
|
.pa_to_nid = marvel_pa_to_nid, |
|
|
.cpuid_to_nid = marvel_cpuid_to_nid, |
|
|
.node_mem_start = marvel_node_mem_start, |
|
|
.node_mem_size = marvel_node_mem_size, |
|
|
}; |
|
|
ALIAS_MV(marvel_ev7)
|
|
|
|