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665 lines
17 KiB
665 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* linux/arch/alpha/kernel/sys_dp264.c |
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* |
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* Copyright (C) 1995 David A Rusling |
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* Copyright (C) 1996, 1999 Jay A Estabrook |
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* Copyright (C) 1998, 1999 Richard Henderson |
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* |
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* Modified by Christopher C. Chimelis, 2001 to |
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* add support for the addition of Shark to the |
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* Tsunami family. |
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* |
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* Code supporting the DP264 (EV6+TSUNAMI). |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/mm.h> |
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#include <linux/sched.h> |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/bitops.h> |
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#include <asm/ptrace.h> |
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#include <asm/dma.h> |
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#include <asm/irq.h> |
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#include <asm/mmu_context.h> |
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#include <asm/io.h> |
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#include <asm/core_tsunami.h> |
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#include <asm/hwrpb.h> |
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#include <asm/tlbflush.h> |
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#include "proto.h" |
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#include "irq_impl.h" |
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#include "pci_impl.h" |
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#include "machvec_impl.h" |
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/* Note mask bit is true for ENABLED irqs. */ |
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static unsigned long cached_irq_mask; |
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/* dp264 boards handle at max four CPUs */ |
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static unsigned long cpu_irq_affinity[4] = { 0UL, 0UL, 0UL, 0UL }; |
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DEFINE_SPINLOCK(dp264_irq_lock); |
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static void |
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tsunami_update_irq_hw(unsigned long mask) |
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{ |
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register tsunami_cchip *cchip = TSUNAMI_cchip; |
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unsigned long isa_enable = 1UL << 55; |
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register int bcpu = boot_cpuid; |
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#ifdef CONFIG_SMP |
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volatile unsigned long *dim0, *dim1, *dim2, *dim3; |
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unsigned long mask0, mask1, mask2, mask3, dummy; |
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mask &= ~isa_enable; |
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mask0 = mask & cpu_irq_affinity[0]; |
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mask1 = mask & cpu_irq_affinity[1]; |
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mask2 = mask & cpu_irq_affinity[2]; |
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mask3 = mask & cpu_irq_affinity[3]; |
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if (bcpu == 0) mask0 |= isa_enable; |
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else if (bcpu == 1) mask1 |= isa_enable; |
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else if (bcpu == 2) mask2 |= isa_enable; |
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else mask3 |= isa_enable; |
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dim0 = &cchip->dim0.csr; |
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dim1 = &cchip->dim1.csr; |
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dim2 = &cchip->dim2.csr; |
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dim3 = &cchip->dim3.csr; |
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if (!cpu_possible(0)) dim0 = &dummy; |
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if (!cpu_possible(1)) dim1 = &dummy; |
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if (!cpu_possible(2)) dim2 = &dummy; |
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if (!cpu_possible(3)) dim3 = &dummy; |
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*dim0 = mask0; |
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*dim1 = mask1; |
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*dim2 = mask2; |
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*dim3 = mask3; |
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mb(); |
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*dim0; |
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*dim1; |
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*dim2; |
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*dim3; |
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#else |
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volatile unsigned long *dimB; |
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if (bcpu == 0) dimB = &cchip->dim0.csr; |
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else if (bcpu == 1) dimB = &cchip->dim1.csr; |
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else if (bcpu == 2) dimB = &cchip->dim2.csr; |
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else dimB = &cchip->dim3.csr; |
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*dimB = mask | isa_enable; |
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mb(); |
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*dimB; |
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#endif |
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} |
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static void |
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dp264_enable_irq(struct irq_data *d) |
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{ |
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spin_lock(&dp264_irq_lock); |
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cached_irq_mask |= 1UL << d->irq; |
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tsunami_update_irq_hw(cached_irq_mask); |
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spin_unlock(&dp264_irq_lock); |
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} |
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static void |
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dp264_disable_irq(struct irq_data *d) |
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{ |
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spin_lock(&dp264_irq_lock); |
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cached_irq_mask &= ~(1UL << d->irq); |
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tsunami_update_irq_hw(cached_irq_mask); |
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spin_unlock(&dp264_irq_lock); |
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} |
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static void |
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clipper_enable_irq(struct irq_data *d) |
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{ |
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spin_lock(&dp264_irq_lock); |
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cached_irq_mask |= 1UL << (d->irq - 16); |
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tsunami_update_irq_hw(cached_irq_mask); |
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spin_unlock(&dp264_irq_lock); |
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} |
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static void |
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clipper_disable_irq(struct irq_data *d) |
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{ |
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spin_lock(&dp264_irq_lock); |
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cached_irq_mask &= ~(1UL << (d->irq - 16)); |
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tsunami_update_irq_hw(cached_irq_mask); |
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spin_unlock(&dp264_irq_lock); |
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} |
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static void |
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cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity) |
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{ |
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int cpu; |
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for (cpu = 0; cpu < 4; cpu++) { |
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unsigned long aff = cpu_irq_affinity[cpu]; |
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if (cpumask_test_cpu(cpu, &affinity)) |
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aff |= 1UL << irq; |
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else |
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aff &= ~(1UL << irq); |
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cpu_irq_affinity[cpu] = aff; |
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} |
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} |
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static int |
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dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity, |
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bool force) |
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{ |
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spin_lock(&dp264_irq_lock); |
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cpu_set_irq_affinity(d->irq, *affinity); |
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tsunami_update_irq_hw(cached_irq_mask); |
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spin_unlock(&dp264_irq_lock); |
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return 0; |
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} |
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static int |
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clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity, |
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bool force) |
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{ |
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spin_lock(&dp264_irq_lock); |
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cpu_set_irq_affinity(d->irq - 16, *affinity); |
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tsunami_update_irq_hw(cached_irq_mask); |
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spin_unlock(&dp264_irq_lock); |
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return 0; |
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} |
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static struct irq_chip dp264_irq_type = { |
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.name = "DP264", |
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.irq_unmask = dp264_enable_irq, |
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.irq_mask = dp264_disable_irq, |
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.irq_mask_ack = dp264_disable_irq, |
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.irq_set_affinity = dp264_set_affinity, |
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}; |
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static struct irq_chip clipper_irq_type = { |
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.name = "CLIPPER", |
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.irq_unmask = clipper_enable_irq, |
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.irq_mask = clipper_disable_irq, |
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.irq_mask_ack = clipper_disable_irq, |
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.irq_set_affinity = clipper_set_affinity, |
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}; |
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static void |
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dp264_device_interrupt(unsigned long vector) |
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{ |
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unsigned long pld; |
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unsigned int i; |
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/* Read the interrupt summary register of TSUNAMI */ |
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pld = TSUNAMI_cchip->dir0.csr; |
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/* |
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* Now for every possible bit set, work through them and call |
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* the appropriate interrupt handler. |
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*/ |
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while (pld) { |
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i = ffz(~pld); |
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pld &= pld - 1; /* clear least bit set */ |
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if (i == 55) |
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isa_device_interrupt(vector); |
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else |
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handle_irq(16 + i); |
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} |
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} |
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static void |
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dp264_srm_device_interrupt(unsigned long vector) |
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{ |
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int irq; |
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irq = (vector - 0x800) >> 4; |
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/* |
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* The SRM console reports PCI interrupts with a vector calculated by: |
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* |
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* 0x900 + (0x10 * DRIR-bit) |
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* |
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* So bit 16 shows up as IRQ 32, etc. |
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* |
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* On DP264/BRICK/MONET, we adjust it down by 16 because at least |
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* that many of the low order bits of the DRIR are not used, and |
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* so we don't count them. |
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*/ |
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if (irq >= 32) |
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irq -= 16; |
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handle_irq(irq); |
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} |
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static void |
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clipper_srm_device_interrupt(unsigned long vector) |
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{ |
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int irq; |
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irq = (vector - 0x800) >> 4; |
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/* |
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* The SRM console reports PCI interrupts with a vector calculated by: |
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* |
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* 0x900 + (0x10 * DRIR-bit) |
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* |
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* So bit 16 shows up as IRQ 32, etc. |
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* |
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* CLIPPER uses bits 8-47 for PCI interrupts, so we do not need |
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* to scale down the vector reported, we just use it. |
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* |
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* Eg IRQ 24 is DRIR bit 8, etc, etc |
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*/ |
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handle_irq(irq); |
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} |
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static void __init |
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init_tsunami_irqs(struct irq_chip * ops, int imin, int imax) |
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{ |
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long i; |
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for (i = imin; i <= imax; ++i) { |
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irq_set_chip_and_handler(i, ops, handle_level_irq); |
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irq_set_status_flags(i, IRQ_LEVEL); |
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} |
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} |
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static void __init |
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dp264_init_irq(void) |
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{ |
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outb(0, DMA1_RESET_REG); |
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outb(0, DMA2_RESET_REG); |
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outb(DMA_MODE_CASCADE, DMA2_MODE_REG); |
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outb(0, DMA2_MASK_REG); |
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if (alpha_using_srm) |
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alpha_mv.device_interrupt = dp264_srm_device_interrupt; |
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tsunami_update_irq_hw(0); |
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init_i8259a_irqs(); |
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init_tsunami_irqs(&dp264_irq_type, 16, 47); |
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} |
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static void __init |
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clipper_init_irq(void) |
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{ |
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outb(0, DMA1_RESET_REG); |
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outb(0, DMA2_RESET_REG); |
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outb(DMA_MODE_CASCADE, DMA2_MODE_REG); |
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outb(0, DMA2_MASK_REG); |
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if (alpha_using_srm) |
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alpha_mv.device_interrupt = clipper_srm_device_interrupt; |
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tsunami_update_irq_hw(0); |
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init_i8259a_irqs(); |
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init_tsunami_irqs(&clipper_irq_type, 24, 63); |
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} |
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/* |
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* PCI Fixup configuration. |
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* |
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* Summary @ TSUNAMI_CSR_DIM0: |
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* Bit Meaning |
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* 0-17 Unused |
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*18 Interrupt SCSI B (Adaptec 7895 builtin) |
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*19 Interrupt SCSI A (Adaptec 7895 builtin) |
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*20 Interrupt Line D from slot 2 PCI0 |
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*21 Interrupt Line C from slot 2 PCI0 |
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*22 Interrupt Line B from slot 2 PCI0 |
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*23 Interrupt Line A from slot 2 PCI0 |
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*24 Interrupt Line D from slot 1 PCI0 |
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*25 Interrupt Line C from slot 1 PCI0 |
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*26 Interrupt Line B from slot 1 PCI0 |
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*27 Interrupt Line A from slot 1 PCI0 |
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*28 Interrupt Line D from slot 0 PCI0 |
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*29 Interrupt Line C from slot 0 PCI0 |
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*30 Interrupt Line B from slot 0 PCI0 |
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*31 Interrupt Line A from slot 0 PCI0 |
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* |
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*32 Interrupt Line D from slot 3 PCI1 |
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*33 Interrupt Line C from slot 3 PCI1 |
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*34 Interrupt Line B from slot 3 PCI1 |
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*35 Interrupt Line A from slot 3 PCI1 |
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*36 Interrupt Line D from slot 2 PCI1 |
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*37 Interrupt Line C from slot 2 PCI1 |
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*38 Interrupt Line B from slot 2 PCI1 |
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*39 Interrupt Line A from slot 2 PCI1 |
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*40 Interrupt Line D from slot 1 PCI1 |
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*41 Interrupt Line C from slot 1 PCI1 |
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*42 Interrupt Line B from slot 1 PCI1 |
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*43 Interrupt Line A from slot 1 PCI1 |
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*44 Interrupt Line D from slot 0 PCI1 |
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*45 Interrupt Line C from slot 0 PCI1 |
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*46 Interrupt Line B from slot 0 PCI1 |
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*47 Interrupt Line A from slot 0 PCI1 |
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*48-52 Unused |
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*53 PCI0 NMI (from Cypress) |
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*54 PCI0 SMI INT (from Cypress) |
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*55 PCI0 ISA Interrupt (from Cypress) |
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*56-60 Unused |
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*61 PCI1 Bus Error |
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*62 PCI0 Bus Error |
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*63 Reserved |
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* |
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* IdSel |
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* 5 Cypress Bridge I/O |
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* 6 SCSI Adaptec builtin |
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* 7 64 bit PCI option slot 0 (all busses) |
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* 8 64 bit PCI option slot 1 (all busses) |
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* 9 64 bit PCI option slot 2 (all busses) |
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* 10 64 bit PCI option slot 3 (not bus 0) |
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*/ |
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static int |
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isa_irq_fixup(const struct pci_dev *dev, int irq) |
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{ |
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u8 irq8; |
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if (irq > 0) |
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return irq; |
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/* This interrupt is routed via ISA bridge, so we'll |
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just have to trust whatever value the console might |
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have assigned. */ |
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pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8); |
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return irq8 & 0xf; |
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} |
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static int |
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dp264_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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static char irq_tab[6][5] = { |
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/*INT INTA INTB INTC INTD */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 5 ISA Bridge */ |
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{ 16+ 3, 16+ 3, 16+ 2, 16+ 2, 16+ 2}, /* IdSel 6 SCSI builtin*/ |
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{ 16+15, 16+15, 16+14, 16+13, 16+12}, /* IdSel 7 slot 0 */ |
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{ 16+11, 16+11, 16+10, 16+ 9, 16+ 8}, /* IdSel 8 slot 1 */ |
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{ 16+ 7, 16+ 7, 16+ 6, 16+ 5, 16+ 4}, /* IdSel 9 slot 2 */ |
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{ 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0} /* IdSel 10 slot 3 */ |
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}; |
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const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5; |
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struct pci_controller *hose = dev->sysdata; |
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int irq = COMMON_TABLE_LOOKUP; |
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if (irq > 0) |
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irq += 16 * hose->index; |
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return isa_irq_fixup(dev, irq); |
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} |
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static int |
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monet_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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static char irq_tab[13][5] = { |
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/*INT INTA INTB INTC INTD */ |
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{ 45, 45, 45, 45, 45}, /* IdSel 3 21143 PCI1 */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 4 unused */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 5 unused */ |
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{ 47, 47, 47, 47, 47}, /* IdSel 6 SCSI PCI1 */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 8 P2P PCI1 */ |
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#if 1 |
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{ 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/ |
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{ 24, 24, 25, 26, 27}, /* IdSel 15 slot 5 PCI2*/ |
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#else |
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{ -1, -1, -1, -1, -1}, /* IdSel 9 unused */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 10 unused */ |
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#endif |
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{ 40, 40, 41, 42, 43}, /* IdSel 11 slot 1 PCI0*/ |
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{ 36, 36, 37, 38, 39}, /* IdSel 12 slot 2 PCI0*/ |
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{ 32, 32, 33, 34, 35}, /* IdSel 13 slot 3 PCI0*/ |
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{ 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/ |
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{ 24, 24, 25, 26, 27} /* IdSel 15 slot 5 PCI2*/ |
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}; |
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const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5; |
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return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP); |
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} |
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static u8 |
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monet_swizzle(struct pci_dev *dev, u8 *pinp) |
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{ |
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struct pci_controller *hose = dev->sysdata; |
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int slot, pin = *pinp; |
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if (!dev->bus->parent) { |
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slot = PCI_SLOT(dev->devfn); |
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} |
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/* Check for the built-in bridge on hose 1. */ |
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else if (hose->index == 1 && PCI_SLOT(dev->bus->self->devfn) == 8) { |
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slot = PCI_SLOT(dev->devfn); |
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} else { |
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/* Must be a card-based bridge. */ |
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do { |
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/* Check for built-in bridge on hose 1. */ |
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if (hose->index == 1 && |
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PCI_SLOT(dev->bus->self->devfn) == 8) { |
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slot = PCI_SLOT(dev->devfn); |
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break; |
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} |
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pin = pci_swizzle_interrupt_pin(dev, pin); |
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/* Move up the chain of bridges. */ |
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dev = dev->bus->self; |
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/* Slot of the next bridge. */ |
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slot = PCI_SLOT(dev->devfn); |
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} while (dev->bus->self); |
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} |
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*pinp = pin; |
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return slot; |
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} |
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static int |
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webbrick_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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static char irq_tab[13][5] = { |
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/*INT INTA INTB INTC INTD */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 8 unused */ |
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{ 29, 29, 29, 29, 29}, /* IdSel 9 21143 #1 */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 10 unused */ |
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{ 30, 30, 30, 30, 30}, /* IdSel 11 21143 #2 */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 12 unused */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 13 unused */ |
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{ 35, 35, 34, 33, 32}, /* IdSel 14 slot 0 */ |
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{ 39, 39, 38, 37, 36}, /* IdSel 15 slot 1 */ |
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{ 43, 43, 42, 41, 40}, /* IdSel 16 slot 2 */ |
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{ 47, 47, 46, 45, 44}, /* IdSel 17 slot 3 */ |
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}; |
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const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5; |
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return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP); |
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} |
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static int |
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clipper_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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static char irq_tab[7][5] = { |
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/*INT INTA INTB INTC INTD */ |
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{ 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 1 slot 1 */ |
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{ 16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 2 slot 2 */ |
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{ 16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 3 slot 3 */ |
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{ 16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 4 slot 4 */ |
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{ 16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 5 slot 5 */ |
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{ 16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 6 slot 6 */ |
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{ -1, -1, -1, -1, -1} /* IdSel 7 ISA Bridge */ |
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}; |
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const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5; |
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struct pci_controller *hose = dev->sysdata; |
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int irq = COMMON_TABLE_LOOKUP; |
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if (irq > 0) |
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irq += 16 * hose->index; |
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return isa_irq_fixup(dev, irq); |
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} |
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static void __init |
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dp264_init_pci(void) |
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{ |
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common_init_pci(); |
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SMC669_Init(0); |
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locate_and_init_vga(NULL); |
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} |
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static void __init |
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monet_init_pci(void) |
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{ |
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common_init_pci(); |
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SMC669_Init(1); |
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es1888_init(); |
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locate_and_init_vga(NULL); |
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} |
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static void __init |
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clipper_init_pci(void) |
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{ |
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common_init_pci(); |
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locate_and_init_vga(NULL); |
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} |
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|
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static void __init |
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webbrick_init_arch(void) |
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{ |
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tsunami_init_arch(); |
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|
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/* Tsunami caches 4 PTEs at a time; DS10 has only 1 hose. */ |
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hose_head->sg_isa->align_entry = 4; |
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hose_head->sg_pci->align_entry = 4; |
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} |
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|
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/* |
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* The System Vectors |
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*/ |
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|
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struct alpha_machine_vector dp264_mv __initmv = { |
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.vector_name = "DP264", |
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DO_EV6_MMU, |
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DO_DEFAULT_RTC, |
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DO_TSUNAMI_IO, |
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.machine_check = tsunami_machine_check, |
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
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.min_io_address = DEFAULT_IO_BASE, |
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.min_mem_address = DEFAULT_MEM_BASE, |
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.pci_dac_offset = TSUNAMI_DAC_OFFSET, |
|
|
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.nr_irqs = 64, |
|
.device_interrupt = dp264_device_interrupt, |
|
|
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.init_arch = tsunami_init_arch, |
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.init_irq = dp264_init_irq, |
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.init_rtc = common_init_rtc, |
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.init_pci = dp264_init_pci, |
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.kill_arch = tsunami_kill_arch, |
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.pci_map_irq = dp264_map_irq, |
|
.pci_swizzle = common_swizzle, |
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}; |
|
ALIAS_MV(dp264) |
|
|
|
struct alpha_machine_vector monet_mv __initmv = { |
|
.vector_name = "Monet", |
|
DO_EV6_MMU, |
|
DO_DEFAULT_RTC, |
|
DO_TSUNAMI_IO, |
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.machine_check = tsunami_machine_check, |
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
|
.min_io_address = DEFAULT_IO_BASE, |
|
.min_mem_address = DEFAULT_MEM_BASE, |
|
.pci_dac_offset = TSUNAMI_DAC_OFFSET, |
|
|
|
.nr_irqs = 64, |
|
.device_interrupt = dp264_device_interrupt, |
|
|
|
.init_arch = tsunami_init_arch, |
|
.init_irq = dp264_init_irq, |
|
.init_rtc = common_init_rtc, |
|
.init_pci = monet_init_pci, |
|
.kill_arch = tsunami_kill_arch, |
|
.pci_map_irq = monet_map_irq, |
|
.pci_swizzle = monet_swizzle, |
|
}; |
|
|
|
struct alpha_machine_vector webbrick_mv __initmv = { |
|
.vector_name = "Webbrick", |
|
DO_EV6_MMU, |
|
DO_DEFAULT_RTC, |
|
DO_TSUNAMI_IO, |
|
.machine_check = tsunami_machine_check, |
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
|
.min_io_address = DEFAULT_IO_BASE, |
|
.min_mem_address = DEFAULT_MEM_BASE, |
|
.pci_dac_offset = TSUNAMI_DAC_OFFSET, |
|
|
|
.nr_irqs = 64, |
|
.device_interrupt = dp264_device_interrupt, |
|
|
|
.init_arch = webbrick_init_arch, |
|
.init_irq = dp264_init_irq, |
|
.init_rtc = common_init_rtc, |
|
.init_pci = common_init_pci, |
|
.kill_arch = tsunami_kill_arch, |
|
.pci_map_irq = webbrick_map_irq, |
|
.pci_swizzle = common_swizzle, |
|
}; |
|
|
|
struct alpha_machine_vector clipper_mv __initmv = { |
|
.vector_name = "Clipper", |
|
DO_EV6_MMU, |
|
DO_DEFAULT_RTC, |
|
DO_TSUNAMI_IO, |
|
.machine_check = tsunami_machine_check, |
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
|
.min_io_address = DEFAULT_IO_BASE, |
|
.min_mem_address = DEFAULT_MEM_BASE, |
|
.pci_dac_offset = TSUNAMI_DAC_OFFSET, |
|
|
|
.nr_irqs = 64, |
|
.device_interrupt = dp264_device_interrupt, |
|
|
|
.init_arch = tsunami_init_arch, |
|
.init_irq = clipper_init_irq, |
|
.init_rtc = common_init_rtc, |
|
.init_pci = clipper_init_pci, |
|
.kill_arch = tsunami_kill_arch, |
|
.pci_map_irq = clipper_map_irq, |
|
.pci_swizzle = common_swizzle, |
|
}; |
|
|
|
/* Sharks strongly resemble Clipper, at least as far |
|
* as interrupt routing, etc, so we're using the |
|
* same functions as Clipper does |
|
*/ |
|
|
|
struct alpha_machine_vector shark_mv __initmv = { |
|
.vector_name = "Shark", |
|
DO_EV6_MMU, |
|
DO_DEFAULT_RTC, |
|
DO_TSUNAMI_IO, |
|
.machine_check = tsunami_machine_check, |
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
|
.min_io_address = DEFAULT_IO_BASE, |
|
.min_mem_address = DEFAULT_MEM_BASE, |
|
.pci_dac_offset = TSUNAMI_DAC_OFFSET, |
|
|
|
.nr_irqs = 64, |
|
.device_interrupt = dp264_device_interrupt, |
|
|
|
.init_arch = tsunami_init_arch, |
|
.init_irq = clipper_init_irq, |
|
.init_rtc = common_init_rtc, |
|
.init_pci = common_init_pci, |
|
.kill_arch = tsunami_kill_arch, |
|
.pci_map_irq = clipper_map_irq, |
|
.pci_swizzle = common_swizzle, |
|
}; |
|
|
|
/* No alpha_mv alias for webbrick/monet/clipper, since we compile them |
|
in unconditionally with DP264; setup_arch knows how to cope. */
|
|
|