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309 lines
7.6 KiB
309 lines
7.6 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* linux/arch/alpha/kernel/sys_alcor.c |
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* |
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* Copyright (C) 1995 David A Rusling |
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* Copyright (C) 1996 Jay A Estabrook |
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* Copyright (C) 1998, 1999 Richard Henderson |
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* |
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* Code supporting the ALCOR and XLT (XL-300/366/433). |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/mm.h> |
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#include <linux/sched.h> |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/reboot.h> |
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#include <linux/bitops.h> |
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#include <asm/ptrace.h> |
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#include <asm/io.h> |
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#include <asm/dma.h> |
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#include <asm/mmu_context.h> |
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#include <asm/irq.h> |
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#include <asm/core_cia.h> |
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#include <asm/tlbflush.h> |
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#include "proto.h" |
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#include "irq_impl.h" |
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#include "pci_impl.h" |
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#include "machvec_impl.h" |
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/* Note mask bit is true for ENABLED irqs. */ |
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static unsigned long cached_irq_mask; |
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static inline void |
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alcor_update_irq_hw(unsigned long mask) |
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{ |
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*(vuip)GRU_INT_MASK = mask; |
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mb(); |
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} |
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static inline void |
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alcor_enable_irq(struct irq_data *d) |
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{ |
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alcor_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16)); |
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} |
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static void |
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alcor_disable_irq(struct irq_data *d) |
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{ |
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alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16))); |
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} |
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static void |
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alcor_mask_and_ack_irq(struct irq_data *d) |
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{ |
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alcor_disable_irq(d); |
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/* On ALCOR/XLT, need to dismiss interrupt via GRU. */ |
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*(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb(); |
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*(vuip)GRU_INT_CLEAR = 0; mb(); |
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} |
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static void |
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alcor_isa_mask_and_ack_irq(struct irq_data *d) |
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{ |
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i8259a_mask_and_ack_irq(d); |
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/* On ALCOR/XLT, need to dismiss interrupt via GRU. */ |
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*(vuip)GRU_INT_CLEAR = 0x80000000; mb(); |
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*(vuip)GRU_INT_CLEAR = 0; mb(); |
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} |
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static struct irq_chip alcor_irq_type = { |
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.name = "ALCOR", |
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.irq_unmask = alcor_enable_irq, |
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.irq_mask = alcor_disable_irq, |
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.irq_mask_ack = alcor_mask_and_ack_irq, |
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}; |
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static void |
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alcor_device_interrupt(unsigned long vector) |
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{ |
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unsigned long pld; |
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unsigned int i; |
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/* Read the interrupt summary register of the GRU */ |
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pld = (*(vuip)GRU_INT_REQ) & GRU_INT_REQ_BITS; |
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/* |
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* Now for every possible bit set, work through them and call |
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* the appropriate interrupt handler. |
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*/ |
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while (pld) { |
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i = ffz(~pld); |
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pld &= pld - 1; /* clear least bit set */ |
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if (i == 31) { |
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isa_device_interrupt(vector); |
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} else { |
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handle_irq(16 + i); |
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} |
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} |
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} |
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static void __init |
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alcor_init_irq(void) |
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{ |
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long i; |
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if (alpha_using_srm) |
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alpha_mv.device_interrupt = srm_device_interrupt; |
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*(vuip)GRU_INT_MASK = 0; mb(); /* all disabled */ |
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*(vuip)GRU_INT_EDGE = 0; mb(); /* all are level */ |
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*(vuip)GRU_INT_HILO = 0x80000000U; mb(); /* ISA only HI */ |
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*(vuip)GRU_INT_CLEAR = 0; mb(); /* all clear */ |
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for (i = 16; i < 48; ++i) { |
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/* On Alcor, at least, lines 20..30 are not connected |
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and can generate spurious interrupts if we turn them |
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on while IRQ probing. */ |
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if (i >= 16+20 && i <= 16+30) |
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continue; |
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irq_set_chip_and_handler(i, &alcor_irq_type, handle_level_irq); |
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irq_set_status_flags(i, IRQ_LEVEL); |
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} |
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i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq; |
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init_i8259a_irqs(); |
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common_init_isa_dma(); |
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if (request_irq(16 + 31, no_action, 0, "isa-cascade", NULL)) |
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pr_err("Failed to register isa-cascade interrupt\n"); |
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} |
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/* |
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* PCI Fixup configuration. |
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* |
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* Summary @ GRU_INT_REQ: |
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* Bit Meaning |
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* 0 Interrupt Line A from slot 2 |
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* 1 Interrupt Line B from slot 2 |
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* 2 Interrupt Line C from slot 2 |
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* 3 Interrupt Line D from slot 2 |
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* 4 Interrupt Line A from slot 1 |
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* 5 Interrupt line B from slot 1 |
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* 6 Interrupt Line C from slot 1 |
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* 7 Interrupt Line D from slot 1 |
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* 8 Interrupt Line A from slot 0 |
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* 9 Interrupt Line B from slot 0 |
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*10 Interrupt Line C from slot 0 |
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*11 Interrupt Line D from slot 0 |
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*12 Interrupt Line A from slot 4 |
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*13 Interrupt Line B from slot 4 |
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*14 Interrupt Line C from slot 4 |
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*15 Interrupt Line D from slot 4 |
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*16 Interrupt Line D from slot 3 |
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*17 Interrupt Line D from slot 3 |
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*18 Interrupt Line D from slot 3 |
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*19 Interrupt Line D from slot 3 |
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*20-30 Reserved |
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*31 EISA interrupt |
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* |
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* The device to slot mapping looks like: |
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* |
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* Slot Device |
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* 6 built-in TULIP (XLT only) |
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* 7 PCI on board slot 0 |
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* 8 PCI on board slot 3 |
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* 9 PCI on board slot 4 |
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* 10 PCEB (PCI-EISA bridge) |
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* 11 PCI on board slot 2 |
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* 12 PCI on board slot 1 |
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* |
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* |
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* This two layered interrupt approach means that we allocate IRQ 16 and |
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* above for PCI interrupts. The IRQ relates to which bit the interrupt |
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* comes in on. This makes interrupt processing much easier. |
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*/ |
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static int |
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alcor_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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static char irq_tab[7][5] = { |
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/*INT INTA INTB INTC INTD */ |
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/* note: IDSEL 17 is XLT only */ |
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{16+13, 16+13, 16+13, 16+13, 16+13}, /* IdSel 17, TULIP */ |
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{ 16+8, 16+8, 16+9, 16+10, 16+11}, /* IdSel 18, slot 0 */ |
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{16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 19, slot 3 */ |
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{16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 20, slot 4 */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 21, PCEB */ |
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{ 16+0, 16+0, 16+1, 16+2, 16+3}, /* IdSel 22, slot 2 */ |
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{ 16+4, 16+4, 16+5, 16+6, 16+7}, /* IdSel 23, slot 1 */ |
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}; |
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const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5; |
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return COMMON_TABLE_LOOKUP; |
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} |
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static void |
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alcor_kill_arch(int mode) |
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{ |
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cia_kill_arch(mode); |
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#ifndef ALPHA_RESTORE_SRM_SETUP |
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switch(mode) { |
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case LINUX_REBOOT_CMD_RESTART: |
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/* Who said DEC engineer's have no sense of humor? ;-) */ |
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if (alpha_using_srm) { |
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*(vuip) GRU_RESET = 0x0000dead; |
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mb(); |
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} |
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break; |
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case LINUX_REBOOT_CMD_HALT: |
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break; |
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case LINUX_REBOOT_CMD_POWER_OFF: |
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break; |
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} |
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halt(); |
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#endif |
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} |
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static void __init |
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alcor_init_pci(void) |
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{ |
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struct pci_dev *dev; |
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cia_init_pci(); |
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/* |
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* Now we can look to see if we are really running on an XLT-type |
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* motherboard, by looking for a 21040 TULIP in slot 6, which is |
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* built into XLT and BRET/MAVERICK, but not available on ALCOR. |
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*/ |
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dev = pci_get_device(PCI_VENDOR_ID_DEC, |
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PCI_DEVICE_ID_DEC_TULIP, |
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NULL); |
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if (dev && dev->devfn == PCI_DEVFN(6,0)) { |
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alpha_mv.sys.cia.gru_int_req_bits = XLT_GRU_INT_REQ_BITS; |
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printk(KERN_INFO "%s: Detected AS500 or XLT motherboard.\n", |
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__func__); |
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} |
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pci_dev_put(dev); |
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} |
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/* |
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* The System Vectors |
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*/ |
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struct alpha_machine_vector alcor_mv __initmv = { |
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.vector_name = "Alcor", |
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DO_EV5_MMU, |
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DO_DEFAULT_RTC, |
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DO_CIA_IO, |
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.machine_check = cia_machine_check, |
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.max_isa_dma_address = ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS, |
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.min_io_address = EISA_DEFAULT_IO_BASE, |
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.min_mem_address = CIA_DEFAULT_MEM_BASE, |
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.nr_irqs = 48, |
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.device_interrupt = alcor_device_interrupt, |
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.init_arch = cia_init_arch, |
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.init_irq = alcor_init_irq, |
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.init_rtc = common_init_rtc, |
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.init_pci = alcor_init_pci, |
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.kill_arch = alcor_kill_arch, |
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.pci_map_irq = alcor_map_irq, |
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.pci_swizzle = common_swizzle, |
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.sys = { .cia = { |
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.gru_int_req_bits = ALCOR_GRU_INT_REQ_BITS |
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}} |
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}; |
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ALIAS_MV(alcor) |
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struct alpha_machine_vector xlt_mv __initmv = { |
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.vector_name = "XLT", |
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DO_EV5_MMU, |
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DO_DEFAULT_RTC, |
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DO_CIA_IO, |
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.machine_check = cia_machine_check, |
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
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.min_io_address = EISA_DEFAULT_IO_BASE, |
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.min_mem_address = CIA_DEFAULT_MEM_BASE, |
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.nr_irqs = 48, |
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.device_interrupt = alcor_device_interrupt, |
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.init_arch = cia_init_arch, |
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.init_irq = alcor_init_irq, |
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.init_rtc = common_init_rtc, |
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.init_pci = alcor_init_pci, |
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.kill_arch = alcor_kill_arch, |
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.pci_map_irq = alcor_map_irq, |
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.pci_swizzle = common_swizzle, |
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.sys = { .cia = { |
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.gru_int_req_bits = XLT_GRU_INT_REQ_BITS |
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}} |
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}; |
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/* No alpha_mv alias for XLT, since we compile it in unconditionally |
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with ALCOR; setup_arch knows how to cope. */
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