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899 lines
23 KiB
899 lines
23 KiB
// SPDX-License-Identifier: GPL-2.0 |
|
/* |
|
* Hardware performance events for the Alpha. |
|
* |
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* We implement HW counts on the EV67 and subsequent CPUs only. |
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* |
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* (C) 2010 Michael J. Cree |
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* |
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* Somewhat based on the Sparc code, and to a lesser extent the PowerPC and |
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* ARM code, which are copyright by their respective authors. |
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*/ |
|
|
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#include <linux/perf_event.h> |
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#include <linux/kprobes.h> |
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#include <linux/kernel.h> |
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#include <linux/kdebug.h> |
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#include <linux/mutex.h> |
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#include <linux/init.h> |
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|
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#include <asm/hwrpb.h> |
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#include <linux/atomic.h> |
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#include <asm/irq.h> |
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#include <asm/irq_regs.h> |
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#include <asm/pal.h> |
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#include <asm/wrperfmon.h> |
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#include <asm/hw_irq.h> |
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|
|
|
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/* The maximum number of PMCs on any Alpha CPU whatsoever. */ |
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#define MAX_HWEVENTS 3 |
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#define PMC_NO_INDEX -1 |
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|
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/* For tracking PMCs and the hw events they monitor on each CPU. */ |
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struct cpu_hw_events { |
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int enabled; |
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/* Number of events scheduled; also number entries valid in arrays below. */ |
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int n_events; |
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/* Number events added since last hw_perf_disable(). */ |
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int n_added; |
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/* Events currently scheduled. */ |
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struct perf_event *event[MAX_HWEVENTS]; |
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/* Event type of each scheduled event. */ |
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unsigned long evtype[MAX_HWEVENTS]; |
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/* Current index of each scheduled event; if not yet determined |
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* contains PMC_NO_INDEX. |
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*/ |
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int current_idx[MAX_HWEVENTS]; |
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/* The active PMCs' config for easy use with wrperfmon(). */ |
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unsigned long config; |
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/* The active counters' indices for easy use with wrperfmon(). */ |
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unsigned long idx_mask; |
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}; |
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DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
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|
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|
|
|
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/* |
|
* A structure to hold the description of the PMCs available on a particular |
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* type of Alpha CPU. |
|
*/ |
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struct alpha_pmu_t { |
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/* Mapping of the perf system hw event types to indigenous event types */ |
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const int *event_map; |
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/* The number of entries in the event_map */ |
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int max_events; |
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/* The number of PMCs on this Alpha */ |
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int num_pmcs; |
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/* |
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* All PMC counters reside in the IBOX register PCTR. This is the |
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* LSB of the counter. |
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*/ |
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int pmc_count_shift[MAX_HWEVENTS]; |
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/* |
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* The mask that isolates the PMC bits when the LSB of the counter |
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* is shifted to bit 0. |
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*/ |
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unsigned long pmc_count_mask[MAX_HWEVENTS]; |
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/* The maximum period the PMC can count. */ |
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unsigned long pmc_max_period[MAX_HWEVENTS]; |
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/* |
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* The maximum value that may be written to the counter due to |
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* hardware restrictions is pmc_max_period - pmc_left. |
|
*/ |
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long pmc_left[3]; |
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/* Subroutine for allocation of PMCs. Enforces constraints. */ |
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int (*check_constraints)(struct perf_event **, unsigned long *, int); |
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/* Subroutine for checking validity of a raw event for this PMU. */ |
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int (*raw_event_valid)(u64 config); |
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}; |
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|
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/* |
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* The Alpha CPU PMU description currently in operation. This is set during |
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* the boot process to the specific CPU of the machine. |
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*/ |
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static const struct alpha_pmu_t *alpha_pmu; |
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|
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#define HW_OP_UNSUPPORTED -1 |
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|
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/* |
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* The hardware description of the EV67, EV68, EV69, EV7 and EV79 PMUs |
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* follow. Since they are identical we refer to them collectively as the |
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* EV67 henceforth. |
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*/ |
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|
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/* |
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* EV67 PMC event types |
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* |
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* There is no one-to-one mapping of the possible hw event types to the |
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* actual codes that are used to program the PMCs hence we introduce our |
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* own hw event type identifiers. |
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*/ |
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enum ev67_pmc_event_type { |
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EV67_CYCLES = 1, |
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EV67_INSTRUCTIONS, |
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EV67_BCACHEMISS, |
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EV67_MBOXREPLAY, |
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EV67_LAST_ET |
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}; |
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#define EV67_NUM_EVENT_TYPES (EV67_LAST_ET-EV67_CYCLES) |
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|
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|
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/* Mapping of the hw event types to the perf tool interface */ |
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static const int ev67_perfmon_event_map[] = { |
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[PERF_COUNT_HW_CPU_CYCLES] = EV67_CYCLES, |
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[PERF_COUNT_HW_INSTRUCTIONS] = EV67_INSTRUCTIONS, |
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[PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, |
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[PERF_COUNT_HW_CACHE_MISSES] = EV67_BCACHEMISS, |
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}; |
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|
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struct ev67_mapping_t { |
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int config; |
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int idx; |
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}; |
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|
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/* |
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* The mapping used for one event only - these must be in same order as enum |
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* ev67_pmc_event_type definition. |
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*/ |
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static const struct ev67_mapping_t ev67_mapping[] = { |
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{EV67_PCTR_INSTR_CYCLES, 1}, /* EV67_CYCLES, */ |
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{EV67_PCTR_INSTR_CYCLES, 0}, /* EV67_INSTRUCTIONS */ |
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{EV67_PCTR_INSTR_BCACHEMISS, 1}, /* EV67_BCACHEMISS */ |
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{EV67_PCTR_CYCLES_MBOX, 1} /* EV67_MBOXREPLAY */ |
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}; |
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|
|
|
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/* |
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* Check that a group of events can be simultaneously scheduled on to the |
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* EV67 PMU. Also allocate counter indices and config. |
|
*/ |
|
static int ev67_check_constraints(struct perf_event **event, |
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unsigned long *evtype, int n_ev) |
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{ |
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int idx0; |
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unsigned long config; |
|
|
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idx0 = ev67_mapping[evtype[0]-1].idx; |
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config = ev67_mapping[evtype[0]-1].config; |
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if (n_ev == 1) |
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goto success; |
|
|
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BUG_ON(n_ev != 2); |
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|
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if (evtype[0] == EV67_MBOXREPLAY || evtype[1] == EV67_MBOXREPLAY) { |
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/* MBOX replay traps must be on PMC 1 */ |
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idx0 = (evtype[0] == EV67_MBOXREPLAY) ? 1 : 0; |
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/* Only cycles can accompany MBOX replay traps */ |
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if (evtype[idx0] == EV67_CYCLES) { |
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config = EV67_PCTR_CYCLES_MBOX; |
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goto success; |
|
} |
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} |
|
|
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if (evtype[0] == EV67_BCACHEMISS || evtype[1] == EV67_BCACHEMISS) { |
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/* Bcache misses must be on PMC 1 */ |
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idx0 = (evtype[0] == EV67_BCACHEMISS) ? 1 : 0; |
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/* Only instructions can accompany Bcache misses */ |
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if (evtype[idx0] == EV67_INSTRUCTIONS) { |
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config = EV67_PCTR_INSTR_BCACHEMISS; |
|
goto success; |
|
} |
|
} |
|
|
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if (evtype[0] == EV67_INSTRUCTIONS || evtype[1] == EV67_INSTRUCTIONS) { |
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/* Instructions must be on PMC 0 */ |
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idx0 = (evtype[0] == EV67_INSTRUCTIONS) ? 0 : 1; |
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/* By this point only cycles can accompany instructions */ |
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if (evtype[idx0^1] == EV67_CYCLES) { |
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config = EV67_PCTR_INSTR_CYCLES; |
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goto success; |
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} |
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} |
|
|
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/* Otherwise, darn it, there is a conflict. */ |
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return -1; |
|
|
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success: |
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event[0]->hw.idx = idx0; |
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event[0]->hw.config_base = config; |
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if (n_ev == 2) { |
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event[1]->hw.idx = idx0 ^ 1; |
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event[1]->hw.config_base = config; |
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} |
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return 0; |
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} |
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|
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static int ev67_raw_event_valid(u64 config) |
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{ |
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return config >= EV67_CYCLES && config < EV67_LAST_ET; |
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}; |
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|
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|
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static const struct alpha_pmu_t ev67_pmu = { |
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.event_map = ev67_perfmon_event_map, |
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.max_events = ARRAY_SIZE(ev67_perfmon_event_map), |
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.num_pmcs = 2, |
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.pmc_count_shift = {EV67_PCTR_0_COUNT_SHIFT, EV67_PCTR_1_COUNT_SHIFT, 0}, |
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.pmc_count_mask = {EV67_PCTR_0_COUNT_MASK, EV67_PCTR_1_COUNT_MASK, 0}, |
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.pmc_max_period = {(1UL<<20) - 1, (1UL<<20) - 1, 0}, |
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.pmc_left = {16, 4, 0}, |
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.check_constraints = ev67_check_constraints, |
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.raw_event_valid = ev67_raw_event_valid, |
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}; |
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|
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|
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/* |
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* Helper routines to ensure that we read/write only the correct PMC bits |
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* when calling the wrperfmon PALcall. |
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*/ |
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static inline void alpha_write_pmc(int idx, unsigned long val) |
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{ |
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val &= alpha_pmu->pmc_count_mask[idx]; |
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val <<= alpha_pmu->pmc_count_shift[idx]; |
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val |= (1<<idx); |
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wrperfmon(PERFMON_CMD_WRITE, val); |
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} |
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|
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static inline unsigned long alpha_read_pmc(int idx) |
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{ |
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unsigned long val; |
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|
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val = wrperfmon(PERFMON_CMD_READ, 0); |
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val >>= alpha_pmu->pmc_count_shift[idx]; |
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val &= alpha_pmu->pmc_count_mask[idx]; |
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return val; |
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} |
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|
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/* Set a new period to sample over */ |
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static int alpha_perf_event_set_period(struct perf_event *event, |
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struct hw_perf_event *hwc, int idx) |
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{ |
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long left = local64_read(&hwc->period_left); |
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long period = hwc->sample_period; |
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int ret = 0; |
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|
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if (unlikely(left <= -period)) { |
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left = period; |
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local64_set(&hwc->period_left, left); |
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hwc->last_period = period; |
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ret = 1; |
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} |
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|
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if (unlikely(left <= 0)) { |
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left += period; |
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local64_set(&hwc->period_left, left); |
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hwc->last_period = period; |
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ret = 1; |
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} |
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|
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/* |
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* Hardware restrictions require that the counters must not be |
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* written with values that are too close to the maximum period. |
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*/ |
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if (unlikely(left < alpha_pmu->pmc_left[idx])) |
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left = alpha_pmu->pmc_left[idx]; |
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if (left > (long)alpha_pmu->pmc_max_period[idx]) |
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left = alpha_pmu->pmc_max_period[idx]; |
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local64_set(&hwc->prev_count, (unsigned long)(-left)); |
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alpha_write_pmc(idx, (unsigned long)(-left)); |
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perf_event_update_userpage(event); |
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return ret; |
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} |
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/* |
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* Calculates the count (the 'delta') since the last time the PMC was read. |
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* |
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* As the PMCs' full period can easily be exceeded within the perf system |
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* sampling period we cannot use any high order bits as a guard bit in the |
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* PMCs to detect overflow as is done by other architectures. The code here |
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* calculates the delta on the basis that there is no overflow when ovf is |
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* zero. The value passed via ovf by the interrupt handler corrects for |
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* overflow. |
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* |
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* This can be racey on rare occasions -- a call to this routine can occur |
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* with an overflowed counter just before the PMI service routine is called. |
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* The check for delta negative hopefully always rectifies this situation. |
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*/ |
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static unsigned long alpha_perf_event_update(struct perf_event *event, |
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struct hw_perf_event *hwc, int idx, long ovf) |
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{ |
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long prev_raw_count, new_raw_count; |
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long delta; |
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|
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again: |
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prev_raw_count = local64_read(&hwc->prev_count); |
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new_raw_count = alpha_read_pmc(idx); |
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if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
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new_raw_count) != prev_raw_count) |
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goto again; |
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delta = (new_raw_count - (prev_raw_count & alpha_pmu->pmc_count_mask[idx])) + ovf; |
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|
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/* It is possible on very rare occasions that the PMC has overflowed |
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* but the interrupt is yet to come. Detect and fix this situation. |
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*/ |
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if (unlikely(delta < 0)) { |
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delta += alpha_pmu->pmc_max_period[idx] + 1; |
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} |
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local64_add(delta, &event->count); |
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local64_sub(delta, &hwc->period_left); |
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|
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return new_raw_count; |
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} |
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|
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/* |
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* Collect all HW events into the array event[]. |
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*/ |
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static int collect_events(struct perf_event *group, int max_count, |
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struct perf_event *event[], unsigned long *evtype, |
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int *current_idx) |
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{ |
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struct perf_event *pe; |
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int n = 0; |
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|
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if (!is_software_event(group)) { |
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if (n >= max_count) |
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return -1; |
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event[n] = group; |
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evtype[n] = group->hw.event_base; |
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current_idx[n++] = PMC_NO_INDEX; |
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} |
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for_each_sibling_event(pe, group) { |
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if (!is_software_event(pe) && pe->state != PERF_EVENT_STATE_OFF) { |
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if (n >= max_count) |
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return -1; |
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event[n] = pe; |
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evtype[n] = pe->hw.event_base; |
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current_idx[n++] = PMC_NO_INDEX; |
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} |
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} |
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return n; |
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} |
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|
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/* |
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* Check that a group of events can be simultaneously scheduled on to the PMU. |
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*/ |
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static int alpha_check_constraints(struct perf_event **events, |
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unsigned long *evtypes, int n_ev) |
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{ |
|
|
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/* No HW events is possible from hw_perf_group_sched_in(). */ |
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if (n_ev == 0) |
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return 0; |
|
|
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if (n_ev > alpha_pmu->num_pmcs) |
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return -1; |
|
|
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return alpha_pmu->check_constraints(events, evtypes, n_ev); |
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} |
|
|
|
|
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/* |
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* If new events have been scheduled then update cpuc with the new |
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* configuration. This may involve shifting cycle counts from one PMC to |
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* another. |
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*/ |
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static void maybe_change_configuration(struct cpu_hw_events *cpuc) |
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{ |
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int j; |
|
|
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if (cpuc->n_added == 0) |
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return; |
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|
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/* Find counters that are moving to another PMC and update */ |
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for (j = 0; j < cpuc->n_events; j++) { |
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struct perf_event *pe = cpuc->event[j]; |
|
|
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if (cpuc->current_idx[j] != PMC_NO_INDEX && |
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cpuc->current_idx[j] != pe->hw.idx) { |
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alpha_perf_event_update(pe, &pe->hw, cpuc->current_idx[j], 0); |
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cpuc->current_idx[j] = PMC_NO_INDEX; |
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} |
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} |
|
|
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/* Assign to counters all unassigned events. */ |
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cpuc->idx_mask = 0; |
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for (j = 0; j < cpuc->n_events; j++) { |
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struct perf_event *pe = cpuc->event[j]; |
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struct hw_perf_event *hwc = &pe->hw; |
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int idx = hwc->idx; |
|
|
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if (cpuc->current_idx[j] == PMC_NO_INDEX) { |
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alpha_perf_event_set_period(pe, hwc, idx); |
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cpuc->current_idx[j] = idx; |
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} |
|
|
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if (!(hwc->state & PERF_HES_STOPPED)) |
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cpuc->idx_mask |= (1<<cpuc->current_idx[j]); |
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} |
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cpuc->config = cpuc->event[0]->hw.config_base; |
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} |
|
|
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|
|
|
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/* Schedule perf HW event on to PMU. |
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* - this function is called from outside this module via the pmu struct |
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* returned from perf event initialisation. |
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*/ |
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static int alpha_pmu_add(struct perf_event *event, int flags) |
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{ |
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struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
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struct hw_perf_event *hwc = &event->hw; |
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int n0; |
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int ret; |
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unsigned long irq_flags; |
|
|
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/* |
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* The Sparc code has the IRQ disable first followed by the perf |
|
* disable, however this can lead to an overflowed counter with the |
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* PMI disabled on rare occasions. The alpha_perf_event_update() |
|
* routine should detect this situation by noting a negative delta, |
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* nevertheless we disable the PMCs first to enable a potential |
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* final PMI to occur before we disable interrupts. |
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*/ |
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perf_pmu_disable(event->pmu); |
|
local_irq_save(irq_flags); |
|
|
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/* Default to error to be returned */ |
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ret = -EAGAIN; |
|
|
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/* Insert event on to PMU and if successful modify ret to valid return */ |
|
n0 = cpuc->n_events; |
|
if (n0 < alpha_pmu->num_pmcs) { |
|
cpuc->event[n0] = event; |
|
cpuc->evtype[n0] = event->hw.event_base; |
|
cpuc->current_idx[n0] = PMC_NO_INDEX; |
|
|
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if (!alpha_check_constraints(cpuc->event, cpuc->evtype, n0+1)) { |
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cpuc->n_events++; |
|
cpuc->n_added++; |
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ret = 0; |
|
} |
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} |
|
|
|
hwc->state = PERF_HES_UPTODATE; |
|
if (!(flags & PERF_EF_START)) |
|
hwc->state |= PERF_HES_STOPPED; |
|
|
|
local_irq_restore(irq_flags); |
|
perf_pmu_enable(event->pmu); |
|
|
|
return ret; |
|
} |
|
|
|
|
|
|
|
/* Disable performance monitoring unit |
|
* - this function is called from outside this module via the pmu struct |
|
* returned from perf event initialisation. |
|
*/ |
|
static void alpha_pmu_del(struct perf_event *event, int flags) |
|
{ |
|
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
|
struct hw_perf_event *hwc = &event->hw; |
|
unsigned long irq_flags; |
|
int j; |
|
|
|
perf_pmu_disable(event->pmu); |
|
local_irq_save(irq_flags); |
|
|
|
for (j = 0; j < cpuc->n_events; j++) { |
|
if (event == cpuc->event[j]) { |
|
int idx = cpuc->current_idx[j]; |
|
|
|
/* Shift remaining entries down into the existing |
|
* slot. |
|
*/ |
|
while (++j < cpuc->n_events) { |
|
cpuc->event[j - 1] = cpuc->event[j]; |
|
cpuc->evtype[j - 1] = cpuc->evtype[j]; |
|
cpuc->current_idx[j - 1] = |
|
cpuc->current_idx[j]; |
|
} |
|
|
|
/* Absorb the final count and turn off the event. */ |
|
alpha_perf_event_update(event, hwc, idx, 0); |
|
perf_event_update_userpage(event); |
|
|
|
cpuc->idx_mask &= ~(1UL<<idx); |
|
cpuc->n_events--; |
|
break; |
|
} |
|
} |
|
|
|
local_irq_restore(irq_flags); |
|
perf_pmu_enable(event->pmu); |
|
} |
|
|
|
|
|
static void alpha_pmu_read(struct perf_event *event) |
|
{ |
|
struct hw_perf_event *hwc = &event->hw; |
|
|
|
alpha_perf_event_update(event, hwc, hwc->idx, 0); |
|
} |
|
|
|
|
|
static void alpha_pmu_stop(struct perf_event *event, int flags) |
|
{ |
|
struct hw_perf_event *hwc = &event->hw; |
|
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
|
|
|
if (!(hwc->state & PERF_HES_STOPPED)) { |
|
cpuc->idx_mask &= ~(1UL<<hwc->idx); |
|
hwc->state |= PERF_HES_STOPPED; |
|
} |
|
|
|
if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
|
alpha_perf_event_update(event, hwc, hwc->idx, 0); |
|
hwc->state |= PERF_HES_UPTODATE; |
|
} |
|
|
|
if (cpuc->enabled) |
|
wrperfmon(PERFMON_CMD_DISABLE, (1UL<<hwc->idx)); |
|
} |
|
|
|
|
|
static void alpha_pmu_start(struct perf_event *event, int flags) |
|
{ |
|
struct hw_perf_event *hwc = &event->hw; |
|
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
|
|
|
if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED))) |
|
return; |
|
|
|
if (flags & PERF_EF_RELOAD) { |
|
WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); |
|
alpha_perf_event_set_period(event, hwc, hwc->idx); |
|
} |
|
|
|
hwc->state = 0; |
|
|
|
cpuc->idx_mask |= 1UL<<hwc->idx; |
|
if (cpuc->enabled) |
|
wrperfmon(PERFMON_CMD_ENABLE, (1UL<<hwc->idx)); |
|
} |
|
|
|
|
|
/* |
|
* Check that CPU performance counters are supported. |
|
* - currently support EV67 and later CPUs. |
|
* - actually some later revisions of the EV6 have the same PMC model as the |
|
* EV67 but we don't do suffiently deep CPU detection to detect them. |
|
* Bad luck to the very few people who might have one, I guess. |
|
*/ |
|
static int supported_cpu(void) |
|
{ |
|
struct percpu_struct *cpu; |
|
unsigned long cputype; |
|
|
|
/* Get cpu type from HW */ |
|
cpu = (struct percpu_struct *)((char *)hwrpb + hwrpb->processor_offset); |
|
cputype = cpu->type & 0xffffffff; |
|
/* Include all of EV67, EV68, EV7, EV79 and EV69 as supported. */ |
|
return (cputype >= EV67_CPU) && (cputype <= EV69_CPU); |
|
} |
|
|
|
|
|
|
|
static void hw_perf_event_destroy(struct perf_event *event) |
|
{ |
|
/* Nothing to be done! */ |
|
return; |
|
} |
|
|
|
|
|
|
|
static int __hw_perf_event_init(struct perf_event *event) |
|
{ |
|
struct perf_event_attr *attr = &event->attr; |
|
struct hw_perf_event *hwc = &event->hw; |
|
struct perf_event *evts[MAX_HWEVENTS]; |
|
unsigned long evtypes[MAX_HWEVENTS]; |
|
int idx_rubbish_bin[MAX_HWEVENTS]; |
|
int ev; |
|
int n; |
|
|
|
/* We only support a limited range of HARDWARE event types with one |
|
* only programmable via a RAW event type. |
|
*/ |
|
if (attr->type == PERF_TYPE_HARDWARE) { |
|
if (attr->config >= alpha_pmu->max_events) |
|
return -EINVAL; |
|
ev = alpha_pmu->event_map[attr->config]; |
|
} else if (attr->type == PERF_TYPE_HW_CACHE) { |
|
return -EOPNOTSUPP; |
|
} else if (attr->type == PERF_TYPE_RAW) { |
|
if (!alpha_pmu->raw_event_valid(attr->config)) |
|
return -EINVAL; |
|
ev = attr->config; |
|
} else { |
|
return -EOPNOTSUPP; |
|
} |
|
|
|
if (ev < 0) { |
|
return ev; |
|
} |
|
|
|
/* |
|
* We place the event type in event_base here and leave calculation |
|
* of the codes to programme the PMU for alpha_pmu_enable() because |
|
* it is only then we will know what HW events are actually |
|
* scheduled on to the PMU. At that point the code to programme the |
|
* PMU is put into config_base and the PMC to use is placed into |
|
* idx. We initialise idx (below) to PMC_NO_INDEX to indicate that |
|
* it is yet to be determined. |
|
*/ |
|
hwc->event_base = ev; |
|
|
|
/* Collect events in a group together suitable for calling |
|
* alpha_check_constraints() to verify that the group as a whole can |
|
* be scheduled on to the PMU. |
|
*/ |
|
n = 0; |
|
if (event->group_leader != event) { |
|
n = collect_events(event->group_leader, |
|
alpha_pmu->num_pmcs - 1, |
|
evts, evtypes, idx_rubbish_bin); |
|
if (n < 0) |
|
return -EINVAL; |
|
} |
|
evtypes[n] = hwc->event_base; |
|
evts[n] = event; |
|
|
|
if (alpha_check_constraints(evts, evtypes, n + 1)) |
|
return -EINVAL; |
|
|
|
/* Indicate that PMU config and idx are yet to be determined. */ |
|
hwc->config_base = 0; |
|
hwc->idx = PMC_NO_INDEX; |
|
|
|
event->destroy = hw_perf_event_destroy; |
|
|
|
/* |
|
* Most architectures reserve the PMU for their use at this point. |
|
* As there is no existing mechanism to arbitrate usage and there |
|
* appears to be no other user of the Alpha PMU we just assume |
|
* that we can just use it, hence a NO-OP here. |
|
* |
|
* Maybe an alpha_reserve_pmu() routine should be implemented but is |
|
* anything else ever going to use it? |
|
*/ |
|
|
|
if (!hwc->sample_period) { |
|
hwc->sample_period = alpha_pmu->pmc_max_period[0]; |
|
hwc->last_period = hwc->sample_period; |
|
local64_set(&hwc->period_left, hwc->sample_period); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
/* |
|
* Main entry point to initialise a HW performance event. |
|
*/ |
|
static int alpha_pmu_event_init(struct perf_event *event) |
|
{ |
|
int err; |
|
|
|
/* does not support taken branch sampling */ |
|
if (has_branch_stack(event)) |
|
return -EOPNOTSUPP; |
|
|
|
switch (event->attr.type) { |
|
case PERF_TYPE_RAW: |
|
case PERF_TYPE_HARDWARE: |
|
case PERF_TYPE_HW_CACHE: |
|
break; |
|
|
|
default: |
|
return -ENOENT; |
|
} |
|
|
|
if (!alpha_pmu) |
|
return -ENODEV; |
|
|
|
/* Do the real initialisation work. */ |
|
err = __hw_perf_event_init(event); |
|
|
|
return err; |
|
} |
|
|
|
/* |
|
* Main entry point - enable HW performance counters. |
|
*/ |
|
static void alpha_pmu_enable(struct pmu *pmu) |
|
{ |
|
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
|
|
|
if (cpuc->enabled) |
|
return; |
|
|
|
cpuc->enabled = 1; |
|
barrier(); |
|
|
|
if (cpuc->n_events > 0) { |
|
/* Update cpuc with information from any new scheduled events. */ |
|
maybe_change_configuration(cpuc); |
|
|
|
/* Start counting the desired events. */ |
|
wrperfmon(PERFMON_CMD_LOGGING_OPTIONS, EV67_PCTR_MODE_AGGREGATE); |
|
wrperfmon(PERFMON_CMD_DESIRED_EVENTS, cpuc->config); |
|
wrperfmon(PERFMON_CMD_ENABLE, cpuc->idx_mask); |
|
} |
|
} |
|
|
|
|
|
/* |
|
* Main entry point - disable HW performance counters. |
|
*/ |
|
|
|
static void alpha_pmu_disable(struct pmu *pmu) |
|
{ |
|
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
|
|
|
if (!cpuc->enabled) |
|
return; |
|
|
|
cpuc->enabled = 0; |
|
cpuc->n_added = 0; |
|
|
|
wrperfmon(PERFMON_CMD_DISABLE, cpuc->idx_mask); |
|
} |
|
|
|
static struct pmu pmu = { |
|
.pmu_enable = alpha_pmu_enable, |
|
.pmu_disable = alpha_pmu_disable, |
|
.event_init = alpha_pmu_event_init, |
|
.add = alpha_pmu_add, |
|
.del = alpha_pmu_del, |
|
.start = alpha_pmu_start, |
|
.stop = alpha_pmu_stop, |
|
.read = alpha_pmu_read, |
|
.capabilities = PERF_PMU_CAP_NO_EXCLUDE, |
|
}; |
|
|
|
|
|
/* |
|
* Main entry point - don't know when this is called but it |
|
* obviously dumps debug info. |
|
*/ |
|
void perf_event_print_debug(void) |
|
{ |
|
unsigned long flags; |
|
unsigned long pcr; |
|
int pcr0, pcr1; |
|
int cpu; |
|
|
|
if (!supported_cpu()) |
|
return; |
|
|
|
local_irq_save(flags); |
|
|
|
cpu = smp_processor_id(); |
|
|
|
pcr = wrperfmon(PERFMON_CMD_READ, 0); |
|
pcr0 = (pcr >> alpha_pmu->pmc_count_shift[0]) & alpha_pmu->pmc_count_mask[0]; |
|
pcr1 = (pcr >> alpha_pmu->pmc_count_shift[1]) & alpha_pmu->pmc_count_mask[1]; |
|
|
|
pr_info("CPU#%d: PCTR0[%06x] PCTR1[%06x]\n", cpu, pcr0, pcr1); |
|
|
|
local_irq_restore(flags); |
|
} |
|
|
|
|
|
/* |
|
* Performance Monitoring Interrupt Service Routine called when a PMC |
|
* overflows. The PMC that overflowed is passed in la_ptr. |
|
*/ |
|
static void alpha_perf_event_irq_handler(unsigned long la_ptr, |
|
struct pt_regs *regs) |
|
{ |
|
struct cpu_hw_events *cpuc; |
|
struct perf_sample_data data; |
|
struct perf_event *event; |
|
struct hw_perf_event *hwc; |
|
int idx, j; |
|
|
|
__this_cpu_inc(irq_pmi_count); |
|
cpuc = this_cpu_ptr(&cpu_hw_events); |
|
|
|
/* Completely counting through the PMC's period to trigger a new PMC |
|
* overflow interrupt while in this interrupt routine is utterly |
|
* disastrous! The EV6 and EV67 counters are sufficiently large to |
|
* prevent this but to be really sure disable the PMCs. |
|
*/ |
|
wrperfmon(PERFMON_CMD_DISABLE, cpuc->idx_mask); |
|
|
|
/* la_ptr is the counter that overflowed. */ |
|
if (unlikely(la_ptr >= alpha_pmu->num_pmcs)) { |
|
/* This should never occur! */ |
|
irq_err_count++; |
|
pr_warn("PMI: silly index %ld\n", la_ptr); |
|
wrperfmon(PERFMON_CMD_ENABLE, cpuc->idx_mask); |
|
return; |
|
} |
|
|
|
idx = la_ptr; |
|
|
|
for (j = 0; j < cpuc->n_events; j++) { |
|
if (cpuc->current_idx[j] == idx) |
|
break; |
|
} |
|
|
|
if (unlikely(j == cpuc->n_events)) { |
|
/* This can occur if the event is disabled right on a PMC overflow. */ |
|
wrperfmon(PERFMON_CMD_ENABLE, cpuc->idx_mask); |
|
return; |
|
} |
|
|
|
event = cpuc->event[j]; |
|
|
|
if (unlikely(!event)) { |
|
/* This should never occur! */ |
|
irq_err_count++; |
|
pr_warn("PMI: No event at index %d!\n", idx); |
|
wrperfmon(PERFMON_CMD_ENABLE, cpuc->idx_mask); |
|
return; |
|
} |
|
|
|
hwc = &event->hw; |
|
alpha_perf_event_update(event, hwc, idx, alpha_pmu->pmc_max_period[idx]+1); |
|
perf_sample_data_init(&data, 0, hwc->last_period); |
|
|
|
if (alpha_perf_event_set_period(event, hwc, idx)) { |
|
if (perf_event_overflow(event, &data, regs)) { |
|
/* Interrupts coming too quickly; "throttle" the |
|
* counter, i.e., disable it for a little while. |
|
*/ |
|
alpha_pmu_stop(event, 0); |
|
} |
|
} |
|
wrperfmon(PERFMON_CMD_ENABLE, cpuc->idx_mask); |
|
|
|
return; |
|
} |
|
|
|
|
|
|
|
/* |
|
* Init call to initialise performance events at kernel startup. |
|
*/ |
|
int __init init_hw_perf_events(void) |
|
{ |
|
pr_info("Performance events: "); |
|
|
|
if (!supported_cpu()) { |
|
pr_cont("No support for your CPU.\n"); |
|
return 0; |
|
} |
|
|
|
pr_cont("Supported CPU type!\n"); |
|
|
|
/* Override performance counter IRQ vector */ |
|
|
|
perf_irq = alpha_perf_event_irq_handler; |
|
|
|
/* And set up PMU specification */ |
|
alpha_pmu = &ev67_pmu; |
|
|
|
perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
|
|
|
return 0; |
|
} |
|
early_initcall(init_hw_perf_events);
|
|
|