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616 lines
16 KiB
616 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* linux/arch/alpha/kernel/core_mcpcia.c |
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* |
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* Based on code written by David A Rusling ([email protected]). |
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* |
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* Code common to all MCbus-PCI Adaptor core logic chipsets |
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*/ |
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|
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#define __EXTERN_INLINE inline |
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#include <asm/io.h> |
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#include <asm/core_mcpcia.h> |
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#undef __EXTERN_INLINE |
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|
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#include <linux/types.h> |
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#include <linux/pci.h> |
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#include <linux/sched.h> |
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#include <linux/init.h> |
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#include <linux/delay.h> |
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|
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#include <asm/ptrace.h> |
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|
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#include "proto.h" |
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#include "pci_impl.h" |
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|
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/* |
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* NOTE: Herein lie back-to-back mb instructions. They are magic. |
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* One plausible explanation is that the i/o controller does not properly |
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* handle the system transaction. Another involves timing. Ho hum. |
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*/ |
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|
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/* |
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* BIOS32-style PCI interface: |
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*/ |
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|
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#define DEBUG_CFG 0 |
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|
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#if DEBUG_CFG |
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# define DBG_CFG(args) printk args |
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#else |
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# define DBG_CFG(args) |
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#endif |
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|
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/* |
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* Given a bus, device, and function number, compute resulting |
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* configuration space address and setup the MCPCIA_HAXR2 register |
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* accordingly. It is therefore not safe to have concurrent |
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* invocations to configuration space access routines, but there |
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* really shouldn't be any need for this. |
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* |
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* Type 0: |
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* |
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* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 |
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* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 |
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
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* | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0| |
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
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* |
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* 31:11 Device select bit. |
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* 10:8 Function number |
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* 7:2 Register number |
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* |
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* Type 1: |
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* |
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* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 |
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* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 |
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
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* | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| |
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
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* |
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* 31:24 reserved |
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* 23:16 bus number (8 bits = 128 possible buses) |
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* 15:11 Device number (5 bits) |
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* 10:8 function number |
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* 7:2 register number |
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* |
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* Notes: |
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* The function number selects which function of a multi-function device |
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* (e.g., SCSI and Ethernet). |
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* |
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* The register selects a DWORD (32 bit) register offset. Hence it |
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* doesn't get shifted by 2 bits as we want to "drop" the bottom two |
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* bits. |
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*/ |
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|
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static unsigned int |
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conf_read(unsigned long addr, unsigned char type1, |
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struct pci_controller *hose) |
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{ |
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unsigned long flags; |
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unsigned long mid = MCPCIA_HOSE2MID(hose->index); |
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unsigned int stat0, value, cpu; |
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|
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cpu = smp_processor_id(); |
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|
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local_irq_save(flags); |
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|
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DBG_CFG(("conf_read(addr=0x%lx, type1=%d, hose=%d)\n", |
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addr, type1, mid)); |
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|
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/* Reset status register to avoid losing errors. */ |
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stat0 = *(vuip)MCPCIA_CAP_ERR(mid); |
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*(vuip)MCPCIA_CAP_ERR(mid) = stat0; |
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mb(); |
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*(vuip)MCPCIA_CAP_ERR(mid); |
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DBG_CFG(("conf_read: MCPCIA_CAP_ERR(%d) was 0x%x\n", mid, stat0)); |
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|
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mb(); |
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draina(); |
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mcheck_expected(cpu) = 1; |
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mcheck_taken(cpu) = 0; |
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mcheck_extra(cpu) = mid; |
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mb(); |
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|
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/* Access configuration space. */ |
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value = *((vuip)addr); |
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mb(); |
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mb(); /* magic */ |
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|
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if (mcheck_taken(cpu)) { |
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mcheck_taken(cpu) = 0; |
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value = 0xffffffffU; |
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mb(); |
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} |
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mcheck_expected(cpu) = 0; |
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mb(); |
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|
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DBG_CFG(("conf_read(): finished\n")); |
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|
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local_irq_restore(flags); |
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return value; |
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} |
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|
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static void |
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conf_write(unsigned long addr, unsigned int value, unsigned char type1, |
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struct pci_controller *hose) |
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{ |
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unsigned long flags; |
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unsigned long mid = MCPCIA_HOSE2MID(hose->index); |
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unsigned int stat0, cpu; |
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|
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cpu = smp_processor_id(); |
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|
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local_irq_save(flags); /* avoid getting hit by machine check */ |
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|
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/* Reset status register to avoid losing errors. */ |
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stat0 = *(vuip)MCPCIA_CAP_ERR(mid); |
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*(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb(); |
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*(vuip)MCPCIA_CAP_ERR(mid); |
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DBG_CFG(("conf_write: MCPCIA CAP_ERR(%d) was 0x%x\n", mid, stat0)); |
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|
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draina(); |
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mcheck_expected(cpu) = 1; |
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mcheck_extra(cpu) = mid; |
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mb(); |
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|
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/* Access configuration space. */ |
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*((vuip)addr) = value; |
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mb(); |
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mb(); /* magic */ |
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*(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */ |
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mcheck_expected(cpu) = 0; |
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mb(); |
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|
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DBG_CFG(("conf_write(): finished\n")); |
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local_irq_restore(flags); |
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} |
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|
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static int |
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mk_conf_addr(struct pci_bus *pbus, unsigned int devfn, int where, |
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struct pci_controller *hose, unsigned long *pci_addr, |
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unsigned char *type1) |
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{ |
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u8 bus = pbus->number; |
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unsigned long addr; |
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DBG_CFG(("mk_conf_addr(bus=%d,devfn=0x%x,hose=%d,where=0x%x," |
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" pci_addr=0x%p, type1=0x%p)\n", |
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bus, devfn, hose->index, where, pci_addr, type1)); |
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|
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/* Type 1 configuration cycle for *ALL* busses. */ |
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*type1 = 1; |
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|
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if (!pbus->parent) /* No parent means peer PCI bus. */ |
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bus = 0; |
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addr = (bus << 16) | (devfn << 8) | (where); |
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addr <<= 5; /* swizzle for SPARSE */ |
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addr |= hose->config_space_base; |
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*pci_addr = addr; |
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DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr)); |
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return 0; |
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} |
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|
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static int |
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mcpcia_read_config(struct pci_bus *bus, unsigned int devfn, int where, |
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int size, u32 *value) |
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{ |
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struct pci_controller *hose = bus->sysdata; |
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unsigned long addr, w; |
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unsigned char type1; |
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if (mk_conf_addr(bus, devfn, where, hose, &addr, &type1)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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addr |= (size - 1) * 8; |
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w = conf_read(addr, type1, hose); |
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switch (size) { |
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case 1: |
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*value = __kernel_extbl(w, where & 3); |
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break; |
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case 2: |
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*value = __kernel_extwl(w, where & 3); |
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break; |
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case 4: |
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*value = w; |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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|
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static int |
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mcpcia_write_config(struct pci_bus *bus, unsigned int devfn, int where, |
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int size, u32 value) |
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{ |
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struct pci_controller *hose = bus->sysdata; |
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unsigned long addr; |
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unsigned char type1; |
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if (mk_conf_addr(bus, devfn, where, hose, &addr, &type1)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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addr |= (size - 1) * 8; |
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value = __kernel_insql(value, where & 3); |
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conf_write(addr, value, type1, hose); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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|
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struct pci_ops mcpcia_pci_ops = |
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{ |
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.read = mcpcia_read_config, |
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.write = mcpcia_write_config, |
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}; |
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|
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void |
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mcpcia_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end) |
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{ |
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wmb(); |
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*(vuip)MCPCIA_SG_TBIA(MCPCIA_HOSE2MID(hose->index)) = 0; |
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mb(); |
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} |
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|
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static int __init |
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mcpcia_probe_hose(int h) |
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{ |
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int cpu = smp_processor_id(); |
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int mid = MCPCIA_HOSE2MID(h); |
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unsigned int pci_rev; |
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|
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/* Gotta be REAL careful. If hose is absent, we get an mcheck. */ |
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mb(); |
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mb(); |
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draina(); |
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wrmces(7); |
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mcheck_expected(cpu) = 2; /* indicates probing */ |
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mcheck_taken(cpu) = 0; |
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mcheck_extra(cpu) = mid; |
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mb(); |
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/* Access the bus revision word. */ |
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pci_rev = *(vuip)MCPCIA_REV(mid); |
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mb(); |
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mb(); /* magic */ |
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if (mcheck_taken(cpu)) { |
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mcheck_taken(cpu) = 0; |
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pci_rev = 0xffffffff; |
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mb(); |
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} |
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mcheck_expected(cpu) = 0; |
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mb(); |
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return (pci_rev >> 16) == PCI_CLASS_BRIDGE_HOST; |
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} |
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static void __init |
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mcpcia_new_hose(int h) |
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{ |
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struct pci_controller *hose; |
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struct resource *io, *mem, *hae_mem; |
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int mid = MCPCIA_HOSE2MID(h); |
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hose = alloc_pci_controller(); |
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if (h == 0) |
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pci_isa_hose = hose; |
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io = alloc_resource(); |
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mem = alloc_resource(); |
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hae_mem = alloc_resource(); |
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|
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hose->io_space = io; |
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hose->mem_space = hae_mem; |
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hose->sparse_mem_base = MCPCIA_SPARSE(mid) - IDENT_ADDR; |
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hose->dense_mem_base = MCPCIA_DENSE(mid) - IDENT_ADDR; |
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hose->sparse_io_base = MCPCIA_IO(mid) - IDENT_ADDR; |
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hose->dense_io_base = 0; |
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hose->config_space_base = MCPCIA_CONF(mid); |
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hose->index = h; |
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io->start = MCPCIA_IO(mid) - MCPCIA_IO_BIAS; |
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io->end = io->start + 0xffff; |
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io->name = pci_io_names[h]; |
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io->flags = IORESOURCE_IO; |
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mem->start = MCPCIA_DENSE(mid) - MCPCIA_MEM_BIAS; |
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mem->end = mem->start + 0xffffffff; |
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mem->name = pci_mem_names[h]; |
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mem->flags = IORESOURCE_MEM; |
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hae_mem->start = mem->start; |
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hae_mem->end = mem->start + MCPCIA_MEM_MASK; |
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hae_mem->name = pci_hae0_name; |
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hae_mem->flags = IORESOURCE_MEM; |
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if (request_resource(&ioport_resource, io) < 0) |
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printk(KERN_ERR "Failed to request IO on hose %d\n", h); |
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if (request_resource(&iomem_resource, mem) < 0) |
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printk(KERN_ERR "Failed to request MEM on hose %d\n", h); |
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if (request_resource(mem, hae_mem) < 0) |
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printk(KERN_ERR "Failed to request HAE_MEM on hose %d\n", h); |
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} |
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static void |
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mcpcia_pci_clr_err(int mid) |
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{ |
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*(vuip)MCPCIA_CAP_ERR(mid); |
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*(vuip)MCPCIA_CAP_ERR(mid) = 0xffffffff; /* Clear them all. */ |
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mb(); |
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*(vuip)MCPCIA_CAP_ERR(mid); /* Re-read for force write. */ |
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} |
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static void __init |
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mcpcia_startup_hose(struct pci_controller *hose) |
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{ |
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int mid = MCPCIA_HOSE2MID(hose->index); |
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unsigned int tmp; |
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mcpcia_pci_clr_err(mid); |
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/* |
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* Set up error reporting. |
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*/ |
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tmp = *(vuip)MCPCIA_CAP_ERR(mid); |
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tmp |= 0x0006; /* master/target abort */ |
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*(vuip)MCPCIA_CAP_ERR(mid) = tmp; |
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mb(); |
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tmp = *(vuip)MCPCIA_CAP_ERR(mid); |
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/* |
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* Set up the PCI->physical memory translation windows. |
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* |
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* Window 0 is scatter-gather 8MB at 8MB (for isa) |
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* Window 1 is scatter-gather (up to) 1GB at 1GB (for pci) |
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* Window 2 is direct access 2GB at 2GB |
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*/ |
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hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, |
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SMP_CACHE_BYTES); |
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hose->sg_pci = iommu_arena_new(hose, 0x40000000, |
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size_for_memory(0x40000000), |
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SMP_CACHE_BYTES); |
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__direct_map_base = 0x80000000; |
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__direct_map_size = 0x80000000; |
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*(vuip)MCPCIA_W0_BASE(mid) = hose->sg_isa->dma_base | 3; |
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*(vuip)MCPCIA_W0_MASK(mid) = (hose->sg_isa->size - 1) & 0xfff00000; |
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*(vuip)MCPCIA_T0_BASE(mid) = virt_to_phys(hose->sg_isa->ptes) >> 8; |
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|
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*(vuip)MCPCIA_W1_BASE(mid) = hose->sg_pci->dma_base | 3; |
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*(vuip)MCPCIA_W1_MASK(mid) = (hose->sg_pci->size - 1) & 0xfff00000; |
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*(vuip)MCPCIA_T1_BASE(mid) = virt_to_phys(hose->sg_pci->ptes) >> 8; |
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|
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*(vuip)MCPCIA_W2_BASE(mid) = __direct_map_base | 1; |
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*(vuip)MCPCIA_W2_MASK(mid) = (__direct_map_size - 1) & 0xfff00000; |
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*(vuip)MCPCIA_T2_BASE(mid) = 0; |
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|
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*(vuip)MCPCIA_W3_BASE(mid) = 0x0; |
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mcpcia_pci_tbi(hose, 0, -1); |
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*(vuip)MCPCIA_HBASE(mid) = 0x0; |
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mb(); |
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*(vuip)MCPCIA_HAE_MEM(mid) = 0U; |
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mb(); |
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*(vuip)MCPCIA_HAE_MEM(mid); /* read it back. */ |
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*(vuip)MCPCIA_HAE_IO(mid) = 0; |
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mb(); |
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*(vuip)MCPCIA_HAE_IO(mid); /* read it back. */ |
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} |
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void __init |
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mcpcia_init_arch(void) |
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{ |
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/* With multiple PCI busses, we play with I/O as physical addrs. */ |
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ioport_resource.end = ~0UL; |
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|
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/* Allocate hose 0. That's the one that all the ISA junk hangs |
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off of, from which we'll be registering stuff here in a bit. |
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Other hose detection is done in mcpcia_init_hoses, which is |
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called from init_IRQ. */ |
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mcpcia_new_hose(0); |
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} |
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|
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/* This is called from init_IRQ, since we cannot take interrupts |
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before then. Which means we cannot do this in init_arch. */ |
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|
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void __init |
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mcpcia_init_hoses(void) |
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{ |
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struct pci_controller *hose; |
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int hose_count; |
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int h; |
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|
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/* First, find how many hoses we have. */ |
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hose_count = 0; |
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for (h = 0; h < MCPCIA_MAX_HOSES; ++h) { |
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if (mcpcia_probe_hose(h)) { |
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if (h != 0) |
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mcpcia_new_hose(h); |
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hose_count++; |
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} |
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} |
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printk("mcpcia_init_hoses: found %d hoses\n", hose_count); |
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|
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/* Now do init for each hose. */ |
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for (hose = hose_head; hose; hose = hose->next) |
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mcpcia_startup_hose(hose); |
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} |
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|
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static void |
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mcpcia_print_uncorrectable(struct el_MCPCIA_uncorrected_frame_mcheck *logout) |
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{ |
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struct el_common_EV5_uncorrectable_mcheck *frame; |
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int i; |
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frame = &logout->procdata; |
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|
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/* Print PAL fields */ |
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for (i = 0; i < 24; i += 2) { |
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printk(" paltmp[%d-%d] = %16lx %16lx\n", |
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i, i+1, frame->paltemp[i], frame->paltemp[i+1]); |
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} |
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for (i = 0; i < 8; i += 2) { |
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printk(" shadow[%d-%d] = %16lx %16lx\n", |
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i, i+1, frame->shadow[i], |
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frame->shadow[i+1]); |
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} |
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printk(" Addr of excepting instruction = %16lx\n", |
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frame->exc_addr); |
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printk(" Summary of arithmetic traps = %16lx\n", |
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frame->exc_sum); |
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printk(" Exception mask = %16lx\n", |
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frame->exc_mask); |
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printk(" Base address for PALcode = %16lx\n", |
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frame->pal_base); |
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printk(" Interrupt Status Reg = %16lx\n", |
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frame->isr); |
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printk(" CURRENT SETUP OF EV5 IBOX = %16lx\n", |
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frame->icsr); |
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printk(" I-CACHE Reg %s parity error = %16lx\n", |
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(frame->ic_perr_stat & 0x800L) ? |
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"Data" : "Tag", |
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frame->ic_perr_stat); |
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printk(" D-CACHE error Reg = %16lx\n", |
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frame->dc_perr_stat); |
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if (frame->dc_perr_stat & 0x2) { |
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switch (frame->dc_perr_stat & 0x03c) { |
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case 8: |
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printk(" Data error in bank 1\n"); |
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break; |
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case 4: |
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printk(" Data error in bank 0\n"); |
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break; |
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case 20: |
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printk(" Tag error in bank 1\n"); |
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break; |
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case 10: |
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printk(" Tag error in bank 0\n"); |
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break; |
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} |
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} |
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printk(" Effective VA = %16lx\n", |
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frame->va); |
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printk(" Reason for D-stream = %16lx\n", |
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frame->mm_stat); |
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printk(" EV5 SCache address = %16lx\n", |
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frame->sc_addr); |
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printk(" EV5 SCache TAG/Data parity = %16lx\n", |
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frame->sc_stat); |
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printk(" EV5 BC_TAG_ADDR = %16lx\n", |
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frame->bc_tag_addr); |
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printk(" EV5 EI_ADDR: Phys addr of Xfer = %16lx\n", |
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frame->ei_addr); |
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printk(" Fill Syndrome = %16lx\n", |
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frame->fill_syndrome); |
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printk(" EI_STAT reg = %16lx\n", |
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frame->ei_stat); |
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printk(" LD_LOCK = %16lx\n", |
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frame->ld_lock); |
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} |
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|
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static void |
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mcpcia_print_system_area(unsigned long la_ptr) |
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{ |
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struct el_common *frame; |
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struct pci_controller *hose; |
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|
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struct IOD_subpacket { |
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unsigned long base; |
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unsigned int whoami; |
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unsigned int rsvd1; |
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unsigned int pci_rev; |
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unsigned int cap_ctrl; |
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unsigned int hae_mem; |
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unsigned int hae_io; |
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unsigned int int_ctl; |
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unsigned int int_reg; |
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unsigned int int_mask0; |
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unsigned int int_mask1; |
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unsigned int mc_err0; |
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unsigned int mc_err1; |
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unsigned int cap_err; |
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unsigned int rsvd2; |
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unsigned int pci_err1; |
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unsigned int mdpa_stat; |
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unsigned int mdpa_syn; |
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unsigned int mdpb_stat; |
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unsigned int mdpb_syn; |
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unsigned int rsvd3; |
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unsigned int rsvd4; |
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unsigned int rsvd5; |
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} *iodpp; |
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frame = (struct el_common *)la_ptr; |
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iodpp = (struct IOD_subpacket *) (la_ptr + frame->sys_offset); |
||
|
||
for (hose = hose_head; hose; hose = hose->next, iodpp++) { |
||
|
||
printk("IOD %d Register Subpacket - Bridge Base Address %16lx\n", |
||
hose->index, iodpp->base); |
||
printk(" WHOAMI = %8x\n", iodpp->whoami); |
||
printk(" PCI_REV = %8x\n", iodpp->pci_rev); |
||
printk(" CAP_CTRL = %8x\n", iodpp->cap_ctrl); |
||
printk(" HAE_MEM = %8x\n", iodpp->hae_mem); |
||
printk(" HAE_IO = %8x\n", iodpp->hae_io); |
||
printk(" INT_CTL = %8x\n", iodpp->int_ctl); |
||
printk(" INT_REG = %8x\n", iodpp->int_reg); |
||
printk(" INT_MASK0 = %8x\n", iodpp->int_mask0); |
||
printk(" INT_MASK1 = %8x\n", iodpp->int_mask1); |
||
printk(" MC_ERR0 = %8x\n", iodpp->mc_err0); |
||
printk(" MC_ERR1 = %8x\n", iodpp->mc_err1); |
||
printk(" CAP_ERR = %8x\n", iodpp->cap_err); |
||
printk(" PCI_ERR1 = %8x\n", iodpp->pci_err1); |
||
printk(" MDPA_STAT = %8x\n", iodpp->mdpa_stat); |
||
printk(" MDPA_SYN = %8x\n", iodpp->mdpa_syn); |
||
printk(" MDPB_STAT = %8x\n", iodpp->mdpb_stat); |
||
printk(" MDPB_SYN = %8x\n", iodpp->mdpb_syn); |
||
} |
||
} |
||
|
||
void |
||
mcpcia_machine_check(unsigned long vector, unsigned long la_ptr) |
||
{ |
||
struct el_MCPCIA_uncorrected_frame_mcheck *mchk_logout; |
||
unsigned int cpu = smp_processor_id(); |
||
int expected; |
||
|
||
mchk_logout = (struct el_MCPCIA_uncorrected_frame_mcheck *)la_ptr; |
||
expected = mcheck_expected(cpu); |
||
|
||
mb(); |
||
mb(); /* magic */ |
||
draina(); |
||
|
||
switch (expected) { |
||
case 0: |
||
{ |
||
/* FIXME: how do we figure out which hose the |
||
error was on? */ |
||
struct pci_controller *hose; |
||
for (hose = hose_head; hose; hose = hose->next) |
||
mcpcia_pci_clr_err(MCPCIA_HOSE2MID(hose->index)); |
||
break; |
||
} |
||
case 1: |
||
mcpcia_pci_clr_err(mcheck_extra(cpu)); |
||
break; |
||
default: |
||
/* Otherwise, we're being called from mcpcia_probe_hose |
||
and there's no hose clear an error from. */ |
||
break; |
||
} |
||
|
||
wrmces(0x7); |
||
mb(); |
||
|
||
process_mcheck_info(vector, la_ptr, "MCPCIA", expected != 0); |
||
if (!expected && vector != 0x620 && vector != 0x630) { |
||
mcpcia_print_uncorrectable(mchk_logout); |
||
mcpcia_print_system_area(la_ptr); |
||
} |
||
}
|
||
|