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36 lines
794 B
Verilog
36 lines
794 B
Verilog
`include "settings.h"
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module MEM_Reg
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(
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input clk,
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input rst,
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input [`REG_FILE_DEPTH-1:0] dst,
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input [`WORD_WIDTH-1:0] ALU_res,
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input [`WORD_WIDTH-1:0] mem,
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input mem_read, WB_en,
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output reg [`REG_FILE_DEPTH-1:0] dst_out,
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output reg [`WORD_WIDTH-1:0] ALU_res_out,
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output reg [`WORD_WIDTH-1:0] mem_out,
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output reg mem_read_out, WB_en_out
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);
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always @(posedge clk, posedge rst) begin
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if(rst) begin
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dst_out <= 0;
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ALU_res_out <= 0;
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mem_out <= 0;
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mem_read_out <= 0;
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WB_en_out <= 0;
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end
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else begin
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dst_out <= dst;
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ALU_res_out <= ALU_res;
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mem_out <= mem;
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mem_read_out <= mem_read;
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WB_en_out <= WB_en;
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end
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end
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endmodule
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