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112 lines
2.7 KiB
112 lines
2.7 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright (C) 2016 Synopsys, Inc. All rights reserved. |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <timer.h> |
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#include <asm/arcregs.h> |
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#include <asm/io.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define NH_MODE (1 << 1) |
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/* |
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* ARC timer control registers are mapped to auxiliary address space. |
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* There are special ARC asm command to access that addresses. |
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* Therefore we use built-in functions to read from and write to timer |
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* control register. |
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*/ |
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/* Driver private data. Contains timer id. Could be either 0 or 1. */ |
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struct arc_timer_priv { |
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uint timer_id; |
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}; |
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static int arc_timer_get_count(struct udevice *dev, u64 *count) |
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{ |
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u32 val = 0; |
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struct arc_timer_priv *priv = dev_get_priv(dev); |
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switch (priv->timer_id) { |
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case 0: |
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val = read_aux_reg(ARC_AUX_TIMER0_CNT); |
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break; |
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case 1: |
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val = read_aux_reg(ARC_AUX_TIMER1_CNT); |
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break; |
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} |
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*count = timer_conv_64(val); |
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return 0; |
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} |
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static int arc_timer_probe(struct udevice *dev) |
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{ |
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int id; |
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struct arc_timer_priv *priv = dev_get_priv(dev); |
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/* Get registers offset and size */ |
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id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1); |
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if (id < 0) |
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return -EINVAL; |
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if (id > 1) |
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return -ENXIO; |
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priv->timer_id = (uint)id; |
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/* |
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* In ARC core there're special registers (Auxiliary or AUX) in its |
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* separate memory space that are used for accessing some hardware |
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* features of the core. They are not mapped in normal memory space |
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* and also always have the same location regardless core configuration. |
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* Thus to simplify understanding of the programming model we chose to |
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* access AUX regs of Timer0 and Timer1 separately instead of using |
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* offsets from some base address. |
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*/ |
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switch (priv->timer_id) { |
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case 0: |
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/* Disable timer if CPU is halted */ |
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write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE); |
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/* Set max value for counter/timer */ |
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write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff); |
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/* Set initial count value and restart counter/timer */ |
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write_aux_reg(ARC_AUX_TIMER0_CNT, 0); |
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break; |
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case 1: |
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/* Disable timer if CPU is halted */ |
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write_aux_reg(ARC_AUX_TIMER1_CTRL, NH_MODE); |
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/* Set max value for counter/timer */ |
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write_aux_reg(ARC_AUX_TIMER1_LIMIT, 0xffffffff); |
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/* Set initial count value and restart counter/timer */ |
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write_aux_reg(ARC_AUX_TIMER1_CNT, 0); |
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break; |
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} |
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return 0; |
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} |
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static const struct timer_ops arc_timer_ops = { |
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.get_count = arc_timer_get_count, |
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}; |
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static const struct udevice_id arc_timer_ids[] = { |
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{ .compatible = "snps,arc-timer" }, |
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{} |
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}; |
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U_BOOT_DRIVER(arc_timer) = { |
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.name = "arc_timer", |
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.id = UCLASS_TIMER, |
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.of_match = arc_timer_ids, |
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.probe = arc_timer_probe, |
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.ops = &arc_timer_ops, |
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.flags = DM_FLAG_PRE_RELOC, |
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.priv_auto_alloc_size = sizeof(struct arc_timer_priv), |
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};
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