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629 lines
14 KiB
629 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright (C) 2010 |
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* Rob Emanuele <[email protected]> |
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* Reinhard Meyer, EMK Elektronik <[email protected]> |
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* |
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* Original Driver: |
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* Copyright (C) 2004-2006 Atmel Corporation |
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*/ |
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|
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#include <common.h> |
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#include <clk.h> |
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#include <dm.h> |
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#include <mmc.h> |
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#include <part.h> |
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#include <malloc.h> |
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#include <asm/io.h> |
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#include <linux/errno.h> |
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#include <asm/byteorder.h> |
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#include <asm/arch/clk.h> |
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#include <asm/arch/hardware.h> |
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#include "atmel_mci.h" |
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|
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#ifndef CONFIG_SYS_MMC_CLK_OD |
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# define CONFIG_SYS_MMC_CLK_OD 150000 |
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#endif |
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|
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#define MMC_DEFAULT_BLKLEN 512 |
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|
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#if defined(CONFIG_ATMEL_MCI_PORTB) |
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# define MCI_BUS 1 |
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#else |
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# define MCI_BUS 0 |
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#endif |
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|
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#ifdef CONFIG_DM_MMC |
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struct atmel_mci_plat { |
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struct mmc mmc; |
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struct mmc_config cfg; |
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struct atmel_mci *mci; |
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}; |
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#endif |
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|
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struct atmel_mci_priv { |
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#ifndef CONFIG_DM_MMC |
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struct mmc_config cfg; |
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struct atmel_mci *mci; |
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#endif |
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unsigned int initialized:1; |
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unsigned int curr_clk; |
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#ifdef CONFIG_DM_MMC |
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ulong bus_clk_rate; |
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#endif |
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}; |
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|
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/* Read Atmel MCI IP version */ |
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static unsigned int atmel_mci_get_version(struct atmel_mci *mci) |
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{ |
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return readl(&mci->version) & 0x00000fff; |
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} |
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|
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/* |
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* Print command and status: |
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* |
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* - always when DEBUG is defined |
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* - on command errors |
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*/ |
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static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg) |
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{ |
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debug("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n", |
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cmdr, cmdr & 0x3F, arg, status, msg); |
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} |
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|
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static inline void mci_set_blklen(atmel_mci_t *mci, int blklen) |
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{ |
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unsigned int version = atmel_mci_get_version(mci); |
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|
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blklen &= 0xfffc; |
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|
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/* MCI IP version >= 0x200 has blkr */ |
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if (version >= 0x200) |
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writel(MMCI_BFINS(BLKLEN, blklen, readl(&mci->blkr)), |
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&mci->blkr); |
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else |
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writel(MMCI_BFINS(BLKLEN, blklen, readl(&mci->mr)), &mci->mr); |
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} |
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|
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/* Setup for MCI Clock and Block Size */ |
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#ifdef CONFIG_DM_MMC |
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static void mci_set_mode(struct udevice *dev, u32 hz, u32 blklen) |
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{ |
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struct atmel_mci_plat *plat = dev_get_platdata(dev); |
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struct atmel_mci_priv *priv = dev_get_priv(dev); |
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struct mmc *mmc = &plat->mmc; |
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u32 bus_hz = priv->bus_clk_rate; |
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atmel_mci_t *mci = plat->mci; |
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#else |
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static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) |
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{ |
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struct atmel_mci_priv *priv = mmc->priv; |
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u32 bus_hz = get_mci_clk_rate(); |
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atmel_mci_t *mci = priv->mci; |
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#endif |
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|
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u32 clkdiv = 255; |
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unsigned int version = atmel_mci_get_version(mci); |
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u32 clkodd = 0; |
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u32 mr; |
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|
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debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n", |
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bus_hz, hz, blklen); |
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if (hz > 0) { |
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if (version >= 0x500) { |
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clkdiv = DIV_ROUND_UP(bus_hz, hz) - 2; |
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if (clkdiv > 511) |
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clkdiv = 511; |
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|
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clkodd = clkdiv & 1; |
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clkdiv >>= 1; |
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|
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debug("mci: setting clock %u Hz, block size %u\n", |
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bus_hz / (clkdiv * 2 + clkodd + 2), blklen); |
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} else { |
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/* find clkdiv yielding a rate <= than requested */ |
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for (clkdiv = 0; clkdiv < 255; clkdiv++) { |
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if ((bus_hz / (clkdiv + 1) / 2) <= hz) |
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break; |
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} |
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debug("mci: setting clock %u Hz, block size %u\n", |
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(bus_hz / (clkdiv + 1)) / 2, blklen); |
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|
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} |
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} |
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if (version >= 0x500) |
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priv->curr_clk = bus_hz / (clkdiv * 2 + clkodd + 2); |
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else |
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priv->curr_clk = (bus_hz / (clkdiv + 1)) / 2; |
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|
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mr = MMCI_BF(CLKDIV, clkdiv); |
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|
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/* MCI IP version >= 0x200 has R/WPROOF */ |
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if (version >= 0x200) |
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mr |= MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF); |
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|
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/* |
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* MCI IP version >= 0x500 use bit 16 as clkodd. |
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* MCI IP version < 0x500 use upper 16 bits for blklen. |
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*/ |
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if (version >= 0x500) |
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mr |= MMCI_BF(CLKODD, clkodd); |
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|
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writel(mr, &mci->mr); |
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|
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mci_set_blklen(mci, blklen); |
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|
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if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS) |
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writel(MMCI_BIT(HSMODE), &mci->cfg); |
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|
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priv->initialized = 1; |
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} |
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|
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/* Return the CMDR with flags for a given command and data packet */ |
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static u32 mci_encode_cmd( |
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struct mmc_cmd *cmd, struct mmc_data *data, u32* error_flags) |
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{ |
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u32 cmdr = 0; |
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|
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/* Default Flags for Errors */ |
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*error_flags |= (MMCI_BIT(DTOE) | MMCI_BIT(RDIRE) | MMCI_BIT(RENDE) | |
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MMCI_BIT(RINDE) | MMCI_BIT(RTOE)); |
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|
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/* Default Flags for the Command */ |
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cmdr |= MMCI_BIT(MAXLAT); |
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|
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if (data) { |
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cmdr |= MMCI_BF(TRCMD, 1); |
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if (data->blocks > 1) |
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cmdr |= MMCI_BF(TRTYP, 1); |
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if (data->flags & MMC_DATA_READ) |
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cmdr |= MMCI_BIT(TRDIR); |
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} |
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|
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if (cmd->resp_type & MMC_RSP_CRC) |
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*error_flags |= MMCI_BIT(RCRCE); |
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if (cmd->resp_type & MMC_RSP_136) |
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cmdr |= MMCI_BF(RSPTYP, 2); |
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else if (cmd->resp_type & MMC_RSP_BUSY) |
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cmdr |= MMCI_BF(RSPTYP, 3); |
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else if (cmd->resp_type & MMC_RSP_PRESENT) |
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cmdr |= MMCI_BF(RSPTYP, 1); |
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|
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return cmdr | MMCI_BF(CMDNB, cmd->cmdidx); |
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} |
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|
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/* Entered into function pointer in mci_send_cmd */ |
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static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags) |
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{ |
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u32 status; |
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|
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do { |
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status = readl(&mci->sr); |
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if (status & (error_flags | MMCI_BIT(OVRE))) |
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goto io_fail; |
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} while (!(status & MMCI_BIT(RXRDY))); |
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|
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if (status & MMCI_BIT(RXRDY)) { |
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*data = readl(&mci->rdr); |
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status = 0; |
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} |
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io_fail: |
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return status; |
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} |
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|
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/* Entered into function pointer in mci_send_cmd */ |
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static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags) |
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{ |
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u32 status; |
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|
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do { |
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status = readl(&mci->sr); |
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if (status & (error_flags | MMCI_BIT(UNRE))) |
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goto io_fail; |
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} while (!(status & MMCI_BIT(TXRDY))); |
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|
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if (status & MMCI_BIT(TXRDY)) { |
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writel(*data, &mci->tdr); |
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status = 0; |
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} |
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io_fail: |
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return status; |
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} |
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|
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/* |
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* Entered into mmc structure during driver init |
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* |
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* Sends a command out on the bus and deals with the block data. |
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* Takes the mmc pointer, a command pointer, and an optional data pointer. |
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*/ |
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#ifdef CONFIG_DM_MMC |
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static int atmel_mci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, |
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struct mmc_data *data) |
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{ |
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struct atmel_mci_plat *plat = dev_get_platdata(dev); |
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struct atmel_mci_priv *priv = dev_get_priv(dev); |
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atmel_mci_t *mci = plat->mci; |
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#else |
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static int |
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mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) |
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{ |
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struct atmel_mci_priv *priv = mmc->priv; |
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atmel_mci_t *mci = priv->mci; |
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#endif |
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u32 cmdr; |
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u32 error_flags = 0; |
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u32 status; |
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|
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if (!priv->initialized) { |
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puts ("MCI not initialized!\n"); |
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return -ECOMM; |
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} |
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|
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/* Figure out the transfer arguments */ |
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cmdr = mci_encode_cmd(cmd, data, &error_flags); |
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|
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mci_set_blklen(mci, data->blocksize); |
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|
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/* For multi blocks read/write, set the block register */ |
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if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) |
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|| (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) |
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writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize), |
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&mci->blkr); |
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|
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/* Send the command */ |
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writel(cmd->cmdarg, &mci->argr); |
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writel(cmdr, &mci->cmdr); |
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|
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#ifdef DEBUG |
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dump_cmd(cmdr, cmd->cmdarg, 0, "DEBUG"); |
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#endif |
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|
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/* Wait for the command to complete */ |
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while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY))); |
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|
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if ((status & error_flags) & MMCI_BIT(RTOE)) { |
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dump_cmd(cmdr, cmd->cmdarg, status, "Command Time Out"); |
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return -ETIMEDOUT; |
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} else if (status & error_flags) { |
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dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed"); |
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return -ECOMM; |
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} |
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|
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/* Copy the response to the response buffer */ |
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if (cmd->resp_type & MMC_RSP_136) { |
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cmd->response[0] = readl(&mci->rspr); |
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cmd->response[1] = readl(&mci->rspr1); |
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cmd->response[2] = readl(&mci->rspr2); |
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cmd->response[3] = readl(&mci->rspr3); |
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} else |
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cmd->response[0] = readl(&mci->rspr); |
|
|
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/* transfer all of the blocks */ |
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if (data) { |
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u32 word_count, block_count; |
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u32* ioptr; |
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u32 i; |
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u32 (*mci_data_op) |
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(atmel_mci_t *mci, u32* data, u32 error_flags); |
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|
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if (data->flags & MMC_DATA_READ) { |
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mci_data_op = mci_data_read; |
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ioptr = (u32*)data->dest; |
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} else { |
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mci_data_op = mci_data_write; |
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ioptr = (u32*)data->src; |
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} |
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|
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status = 0; |
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for (block_count = 0; |
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block_count < data->blocks && !status; |
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block_count++) { |
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word_count = 0; |
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do { |
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status = mci_data_op(mci, ioptr, error_flags); |
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word_count++; |
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ioptr++; |
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} while (!status && word_count < (data->blocksize/4)); |
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#ifdef DEBUG |
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if (data->flags & MMC_DATA_READ) |
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{ |
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u32 cnt = word_count * 4; |
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printf("Read Data:\n"); |
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print_buffer(0, data->dest + cnt * block_count, |
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1, cnt, 0); |
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} |
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#endif |
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if (status) { |
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dump_cmd(cmdr, cmd->cmdarg, status, |
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"Data Transfer Failed"); |
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return -ECOMM; |
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} |
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} |
|
|
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/* Wait for Transfer End */ |
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i = 0; |
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do { |
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status = readl(&mci->sr); |
|
|
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if (status & error_flags) { |
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dump_cmd(cmdr, cmd->cmdarg, status, |
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"DTIP Wait Failed"); |
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return -ECOMM; |
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} |
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i++; |
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} while ((status & MMCI_BIT(DTIP)) && i < 10000); |
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if (status & MMCI_BIT(DTIP)) { |
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dump_cmd(cmdr, cmd->cmdarg, status, |
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"XFER DTIP never unset, ignoring"); |
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} |
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} |
|
|
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/* |
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* After the switch command, wait for 8 clocks before the next |
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* command |
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*/ |
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if (cmd->cmdidx == MMC_CMD_SWITCH) |
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udelay(8*1000000 / priv->curr_clk); /* 8 clk in us */ |
|
|
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return 0; |
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} |
|
|
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#ifdef CONFIG_DM_MMC |
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static int atmel_mci_set_ios(struct udevice *dev) |
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{ |
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struct atmel_mci_plat *plat = dev_get_platdata(dev); |
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struct mmc *mmc = mmc_get_mmc_dev(dev); |
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atmel_mci_t *mci = plat->mci; |
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#else |
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/* Entered into mmc structure during driver init */ |
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static int mci_set_ios(struct mmc *mmc) |
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{ |
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struct atmel_mci_priv *priv = mmc->priv; |
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atmel_mci_t *mci = priv->mci; |
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#endif |
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int bus_width = mmc->bus_width; |
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unsigned int version = atmel_mci_get_version(mci); |
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int busw; |
|
|
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/* Set the clock speed */ |
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#ifdef CONFIG_DM_MMC |
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mci_set_mode(dev, mmc->clock, MMC_DEFAULT_BLKLEN); |
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#else |
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mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN); |
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#endif |
|
|
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/* |
|
* set the bus width and select slot for this interface |
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* there is no capability for multiple slots on the same interface yet |
|
*/ |
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if ((version & 0xf00) >= 0x300) { |
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switch (bus_width) { |
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case 8: |
|
busw = 3; |
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break; |
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case 4: |
|
busw = 2; |
|
break; |
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default: |
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busw = 0; |
|
break; |
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} |
|
|
|
writel(busw << 6 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); |
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} else { |
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busw = (bus_width == 4) ? 1 : 0; |
|
|
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writel(busw << 7 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); |
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} |
|
|
|
return 0; |
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} |
|
|
|
#ifdef CONFIG_DM_MMC |
|
static int atmel_mci_hw_init(struct udevice *dev) |
|
{ |
|
struct atmel_mci_plat *plat = dev_get_platdata(dev); |
|
atmel_mci_t *mci = plat->mci; |
|
#else |
|
/* Entered into mmc structure during driver init */ |
|
static int mci_init(struct mmc *mmc) |
|
{ |
|
struct atmel_mci_priv *priv = mmc->priv; |
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atmel_mci_t *mci = priv->mci; |
|
#endif |
|
|
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/* Initialize controller */ |
|
writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */ |
|
writel(MMCI_BIT(PWSDIS), &mci->cr); /* disable power save */ |
|
writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */ |
|
writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */ |
|
|
|
/* This delay can be optimized, but stick with max value */ |
|
writel(0x7f, &mci->dtor); |
|
/* Disable Interrupts */ |
|
writel(~0UL, &mci->idr); |
|
|
|
/* Set default clocks and blocklen */ |
|
#ifdef CONFIG_DM_MMC |
|
mci_set_mode(dev, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); |
|
#else |
|
mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); |
|
#endif |
|
|
|
return 0; |
|
} |
|
|
|
#ifndef CONFIG_DM_MMC |
|
static const struct mmc_ops atmel_mci_ops = { |
|
.send_cmd = mci_send_cmd, |
|
.set_ios = mci_set_ios, |
|
.init = mci_init, |
|
}; |
|
|
|
/* |
|
* This is the only exported function |
|
* |
|
* Call it with the MCI register base address |
|
*/ |
|
int atmel_mci_init(void *regs) |
|
{ |
|
struct mmc *mmc; |
|
struct mmc_config *cfg; |
|
struct atmel_mci_priv *priv; |
|
unsigned int version; |
|
|
|
priv = calloc(1, sizeof(*priv)); |
|
if (!priv) |
|
return -ENOMEM; |
|
|
|
cfg = &priv->cfg; |
|
|
|
cfg->name = "mci"; |
|
cfg->ops = &atmel_mci_ops; |
|
|
|
priv->mci = (struct atmel_mci *)regs; |
|
priv->initialized = 0; |
|
|
|
/* need to be able to pass these in on a board by board basis */ |
|
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
|
version = atmel_mci_get_version(priv->mci); |
|
if ((version & 0xf00) >= 0x300) { |
|
cfg->host_caps = MMC_MODE_8BIT; |
|
cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; |
|
} |
|
|
|
cfg->host_caps |= MMC_MODE_4BIT; |
|
|
|
/* |
|
* min and max frequencies determined by |
|
* max and min of clock divider |
|
*/ |
|
cfg->f_min = get_mci_clk_rate() / (2*256); |
|
cfg->f_max = get_mci_clk_rate() / (2*1); |
|
|
|
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
|
|
|
mmc = mmc_create(cfg, priv); |
|
|
|
if (mmc == NULL) { |
|
free(priv); |
|
return -ENODEV; |
|
} |
|
/* NOTE: possibly leaking the priv structure */ |
|
|
|
return 0; |
|
} |
|
#endif |
|
|
|
#ifdef CONFIG_DM_MMC |
|
static const struct dm_mmc_ops atmel_mci_mmc_ops = { |
|
.send_cmd = atmel_mci_send_cmd, |
|
.set_ios = atmel_mci_set_ios, |
|
}; |
|
|
|
static void atmel_mci_setup_cfg(struct udevice *dev) |
|
{ |
|
struct atmel_mci_plat *plat = dev_get_platdata(dev); |
|
struct atmel_mci_priv *priv = dev_get_priv(dev); |
|
struct mmc_config *cfg; |
|
u32 version; |
|
|
|
cfg = &plat->cfg; |
|
cfg->name = "Atmel mci"; |
|
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
|
|
|
/* |
|
* If the version is above 3.0, the capabilities of the 8-bit |
|
* bus width and high speed are supported. |
|
*/ |
|
version = atmel_mci_get_version(plat->mci); |
|
if ((version & 0xf00) >= 0x300) { |
|
cfg->host_caps = MMC_MODE_8BIT | |
|
MMC_MODE_HS | MMC_MODE_HS_52MHz; |
|
} |
|
|
|
cfg->host_caps |= MMC_MODE_4BIT; |
|
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
|
cfg->f_min = priv->bus_clk_rate / (2 * 256); |
|
cfg->f_max = priv->bus_clk_rate / 2; |
|
} |
|
|
|
static int atmel_mci_enable_clk(struct udevice *dev) |
|
{ |
|
struct atmel_mci_priv *priv = dev_get_priv(dev); |
|
struct clk clk; |
|
ulong clk_rate; |
|
int ret = 0; |
|
|
|
ret = clk_get_by_index(dev, 0, &clk); |
|
if (ret) { |
|
ret = -EINVAL; |
|
goto failed; |
|
} |
|
|
|
ret = clk_enable(&clk); |
|
if (ret) |
|
goto failed; |
|
|
|
clk_rate = clk_get_rate(&clk); |
|
if (!clk_rate) { |
|
ret = -EINVAL; |
|
goto failed; |
|
} |
|
|
|
priv->bus_clk_rate = clk_rate; |
|
|
|
failed: |
|
clk_free(&clk); |
|
|
|
return ret; |
|
} |
|
|
|
static int atmel_mci_probe(struct udevice *dev) |
|
{ |
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
|
struct atmel_mci_plat *plat = dev_get_platdata(dev); |
|
struct mmc *mmc; |
|
int ret; |
|
|
|
ret = atmel_mci_enable_clk(dev); |
|
if (ret) |
|
return ret; |
|
|
|
plat->mci = (struct atmel_mci *)devfdt_get_addr_ptr(dev); |
|
|
|
atmel_mci_setup_cfg(dev); |
|
|
|
mmc = &plat->mmc; |
|
mmc->cfg = &plat->cfg; |
|
mmc->dev = dev; |
|
upriv->mmc = mmc; |
|
|
|
atmel_mci_hw_init(dev); |
|
|
|
return 0; |
|
} |
|
|
|
static int atmel_mci_bind(struct udevice *dev) |
|
{ |
|
struct atmel_mci_plat *plat = dev_get_platdata(dev); |
|
|
|
return mmc_bind(dev, &plat->mmc, &plat->cfg); |
|
} |
|
|
|
static const struct udevice_id atmel_mci_ids[] = { |
|
{ .compatible = "atmel,hsmci" }, |
|
{ } |
|
}; |
|
|
|
U_BOOT_DRIVER(atmel_mci) = { |
|
.name = "atmel-mci", |
|
.id = UCLASS_MMC, |
|
.of_match = atmel_mci_ids, |
|
.bind = atmel_mci_bind, |
|
.probe = atmel_mci_probe, |
|
.platdata_auto_alloc_size = sizeof(struct atmel_mci_plat), |
|
.priv_auto_alloc_size = sizeof(struct atmel_mci_priv), |
|
.ops = &atmel_mci_mmc_ops, |
|
}; |
|
#endif
|
|
|