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31 lines
961 B
31 lines
961 B
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Definitions for CS4271 ASoC codec driver |
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* |
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* Copyright (c) 2010 Alexander Sverdlin <[email protected]> |
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*/ |
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#ifndef __CS4271_H |
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#define __CS4271_H |
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struct cs4271_platform_data { |
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int gpio_nreset; /* GPIO driving Reset pin, if any */ |
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bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */ |
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/* |
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* The CS4271 requires its LRCLK and MCLK to be stable before its RESET |
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* line is de-asserted. That also means that clocks cannot be changed |
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* without putting the chip back into hardware reset, which also requires |
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* a complete re-initialization of all registers. |
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* |
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* One (undocumented) workaround is to assert and de-assert the PDN bit |
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* in the MODE2 register. This workaround can be enabled with the |
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* following flag. |
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* |
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* Note that this is not needed in case the clocks are stable |
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* throughout the entire runtime of the codec. |
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*/ |
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bool enable_soft_reset; |
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}; |
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#endif /* __CS4271_H */
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