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965 lines
24 KiB
965 lines
24 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* I2C Link Layer for PN544 HCI based Driver |
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* |
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* Copyright (C) 2012 Intel Corporation. All rights reserved. |
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*/ |
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|
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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|
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#include <linux/crc-ccitt.h> |
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#include <linux/module.h> |
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#include <linux/i2c.h> |
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#include <linux/acpi.h> |
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#include <linux/interrupt.h> |
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#include <linux/delay.h> |
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#include <linux/nfc.h> |
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#include <linux/firmware.h> |
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#include <linux/gpio/consumer.h> |
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|
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#include <asm/unaligned.h> |
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|
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#include <net/nfc/hci.h> |
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#include <net/nfc/llc.h> |
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#include <net/nfc/nfc.h> |
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|
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#include "pn544.h" |
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|
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#define PN544_I2C_FRAME_HEADROOM 1 |
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#define PN544_I2C_FRAME_TAILROOM 2 |
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|
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/* GPIO names */ |
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#define PN544_GPIO_NAME_IRQ "pn544_irq" |
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#define PN544_GPIO_NAME_FW "pn544_fw" |
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#define PN544_GPIO_NAME_EN "pn544_en" |
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|
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/* framing in HCI mode */ |
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#define PN544_HCI_I2C_LLC_LEN 1 |
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#define PN544_HCI_I2C_LLC_CRC 2 |
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#define PN544_HCI_I2C_LLC_LEN_CRC (PN544_HCI_I2C_LLC_LEN + \ |
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PN544_HCI_I2C_LLC_CRC) |
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#define PN544_HCI_I2C_LLC_MIN_SIZE (1 + PN544_HCI_I2C_LLC_LEN_CRC) |
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#define PN544_HCI_I2C_LLC_MAX_PAYLOAD 29 |
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#define PN544_HCI_I2C_LLC_MAX_SIZE (PN544_HCI_I2C_LLC_LEN_CRC + 1 + \ |
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PN544_HCI_I2C_LLC_MAX_PAYLOAD) |
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|
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static const struct i2c_device_id pn544_hci_i2c_id_table[] = { |
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{"pn544", 0}, |
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{} |
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}; |
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|
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MODULE_DEVICE_TABLE(i2c, pn544_hci_i2c_id_table); |
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|
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static const struct acpi_device_id pn544_hci_i2c_acpi_match[] __maybe_unused = { |
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{"NXP5440", 0}, |
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{} |
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}; |
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|
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MODULE_DEVICE_TABLE(acpi, pn544_hci_i2c_acpi_match); |
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|
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#define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c" |
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|
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/* |
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* Exposed through the 4 most significant bytes |
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* from the HCI SW_VERSION first byte, a.k.a. |
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* SW RomLib. |
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*/ |
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#define PN544_HW_VARIANT_C2 0xa |
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#define PN544_HW_VARIANT_C3 0xb |
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|
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#define PN544_FW_CMD_RESET 0x01 |
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#define PN544_FW_CMD_WRITE 0x08 |
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#define PN544_FW_CMD_CHECK 0x06 |
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#define PN544_FW_CMD_SECURE_WRITE 0x0C |
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#define PN544_FW_CMD_SECURE_CHUNK_WRITE 0x0D |
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|
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struct pn544_i2c_fw_frame_write { |
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u8 cmd; |
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u16 be_length; |
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u8 be_dest_addr[3]; |
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u16 be_datalen; |
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u8 data[]; |
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} __packed; |
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|
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struct pn544_i2c_fw_frame_check { |
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u8 cmd; |
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u16 be_length; |
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u8 be_start_addr[3]; |
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u16 be_datalen; |
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u16 be_crc; |
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} __packed; |
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|
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struct pn544_i2c_fw_frame_response { |
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u8 status; |
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u16 be_length; |
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} __packed; |
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|
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struct pn544_i2c_fw_blob { |
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u32 be_size; |
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u32 be_destaddr; |
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u8 data[]; |
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}; |
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|
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struct pn544_i2c_fw_secure_frame { |
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u8 cmd; |
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u16 be_datalen; |
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u8 data[]; |
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} __packed; |
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|
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struct pn544_i2c_fw_secure_blob { |
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u64 header; |
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u8 data[]; |
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}; |
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|
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#define PN544_FW_CMD_RESULT_TIMEOUT 0x01 |
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#define PN544_FW_CMD_RESULT_BAD_CRC 0x02 |
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#define PN544_FW_CMD_RESULT_ACCESS_DENIED 0x08 |
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#define PN544_FW_CMD_RESULT_PROTOCOL_ERROR 0x0B |
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#define PN544_FW_CMD_RESULT_INVALID_PARAMETER 0x11 |
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#define PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND 0x13 |
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#define PN544_FW_CMD_RESULT_INVALID_LENGTH 0x18 |
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#define PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR 0x19 |
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#define PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR 0x1D |
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#define PN544_FW_CMD_RESULT_MEMORY_ERROR 0x20 |
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#define PN544_FW_CMD_RESULT_CHUNK_OK 0x21 |
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#define PN544_FW_CMD_RESULT_WRITE_FAILED 0x74 |
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#define PN544_FW_CMD_RESULT_COMMAND_REJECTED 0xE0 |
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#define PN544_FW_CMD_RESULT_CHUNK_ERROR 0xE6 |
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|
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#define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) |
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|
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#define PN544_FW_WRITE_BUFFER_MAX_LEN 0x9f7 |
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#define PN544_FW_I2C_MAX_PAYLOAD PN544_HCI_I2C_LLC_MAX_SIZE |
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#define PN544_FW_I2C_WRITE_FRAME_HEADER_LEN 8 |
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#define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\ |
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PN544_FW_I2C_WRITE_FRAME_HEADER_LEN),\ |
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PN544_FW_WRITE_BUFFER_MAX_LEN) |
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#define PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN 3 |
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#define PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN (PN544_FW_I2C_MAX_PAYLOAD -\ |
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PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN) |
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#define PN544_FW_SECURE_FRAME_HEADER_LEN 3 |
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#define PN544_FW_SECURE_BLOB_HEADER_LEN 8 |
|
|
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#define FW_WORK_STATE_IDLE 1 |
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#define FW_WORK_STATE_START 2 |
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#define FW_WORK_STATE_WAIT_WRITE_ANSWER 3 |
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#define FW_WORK_STATE_WAIT_CHECK_ANSWER 4 |
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#define FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER 5 |
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|
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struct pn544_i2c_phy { |
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struct i2c_client *i2c_dev; |
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struct nfc_hci_dev *hdev; |
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|
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struct gpio_desc *gpiod_en; |
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struct gpio_desc *gpiod_fw; |
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|
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unsigned int en_polarity; |
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|
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u8 hw_variant; |
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struct work_struct fw_work; |
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int fw_work_state; |
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char firmware_name[NFC_FIRMWARE_NAME_MAXSIZE + 1]; |
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const struct firmware *fw; |
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u32 fw_blob_dest_addr; |
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size_t fw_blob_size; |
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const u8 *fw_blob_data; |
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size_t fw_written; |
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size_t fw_size; |
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|
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int fw_cmd_result; |
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|
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int powered; |
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int run_mode; |
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|
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int hard_fault; /* |
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* < 0 if hardware error occured (e.g. i2c err) |
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* and prevents normal operation. |
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*/ |
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}; |
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|
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#define I2C_DUMP_SKB(info, skb) \ |
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do { \ |
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pr_debug("%s:\n", info); \ |
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print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \ |
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16, 1, (skb)->data, (skb)->len, 0); \ |
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} while (0) |
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|
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static void pn544_hci_i2c_platform_init(struct pn544_i2c_phy *phy) |
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{ |
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int polarity, retry, ret; |
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static const char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 }; |
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int count = sizeof(rset_cmd); |
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nfc_info(&phy->i2c_dev->dev, "Detecting nfc_en polarity\n"); |
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|
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/* Disable fw download */ |
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gpiod_set_value_cansleep(phy->gpiod_fw, 0); |
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|
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for (polarity = 0; polarity < 2; polarity++) { |
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phy->en_polarity = polarity; |
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retry = 3; |
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while (retry--) { |
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/* power off */ |
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gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity); |
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usleep_range(10000, 15000); |
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|
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/* power on */ |
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gpiod_set_value_cansleep(phy->gpiod_en, phy->en_polarity); |
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usleep_range(10000, 15000); |
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|
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/* send reset */ |
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dev_dbg(&phy->i2c_dev->dev, "Sending reset cmd\n"); |
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ret = i2c_master_send(phy->i2c_dev, rset_cmd, count); |
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if (ret == count) { |
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nfc_info(&phy->i2c_dev->dev, |
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"nfc_en polarity : active %s\n", |
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(polarity == 0 ? "low" : "high")); |
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goto out; |
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} |
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} |
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} |
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nfc_err(&phy->i2c_dev->dev, |
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"Could not detect nfc_en polarity, fallback to active high\n"); |
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|
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out: |
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gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity); |
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usleep_range(10000, 15000); |
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} |
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static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode) |
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{ |
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gpiod_set_value_cansleep(phy->gpiod_fw, run_mode == PN544_FW_MODE ? 1 : 0); |
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gpiod_set_value_cansleep(phy->gpiod_en, phy->en_polarity); |
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usleep_range(10000, 15000); |
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|
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phy->run_mode = run_mode; |
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} |
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static int pn544_hci_i2c_enable(void *phy_id) |
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{ |
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struct pn544_i2c_phy *phy = phy_id; |
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pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE); |
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phy->powered = 1; |
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return 0; |
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} |
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static void pn544_hci_i2c_disable(void *phy_id) |
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{ |
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struct pn544_i2c_phy *phy = phy_id; |
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gpiod_set_value_cansleep(phy->gpiod_fw, 0); |
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gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity); |
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usleep_range(10000, 15000); |
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gpiod_set_value_cansleep(phy->gpiod_en, phy->en_polarity); |
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usleep_range(10000, 15000); |
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gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity); |
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usleep_range(10000, 15000); |
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phy->powered = 0; |
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} |
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static void pn544_hci_i2c_add_len_crc(struct sk_buff *skb) |
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{ |
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u16 crc; |
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int len; |
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len = skb->len + 2; |
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*(u8 *)skb_push(skb, 1) = len; |
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crc = crc_ccitt(0xffff, skb->data, skb->len); |
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crc = ~crc; |
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skb_put_u8(skb, crc & 0xff); |
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skb_put_u8(skb, crc >> 8); |
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} |
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static void pn544_hci_i2c_remove_len_crc(struct sk_buff *skb) |
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{ |
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skb_pull(skb, PN544_I2C_FRAME_HEADROOM); |
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skb_trim(skb, PN544_I2C_FRAME_TAILROOM); |
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} |
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|
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/* |
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* Writing a frame must not return the number of written bytes. |
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* It must return either zero for success, or <0 for error. |
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* In addition, it must not alter the skb |
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*/ |
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static int pn544_hci_i2c_write(void *phy_id, struct sk_buff *skb) |
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{ |
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int r; |
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struct pn544_i2c_phy *phy = phy_id; |
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struct i2c_client *client = phy->i2c_dev; |
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|
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if (phy->hard_fault != 0) |
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return phy->hard_fault; |
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usleep_range(3000, 6000); |
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pn544_hci_i2c_add_len_crc(skb); |
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I2C_DUMP_SKB("i2c frame written", skb); |
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r = i2c_master_send(client, skb->data, skb->len); |
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|
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if (r == -EREMOTEIO) { /* Retry, chip was in standby */ |
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usleep_range(6000, 10000); |
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r = i2c_master_send(client, skb->data, skb->len); |
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} |
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|
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if (r >= 0) { |
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if (r != skb->len) |
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r = -EREMOTEIO; |
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else |
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r = 0; |
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} |
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|
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pn544_hci_i2c_remove_len_crc(skb); |
|
|
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return r; |
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} |
|
|
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static int check_crc(u8 *buf, int buflen) |
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{ |
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int len; |
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u16 crc; |
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|
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len = buf[0] + 1; |
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crc = crc_ccitt(0xffff, buf, len - 2); |
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crc = ~crc; |
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|
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if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) { |
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pr_err("CRC error 0x%x != 0x%x 0x%x\n", |
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crc, buf[len - 1], buf[len - 2]); |
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pr_info("%s: BAD CRC\n", __func__); |
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print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE, |
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16, 2, buf, buflen, false); |
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return -EPERM; |
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} |
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return 0; |
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} |
|
|
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/* |
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* Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees |
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* that i2c bus will be flushed and that next read will start on a new frame. |
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* returned skb contains only LLC header and payload. |
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* returns: |
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* -EREMOTEIO : i2c read error (fatal) |
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* -EBADMSG : frame was incorrect and discarded |
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* -ENOMEM : cannot allocate skb, frame dropped |
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*/ |
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static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb) |
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{ |
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int r; |
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u8 len; |
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u8 tmp[PN544_HCI_I2C_LLC_MAX_SIZE - 1]; |
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struct i2c_client *client = phy->i2c_dev; |
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|
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r = i2c_master_recv(client, &len, 1); |
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if (r != 1) { |
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nfc_err(&client->dev, "cannot read len byte\n"); |
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return -EREMOTEIO; |
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} |
|
|
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if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) || |
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(len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) { |
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nfc_err(&client->dev, "invalid len byte\n"); |
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r = -EBADMSG; |
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goto flush; |
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} |
|
|
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*skb = alloc_skb(1 + len, GFP_KERNEL); |
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if (*skb == NULL) { |
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r = -ENOMEM; |
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goto flush; |
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} |
|
|
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skb_put_u8(*skb, len); |
|
|
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r = i2c_master_recv(client, skb_put(*skb, len), len); |
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if (r != len) { |
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kfree_skb(*skb); |
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return -EREMOTEIO; |
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} |
|
|
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I2C_DUMP_SKB("i2c frame read", *skb); |
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|
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r = check_crc((*skb)->data, (*skb)->len); |
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if (r != 0) { |
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kfree_skb(*skb); |
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r = -EBADMSG; |
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goto flush; |
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} |
|
|
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skb_pull(*skb, 1); |
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skb_trim(*skb, (*skb)->len - 2); |
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|
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usleep_range(3000, 6000); |
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|
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return 0; |
|
|
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flush: |
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if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0) |
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r = -EREMOTEIO; |
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|
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usleep_range(3000, 6000); |
|
|
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return r; |
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} |
|
|
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static int pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy *phy) |
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{ |
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int r; |
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struct pn544_i2c_fw_frame_response response; |
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struct i2c_client *client = phy->i2c_dev; |
|
|
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r = i2c_master_recv(client, (char *) &response, sizeof(response)); |
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if (r != sizeof(response)) { |
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nfc_err(&client->dev, "cannot read fw status\n"); |
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return -EIO; |
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} |
|
|
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usleep_range(3000, 6000); |
|
|
|
switch (response.status) { |
|
case 0: |
|
return 0; |
|
case PN544_FW_CMD_RESULT_CHUNK_OK: |
|
return response.status; |
|
case PN544_FW_CMD_RESULT_TIMEOUT: |
|
return -ETIMEDOUT; |
|
case PN544_FW_CMD_RESULT_BAD_CRC: |
|
return -ENODATA; |
|
case PN544_FW_CMD_RESULT_ACCESS_DENIED: |
|
return -EACCES; |
|
case PN544_FW_CMD_RESULT_PROTOCOL_ERROR: |
|
return -EPROTO; |
|
case PN544_FW_CMD_RESULT_INVALID_PARAMETER: |
|
return -EINVAL; |
|
case PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND: |
|
return -ENOTSUPP; |
|
case PN544_FW_CMD_RESULT_INVALID_LENGTH: |
|
return -EBADMSG; |
|
case PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR: |
|
return -ENOKEY; |
|
case PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR: |
|
return -EINVAL; |
|
case PN544_FW_CMD_RESULT_MEMORY_ERROR: |
|
return -ENOMEM; |
|
case PN544_FW_CMD_RESULT_COMMAND_REJECTED: |
|
return -EACCES; |
|
case PN544_FW_CMD_RESULT_WRITE_FAILED: |
|
case PN544_FW_CMD_RESULT_CHUNK_ERROR: |
|
return -EIO; |
|
default: |
|
return -EIO; |
|
} |
|
} |
|
|
|
/* |
|
* Reads an shdlc frame from the chip. This is not as straightforward as it |
|
* seems. There are cases where we could loose the frame start synchronization. |
|
* The frame format is len-data-crc, and corruption can occur anywhere while |
|
* transiting on i2c bus, such that we could read an invalid len. |
|
* In order to recover synchronization with the next frame, we must be sure |
|
* to read the real amount of data without using the len byte. We do this by |
|
* assuming the following: |
|
* - the chip will always present only one single complete frame on the bus |
|
* before triggering the interrupt |
|
* - the chip will not present a new frame until we have completely read |
|
* the previous one (or until we have handled the interrupt). |
|
* The tricky case is when we read a corrupted len that is less than the real |
|
* len. We must detect this here in order to determine that we need to flush |
|
* the bus. This is the reason why we check the crc here. |
|
*/ |
|
static irqreturn_t pn544_hci_i2c_irq_thread_fn(int irq, void *phy_id) |
|
{ |
|
struct pn544_i2c_phy *phy = phy_id; |
|
struct i2c_client *client; |
|
struct sk_buff *skb = NULL; |
|
int r; |
|
|
|
if (!phy || irq != phy->i2c_dev->irq) { |
|
WARN_ON_ONCE(1); |
|
return IRQ_NONE; |
|
} |
|
|
|
client = phy->i2c_dev; |
|
dev_dbg(&client->dev, "IRQ\n"); |
|
|
|
if (phy->hard_fault != 0) |
|
return IRQ_HANDLED; |
|
|
|
if (phy->run_mode == PN544_FW_MODE) { |
|
phy->fw_cmd_result = pn544_hci_i2c_fw_read_status(phy); |
|
schedule_work(&phy->fw_work); |
|
} else { |
|
r = pn544_hci_i2c_read(phy, &skb); |
|
if (r == -EREMOTEIO) { |
|
phy->hard_fault = r; |
|
|
|
nfc_hci_recv_frame(phy->hdev, NULL); |
|
|
|
return IRQ_HANDLED; |
|
} else if ((r == -ENOMEM) || (r == -EBADMSG)) { |
|
return IRQ_HANDLED; |
|
} |
|
|
|
nfc_hci_recv_frame(phy->hdev, skb); |
|
} |
|
return IRQ_HANDLED; |
|
} |
|
|
|
static const struct nfc_phy_ops i2c_phy_ops = { |
|
.write = pn544_hci_i2c_write, |
|
.enable = pn544_hci_i2c_enable, |
|
.disable = pn544_hci_i2c_disable, |
|
}; |
|
|
|
static int pn544_hci_i2c_fw_download(void *phy_id, const char *firmware_name, |
|
u8 hw_variant) |
|
{ |
|
struct pn544_i2c_phy *phy = phy_id; |
|
|
|
pr_info("Starting Firmware Download (%s)\n", firmware_name); |
|
|
|
strcpy(phy->firmware_name, firmware_name); |
|
|
|
phy->hw_variant = hw_variant; |
|
phy->fw_work_state = FW_WORK_STATE_START; |
|
|
|
schedule_work(&phy->fw_work); |
|
|
|
return 0; |
|
} |
|
|
|
static void pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy *phy, |
|
int result) |
|
{ |
|
pr_info("Firmware Download Complete, result=%d\n", result); |
|
|
|
pn544_hci_i2c_disable(phy); |
|
|
|
phy->fw_work_state = FW_WORK_STATE_IDLE; |
|
|
|
if (phy->fw) { |
|
release_firmware(phy->fw); |
|
phy->fw = NULL; |
|
} |
|
|
|
nfc_fw_download_done(phy->hdev->ndev, phy->firmware_name, (u32) -result); |
|
} |
|
|
|
static int pn544_hci_i2c_fw_write_cmd(struct i2c_client *client, u32 dest_addr, |
|
const u8 *data, u16 datalen) |
|
{ |
|
u8 frame[PN544_FW_I2C_MAX_PAYLOAD]; |
|
struct pn544_i2c_fw_frame_write *framep; |
|
u16 params_len; |
|
int framelen; |
|
int r; |
|
|
|
if (datalen > PN544_FW_I2C_WRITE_DATA_MAX_LEN) |
|
datalen = PN544_FW_I2C_WRITE_DATA_MAX_LEN; |
|
|
|
framep = (struct pn544_i2c_fw_frame_write *) frame; |
|
|
|
params_len = sizeof(framep->be_dest_addr) + |
|
sizeof(framep->be_datalen) + datalen; |
|
framelen = params_len + sizeof(framep->cmd) + |
|
sizeof(framep->be_length); |
|
|
|
framep->cmd = PN544_FW_CMD_WRITE; |
|
|
|
put_unaligned_be16(params_len, &framep->be_length); |
|
|
|
framep->be_dest_addr[0] = (dest_addr & 0xff0000) >> 16; |
|
framep->be_dest_addr[1] = (dest_addr & 0xff00) >> 8; |
|
framep->be_dest_addr[2] = dest_addr & 0xff; |
|
|
|
put_unaligned_be16(datalen, &framep->be_datalen); |
|
|
|
memcpy(framep->data, data, datalen); |
|
|
|
r = i2c_master_send(client, frame, framelen); |
|
|
|
if (r == framelen) |
|
return datalen; |
|
else if (r < 0) |
|
return r; |
|
else |
|
return -EIO; |
|
} |
|
|
|
static int pn544_hci_i2c_fw_check_cmd(struct i2c_client *client, u32 start_addr, |
|
const u8 *data, u16 datalen) |
|
{ |
|
struct pn544_i2c_fw_frame_check frame; |
|
int r; |
|
u16 crc; |
|
|
|
/* calculate local crc for the data we want to check */ |
|
crc = crc_ccitt(0xffff, data, datalen); |
|
|
|
frame.cmd = PN544_FW_CMD_CHECK; |
|
|
|
put_unaligned_be16(sizeof(frame.be_start_addr) + |
|
sizeof(frame.be_datalen) + sizeof(frame.be_crc), |
|
&frame.be_length); |
|
|
|
/* tell the chip the memory region to which our crc applies */ |
|
frame.be_start_addr[0] = (start_addr & 0xff0000) >> 16; |
|
frame.be_start_addr[1] = (start_addr & 0xff00) >> 8; |
|
frame.be_start_addr[2] = start_addr & 0xff; |
|
|
|
put_unaligned_be16(datalen, &frame.be_datalen); |
|
|
|
/* |
|
* and give our local crc. Chip will calculate its own crc for the |
|
* region and compare with ours. |
|
*/ |
|
put_unaligned_be16(crc, &frame.be_crc); |
|
|
|
r = i2c_master_send(client, (const char *) &frame, sizeof(frame)); |
|
|
|
if (r == sizeof(frame)) |
|
return 0; |
|
else if (r < 0) |
|
return r; |
|
else |
|
return -EIO; |
|
} |
|
|
|
static int pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy *phy) |
|
{ |
|
int r; |
|
|
|
r = pn544_hci_i2c_fw_write_cmd(phy->i2c_dev, |
|
phy->fw_blob_dest_addr + phy->fw_written, |
|
phy->fw_blob_data + phy->fw_written, |
|
phy->fw_blob_size - phy->fw_written); |
|
if (r < 0) |
|
return r; |
|
|
|
phy->fw_written += r; |
|
phy->fw_work_state = FW_WORK_STATE_WAIT_WRITE_ANSWER; |
|
|
|
return 0; |
|
} |
|
|
|
static int pn544_hci_i2c_fw_secure_write_frame_cmd(struct pn544_i2c_phy *phy, |
|
const u8 *data, u16 datalen) |
|
{ |
|
u8 buf[PN544_FW_I2C_MAX_PAYLOAD]; |
|
struct pn544_i2c_fw_secure_frame *chunk; |
|
int chunklen; |
|
int r; |
|
|
|
if (datalen > PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN) |
|
datalen = PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN; |
|
|
|
chunk = (struct pn544_i2c_fw_secure_frame *) buf; |
|
|
|
chunk->cmd = PN544_FW_CMD_SECURE_CHUNK_WRITE; |
|
|
|
put_unaligned_be16(datalen, &chunk->be_datalen); |
|
|
|
memcpy(chunk->data, data, datalen); |
|
|
|
chunklen = sizeof(chunk->cmd) + sizeof(chunk->be_datalen) + datalen; |
|
|
|
r = i2c_master_send(phy->i2c_dev, buf, chunklen); |
|
|
|
if (r == chunklen) |
|
return datalen; |
|
else if (r < 0) |
|
return r; |
|
else |
|
return -EIO; |
|
|
|
} |
|
|
|
static int pn544_hci_i2c_fw_secure_write_frame(struct pn544_i2c_phy *phy) |
|
{ |
|
struct pn544_i2c_fw_secure_frame *framep; |
|
int r; |
|
|
|
framep = (struct pn544_i2c_fw_secure_frame *) phy->fw_blob_data; |
|
if (phy->fw_written == 0) |
|
phy->fw_blob_size = get_unaligned_be16(&framep->be_datalen) |
|
+ PN544_FW_SECURE_FRAME_HEADER_LEN; |
|
|
|
/* Only secure write command can be chunked*/ |
|
if (phy->fw_blob_size > PN544_FW_I2C_MAX_PAYLOAD && |
|
framep->cmd != PN544_FW_CMD_SECURE_WRITE) |
|
return -EINVAL; |
|
|
|
/* The firmware also have other commands, we just send them directly */ |
|
if (phy->fw_blob_size < PN544_FW_I2C_MAX_PAYLOAD) { |
|
r = i2c_master_send(phy->i2c_dev, |
|
(const char *) phy->fw_blob_data, phy->fw_blob_size); |
|
|
|
if (r == phy->fw_blob_size) |
|
goto exit; |
|
else if (r < 0) |
|
return r; |
|
else |
|
return -EIO; |
|
} |
|
|
|
r = pn544_hci_i2c_fw_secure_write_frame_cmd(phy, |
|
phy->fw_blob_data + phy->fw_written, |
|
phy->fw_blob_size - phy->fw_written); |
|
if (r < 0) |
|
return r; |
|
|
|
exit: |
|
phy->fw_written += r; |
|
phy->fw_work_state = FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER; |
|
|
|
/* SW reset command will not trig any response from PN544 */ |
|
if (framep->cmd == PN544_FW_CMD_RESET) { |
|
pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE); |
|
phy->fw_cmd_result = 0; |
|
schedule_work(&phy->fw_work); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static void pn544_hci_i2c_fw_work(struct work_struct *work) |
|
{ |
|
struct pn544_i2c_phy *phy = container_of(work, struct pn544_i2c_phy, |
|
fw_work); |
|
int r; |
|
struct pn544_i2c_fw_blob *blob; |
|
struct pn544_i2c_fw_secure_blob *secure_blob; |
|
|
|
switch (phy->fw_work_state) { |
|
case FW_WORK_STATE_START: |
|
pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE); |
|
|
|
r = request_firmware(&phy->fw, phy->firmware_name, |
|
&phy->i2c_dev->dev); |
|
if (r < 0) |
|
goto exit_state_start; |
|
|
|
phy->fw_written = 0; |
|
|
|
switch (phy->hw_variant) { |
|
case PN544_HW_VARIANT_C2: |
|
blob = (struct pn544_i2c_fw_blob *) phy->fw->data; |
|
phy->fw_blob_size = get_unaligned_be32(&blob->be_size); |
|
phy->fw_blob_dest_addr = get_unaligned_be32( |
|
&blob->be_destaddr); |
|
phy->fw_blob_data = blob->data; |
|
|
|
r = pn544_hci_i2c_fw_write_chunk(phy); |
|
break; |
|
case PN544_HW_VARIANT_C3: |
|
secure_blob = (struct pn544_i2c_fw_secure_blob *) |
|
phy->fw->data; |
|
phy->fw_blob_data = secure_blob->data; |
|
phy->fw_size = phy->fw->size; |
|
r = pn544_hci_i2c_fw_secure_write_frame(phy); |
|
break; |
|
default: |
|
r = -ENOTSUPP; |
|
break; |
|
} |
|
|
|
exit_state_start: |
|
if (r < 0) |
|
pn544_hci_i2c_fw_work_complete(phy, r); |
|
break; |
|
|
|
case FW_WORK_STATE_WAIT_WRITE_ANSWER: |
|
r = phy->fw_cmd_result; |
|
if (r < 0) |
|
goto exit_state_wait_write_answer; |
|
|
|
if (phy->fw_written == phy->fw_blob_size) { |
|
r = pn544_hci_i2c_fw_check_cmd(phy->i2c_dev, |
|
phy->fw_blob_dest_addr, |
|
phy->fw_blob_data, |
|
phy->fw_blob_size); |
|
if (r < 0) |
|
goto exit_state_wait_write_answer; |
|
phy->fw_work_state = FW_WORK_STATE_WAIT_CHECK_ANSWER; |
|
break; |
|
} |
|
|
|
r = pn544_hci_i2c_fw_write_chunk(phy); |
|
|
|
exit_state_wait_write_answer: |
|
if (r < 0) |
|
pn544_hci_i2c_fw_work_complete(phy, r); |
|
break; |
|
|
|
case FW_WORK_STATE_WAIT_CHECK_ANSWER: |
|
r = phy->fw_cmd_result; |
|
if (r < 0) |
|
goto exit_state_wait_check_answer; |
|
|
|
blob = (struct pn544_i2c_fw_blob *) (phy->fw_blob_data + |
|
phy->fw_blob_size); |
|
phy->fw_blob_size = get_unaligned_be32(&blob->be_size); |
|
if (phy->fw_blob_size != 0) { |
|
phy->fw_blob_dest_addr = |
|
get_unaligned_be32(&blob->be_destaddr); |
|
phy->fw_blob_data = blob->data; |
|
|
|
phy->fw_written = 0; |
|
r = pn544_hci_i2c_fw_write_chunk(phy); |
|
} |
|
|
|
exit_state_wait_check_answer: |
|
if (r < 0 || phy->fw_blob_size == 0) |
|
pn544_hci_i2c_fw_work_complete(phy, r); |
|
break; |
|
|
|
case FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER: |
|
r = phy->fw_cmd_result; |
|
if (r < 0) |
|
goto exit_state_wait_secure_write_answer; |
|
|
|
if (r == PN544_FW_CMD_RESULT_CHUNK_OK) { |
|
r = pn544_hci_i2c_fw_secure_write_frame(phy); |
|
goto exit_state_wait_secure_write_answer; |
|
} |
|
|
|
if (phy->fw_written == phy->fw_blob_size) { |
|
secure_blob = (struct pn544_i2c_fw_secure_blob *) |
|
(phy->fw_blob_data + phy->fw_blob_size); |
|
phy->fw_size -= phy->fw_blob_size + |
|
PN544_FW_SECURE_BLOB_HEADER_LEN; |
|
if (phy->fw_size >= PN544_FW_SECURE_BLOB_HEADER_LEN |
|
+ PN544_FW_SECURE_FRAME_HEADER_LEN) { |
|
phy->fw_blob_data = secure_blob->data; |
|
|
|
phy->fw_written = 0; |
|
r = pn544_hci_i2c_fw_secure_write_frame(phy); |
|
} |
|
} |
|
|
|
exit_state_wait_secure_write_answer: |
|
if (r < 0 || phy->fw_size == 0) |
|
pn544_hci_i2c_fw_work_complete(phy, r); |
|
break; |
|
|
|
default: |
|
break; |
|
} |
|
} |
|
|
|
static const struct acpi_gpio_params enable_gpios = { 1, 0, false }; |
|
static const struct acpi_gpio_params firmware_gpios = { 2, 0, false }; |
|
|
|
static const struct acpi_gpio_mapping acpi_pn544_gpios[] = { |
|
{ "enable-gpios", &enable_gpios, 1 }, |
|
{ "firmware-gpios", &firmware_gpios, 1 }, |
|
{ }, |
|
}; |
|
|
|
static int pn544_hci_i2c_probe(struct i2c_client *client, |
|
const struct i2c_device_id *id) |
|
{ |
|
struct device *dev = &client->dev; |
|
struct pn544_i2c_phy *phy; |
|
int r = 0; |
|
|
|
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { |
|
nfc_err(&client->dev, "Need I2C_FUNC_I2C\n"); |
|
return -ENODEV; |
|
} |
|
|
|
phy = devm_kzalloc(&client->dev, sizeof(struct pn544_i2c_phy), |
|
GFP_KERNEL); |
|
if (!phy) |
|
return -ENOMEM; |
|
|
|
INIT_WORK(&phy->fw_work, pn544_hci_i2c_fw_work); |
|
phy->fw_work_state = FW_WORK_STATE_IDLE; |
|
|
|
phy->i2c_dev = client; |
|
i2c_set_clientdata(client, phy); |
|
|
|
r = devm_acpi_dev_add_driver_gpios(dev, acpi_pn544_gpios); |
|
if (r) |
|
dev_dbg(dev, "Unable to add GPIO mapping table\n"); |
|
|
|
/* Get EN GPIO */ |
|
phy->gpiod_en = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); |
|
if (IS_ERR(phy->gpiod_en)) { |
|
nfc_err(dev, "Unable to get EN GPIO\n"); |
|
return PTR_ERR(phy->gpiod_en); |
|
} |
|
|
|
/* Get FW GPIO */ |
|
phy->gpiod_fw = devm_gpiod_get(dev, "firmware", GPIOD_OUT_LOW); |
|
if (IS_ERR(phy->gpiod_fw)) { |
|
nfc_err(dev, "Unable to get FW GPIO\n"); |
|
return PTR_ERR(phy->gpiod_fw); |
|
} |
|
|
|
pn544_hci_i2c_platform_init(phy); |
|
|
|
r = devm_request_threaded_irq(&client->dev, client->irq, NULL, |
|
pn544_hci_i2c_irq_thread_fn, |
|
IRQF_TRIGGER_RISING | IRQF_ONESHOT, |
|
PN544_HCI_I2C_DRIVER_NAME, phy); |
|
if (r < 0) { |
|
nfc_err(&client->dev, "Unable to register IRQ handler\n"); |
|
return r; |
|
} |
|
|
|
r = pn544_hci_probe(phy, &i2c_phy_ops, LLC_SHDLC_NAME, |
|
PN544_I2C_FRAME_HEADROOM, PN544_I2C_FRAME_TAILROOM, |
|
PN544_HCI_I2C_LLC_MAX_PAYLOAD, |
|
pn544_hci_i2c_fw_download, &phy->hdev); |
|
if (r < 0) |
|
return r; |
|
|
|
return 0; |
|
} |
|
|
|
static void pn544_hci_i2c_remove(struct i2c_client *client) |
|
{ |
|
struct pn544_i2c_phy *phy = i2c_get_clientdata(client); |
|
|
|
cancel_work_sync(&phy->fw_work); |
|
if (phy->fw_work_state != FW_WORK_STATE_IDLE) |
|
pn544_hci_i2c_fw_work_complete(phy, -ENODEV); |
|
|
|
pn544_hci_remove(phy->hdev); |
|
|
|
if (phy->powered) |
|
pn544_hci_i2c_disable(phy); |
|
} |
|
|
|
static const struct of_device_id of_pn544_i2c_match[] __maybe_unused = { |
|
{ .compatible = "nxp,pn544-i2c", }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, of_pn544_i2c_match); |
|
|
|
static struct i2c_driver pn544_hci_i2c_driver = { |
|
.driver = { |
|
.name = PN544_HCI_I2C_DRIVER_NAME, |
|
.of_match_table = of_match_ptr(of_pn544_i2c_match), |
|
.acpi_match_table = ACPI_PTR(pn544_hci_i2c_acpi_match), |
|
}, |
|
.probe = pn544_hci_i2c_probe, |
|
.id_table = pn544_hci_i2c_id_table, |
|
.remove = pn544_hci_i2c_remove, |
|
}; |
|
|
|
module_i2c_driver(pn544_hci_i2c_driver); |
|
|
|
MODULE_LICENSE("GPL"); |
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
|