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704 lines
18 KiB
704 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Actions Semi Owl SoCs SD/MMC driver |
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* |
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* Copyright (c) 2014 Actions Semi Inc. |
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* Copyright (c) 2019 Manivannan Sadhasivam <[email protected]> |
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* |
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* TODO: SDIO support |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/dmaengine.h> |
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#include <linux/dma-direction.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/interrupt.h> |
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#include <linux/mmc/host.h> |
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#include <linux/mmc/slot-gpio.h> |
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#include <linux/module.h> |
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#include <linux/of_platform.h> |
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#include <linux/reset.h> |
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#include <linux/spinlock.h> |
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|
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/* |
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* SDC registers |
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*/ |
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#define OWL_REG_SD_EN 0x0000 |
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#define OWL_REG_SD_CTL 0x0004 |
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#define OWL_REG_SD_STATE 0x0008 |
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#define OWL_REG_SD_CMD 0x000c |
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#define OWL_REG_SD_ARG 0x0010 |
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#define OWL_REG_SD_RSPBUF0 0x0014 |
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#define OWL_REG_SD_RSPBUF1 0x0018 |
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#define OWL_REG_SD_RSPBUF2 0x001c |
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#define OWL_REG_SD_RSPBUF3 0x0020 |
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#define OWL_REG_SD_RSPBUF4 0x0024 |
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#define OWL_REG_SD_DAT 0x0028 |
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#define OWL_REG_SD_BLK_SIZE 0x002c |
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#define OWL_REG_SD_BLK_NUM 0x0030 |
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#define OWL_REG_SD_BUF_SIZE 0x0034 |
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|
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/* SD_EN Bits */ |
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#define OWL_SD_EN_RANE BIT(31) |
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#define OWL_SD_EN_RAN_SEED(x) (((x) & 0x3f) << 24) |
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#define OWL_SD_EN_S18EN BIT(12) |
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#define OWL_SD_EN_RESE BIT(10) |
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#define OWL_SD_EN_DAT1_S BIT(9) |
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#define OWL_SD_EN_CLK_S BIT(8) |
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#define OWL_SD_ENABLE BIT(7) |
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#define OWL_SD_EN_BSEL BIT(6) |
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#define OWL_SD_EN_SDIOEN BIT(3) |
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#define OWL_SD_EN_DDREN BIT(2) |
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#define OWL_SD_EN_DATAWID(x) (((x) & 0x3) << 0) |
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|
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/* SD_CTL Bits */ |
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#define OWL_SD_CTL_TOUTEN BIT(31) |
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#define OWL_SD_CTL_TOUTCNT(x) (((x) & 0x7f) << 24) |
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#define OWL_SD_CTL_DELAY_MSK GENMASK(23, 16) |
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#define OWL_SD_CTL_RDELAY(x) (((x) & 0xf) << 20) |
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#define OWL_SD_CTL_WDELAY(x) (((x) & 0xf) << 16) |
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#define OWL_SD_CTL_CMDLEN BIT(13) |
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#define OWL_SD_CTL_SCC BIT(12) |
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#define OWL_SD_CTL_TCN(x) (((x) & 0xf) << 8) |
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#define OWL_SD_CTL_TS BIT(7) |
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#define OWL_SD_CTL_LBE BIT(6) |
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#define OWL_SD_CTL_C7EN BIT(5) |
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#define OWL_SD_CTL_TM(x) (((x) & 0xf) << 0) |
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|
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#define OWL_SD_DELAY_LOW_CLK 0x0f |
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#define OWL_SD_DELAY_MID_CLK 0x0a |
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#define OWL_SD_DELAY_HIGH_CLK 0x09 |
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#define OWL_SD_RDELAY_DDR50 0x0a |
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#define OWL_SD_WDELAY_DDR50 0x08 |
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|
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/* SD_STATE Bits */ |
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#define OWL_SD_STATE_DAT1BS BIT(18) |
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#define OWL_SD_STATE_SDIOB_P BIT(17) |
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#define OWL_SD_STATE_SDIOB_EN BIT(16) |
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#define OWL_SD_STATE_TOUTE BIT(15) |
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#define OWL_SD_STATE_BAEP BIT(14) |
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#define OWL_SD_STATE_MEMRDY BIT(12) |
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#define OWL_SD_STATE_CMDS BIT(11) |
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#define OWL_SD_STATE_DAT1AS BIT(10) |
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#define OWL_SD_STATE_SDIOA_P BIT(9) |
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#define OWL_SD_STATE_SDIOA_EN BIT(8) |
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#define OWL_SD_STATE_DAT0S BIT(7) |
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#define OWL_SD_STATE_TEIE BIT(6) |
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#define OWL_SD_STATE_TEI BIT(5) |
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#define OWL_SD_STATE_CLNR BIT(4) |
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#define OWL_SD_STATE_CLC BIT(3) |
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#define OWL_SD_STATE_WC16ER BIT(2) |
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#define OWL_SD_STATE_RC16ER BIT(1) |
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#define OWL_SD_STATE_CRC7ER BIT(0) |
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|
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#define OWL_CMD_TIMEOUT_MS 30000 |
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struct owl_mmc_host { |
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struct device *dev; |
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struct reset_control *reset; |
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void __iomem *base; |
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struct clk *clk; |
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struct completion sdc_complete; |
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spinlock_t lock; |
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int irq; |
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u32 clock; |
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bool ddr_50; |
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enum dma_data_direction dma_dir; |
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struct dma_chan *dma; |
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struct dma_async_tx_descriptor *desc; |
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struct dma_slave_config dma_cfg; |
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struct completion dma_complete; |
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struct mmc_host *mmc; |
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struct mmc_request *mrq; |
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struct mmc_command *cmd; |
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struct mmc_data *data; |
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}; |
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static void owl_mmc_update_reg(void __iomem *reg, unsigned int val, bool state) |
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{ |
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unsigned int regval; |
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regval = readl(reg); |
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if (state) |
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regval |= val; |
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else |
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regval &= ~val; |
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writel(regval, reg); |
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} |
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static irqreturn_t owl_irq_handler(int irq, void *devid) |
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{ |
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struct owl_mmc_host *owl_host = devid; |
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u32 state; |
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spin_lock(&owl_host->lock); |
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state = readl(owl_host->base + OWL_REG_SD_STATE); |
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if (state & OWL_SD_STATE_TEI) { |
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state = readl(owl_host->base + OWL_REG_SD_STATE); |
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state |= OWL_SD_STATE_TEI; |
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writel(state, owl_host->base + OWL_REG_SD_STATE); |
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complete(&owl_host->sdc_complete); |
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} |
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spin_unlock(&owl_host->lock); |
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return IRQ_HANDLED; |
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} |
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static void owl_mmc_finish_request(struct owl_mmc_host *owl_host) |
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{ |
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struct mmc_request *mrq = owl_host->mrq; |
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struct mmc_data *data = mrq->data; |
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/* Should never be NULL */ |
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WARN_ON(!mrq); |
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owl_host->mrq = NULL; |
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if (data) |
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dma_unmap_sg(owl_host->dma->device->dev, data->sg, data->sg_len, |
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owl_host->dma_dir); |
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/* Finally finish request */ |
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mmc_request_done(owl_host->mmc, mrq); |
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} |
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static void owl_mmc_send_cmd(struct owl_mmc_host *owl_host, |
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struct mmc_command *cmd, |
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struct mmc_data *data) |
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{ |
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unsigned long timeout; |
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u32 mode, state, resp[2]; |
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u32 cmd_rsp_mask = 0; |
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init_completion(&owl_host->sdc_complete); |
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switch (mmc_resp_type(cmd)) { |
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case MMC_RSP_NONE: |
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mode = OWL_SD_CTL_TM(0); |
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break; |
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case MMC_RSP_R1: |
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if (data) { |
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if (data->flags & MMC_DATA_READ) |
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mode = OWL_SD_CTL_TM(4); |
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else |
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mode = OWL_SD_CTL_TM(5); |
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} else { |
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mode = OWL_SD_CTL_TM(1); |
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} |
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cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER; |
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break; |
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case MMC_RSP_R1B: |
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mode = OWL_SD_CTL_TM(3); |
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cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER; |
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break; |
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case MMC_RSP_R2: |
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mode = OWL_SD_CTL_TM(2); |
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cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER; |
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break; |
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case MMC_RSP_R3: |
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mode = OWL_SD_CTL_TM(1); |
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cmd_rsp_mask = OWL_SD_STATE_CLNR; |
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break; |
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default: |
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dev_warn(owl_host->dev, "Unknown MMC command\n"); |
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cmd->error = -EINVAL; |
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return; |
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} |
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/* Keep current WDELAY and RDELAY */ |
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mode |= (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16)); |
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/* Start to send corresponding command type */ |
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writel(cmd->arg, owl_host->base + OWL_REG_SD_ARG); |
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writel(cmd->opcode, owl_host->base + OWL_REG_SD_CMD); |
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/* Set LBE to send clk at the end of last read block */ |
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if (data) { |
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mode |= (OWL_SD_CTL_TS | OWL_SD_CTL_LBE | 0x64000000); |
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} else { |
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mode &= ~(OWL_SD_CTL_TOUTEN | OWL_SD_CTL_LBE); |
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mode |= OWL_SD_CTL_TS; |
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} |
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owl_host->cmd = cmd; |
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/* Start transfer */ |
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writel(mode, owl_host->base + OWL_REG_SD_CTL); |
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if (data) |
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return; |
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timeout = msecs_to_jiffies(cmd->busy_timeout ? cmd->busy_timeout : |
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OWL_CMD_TIMEOUT_MS); |
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if (!wait_for_completion_timeout(&owl_host->sdc_complete, timeout)) { |
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dev_err(owl_host->dev, "CMD interrupt timeout\n"); |
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cmd->error = -ETIMEDOUT; |
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return; |
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} |
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state = readl(owl_host->base + OWL_REG_SD_STATE); |
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if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { |
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if (cmd_rsp_mask & state) { |
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if (state & OWL_SD_STATE_CLNR) { |
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dev_err(owl_host->dev, "Error CMD_NO_RSP\n"); |
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cmd->error = -EILSEQ; |
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return; |
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} |
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if (state & OWL_SD_STATE_CRC7ER) { |
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dev_err(owl_host->dev, "Error CMD_RSP_CRC\n"); |
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cmd->error = -EILSEQ; |
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return; |
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} |
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} |
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if (mmc_resp_type(cmd) & MMC_RSP_136) { |
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cmd->resp[3] = readl(owl_host->base + OWL_REG_SD_RSPBUF0); |
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cmd->resp[2] = readl(owl_host->base + OWL_REG_SD_RSPBUF1); |
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cmd->resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF2); |
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cmd->resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF3); |
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} else { |
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resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF0); |
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resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF1); |
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cmd->resp[0] = resp[1] << 24 | resp[0] >> 8; |
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cmd->resp[1] = resp[1] >> 8; |
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} |
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} |
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} |
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static void owl_mmc_dma_complete(void *param) |
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{ |
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struct owl_mmc_host *owl_host = param; |
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struct mmc_data *data = owl_host->data; |
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if (data) |
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complete(&owl_host->dma_complete); |
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} |
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static int owl_mmc_prepare_data(struct owl_mmc_host *owl_host, |
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struct mmc_data *data) |
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{ |
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u32 total; |
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owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, OWL_SD_EN_BSEL, |
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true); |
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writel(data->blocks, owl_host->base + OWL_REG_SD_BLK_NUM); |
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writel(data->blksz, owl_host->base + OWL_REG_SD_BLK_SIZE); |
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total = data->blksz * data->blocks; |
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if (total < 512) |
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writel(total, owl_host->base + OWL_REG_SD_BUF_SIZE); |
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else |
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writel(512, owl_host->base + OWL_REG_SD_BUF_SIZE); |
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if (data->flags & MMC_DATA_WRITE) { |
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owl_host->dma_dir = DMA_TO_DEVICE; |
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owl_host->dma_cfg.direction = DMA_MEM_TO_DEV; |
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} else { |
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owl_host->dma_dir = DMA_FROM_DEVICE; |
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owl_host->dma_cfg.direction = DMA_DEV_TO_MEM; |
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} |
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dma_map_sg(owl_host->dma->device->dev, data->sg, |
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data->sg_len, owl_host->dma_dir); |
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dmaengine_slave_config(owl_host->dma, &owl_host->dma_cfg); |
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owl_host->desc = dmaengine_prep_slave_sg(owl_host->dma, data->sg, |
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data->sg_len, |
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owl_host->dma_cfg.direction, |
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DMA_PREP_INTERRUPT | |
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DMA_CTRL_ACK); |
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if (!owl_host->desc) { |
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dev_err(owl_host->dev, "Can't prepare slave sg\n"); |
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return -EBUSY; |
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} |
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owl_host->data = data; |
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owl_host->desc->callback = owl_mmc_dma_complete; |
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owl_host->desc->callback_param = (void *)owl_host; |
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data->error = 0; |
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return 0; |
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} |
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static void owl_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) |
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{ |
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struct owl_mmc_host *owl_host = mmc_priv(mmc); |
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struct mmc_data *data = mrq->data; |
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int ret; |
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owl_host->mrq = mrq; |
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if (mrq->data) { |
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ret = owl_mmc_prepare_data(owl_host, data); |
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if (ret < 0) { |
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data->error = ret; |
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goto err_out; |
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} |
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init_completion(&owl_host->dma_complete); |
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dmaengine_submit(owl_host->desc); |
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dma_async_issue_pending(owl_host->dma); |
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} |
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owl_mmc_send_cmd(owl_host, mrq->cmd, data); |
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if (data) { |
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if (!wait_for_completion_timeout(&owl_host->sdc_complete, |
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10 * HZ)) { |
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dev_err(owl_host->dev, "CMD interrupt timeout\n"); |
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mrq->cmd->error = -ETIMEDOUT; |
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dmaengine_terminate_all(owl_host->dma); |
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goto err_out; |
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} |
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if (!wait_for_completion_timeout(&owl_host->dma_complete, |
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5 * HZ)) { |
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dev_err(owl_host->dev, "DMA interrupt timeout\n"); |
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mrq->cmd->error = -ETIMEDOUT; |
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dmaengine_terminate_all(owl_host->dma); |
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goto err_out; |
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} |
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if (data->stop) |
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owl_mmc_send_cmd(owl_host, data->stop, NULL); |
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data->bytes_xfered = data->blocks * data->blksz; |
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} |
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err_out: |
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owl_mmc_finish_request(owl_host); |
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} |
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static int owl_mmc_set_clk_rate(struct owl_mmc_host *owl_host, |
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unsigned int rate) |
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{ |
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unsigned long clk_rate; |
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int ret; |
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u32 reg; |
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reg = readl(owl_host->base + OWL_REG_SD_CTL); |
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reg &= ~OWL_SD_CTL_DELAY_MSK; |
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/* Set RDELAY and WDELAY based on the clock */ |
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if (rate <= 1000000) { |
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writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_LOW_CLK) | |
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OWL_SD_CTL_WDELAY(OWL_SD_DELAY_LOW_CLK), |
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owl_host->base + OWL_REG_SD_CTL); |
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} else if ((rate > 1000000) && (rate <= 26000000)) { |
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writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_MID_CLK) | |
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OWL_SD_CTL_WDELAY(OWL_SD_DELAY_MID_CLK), |
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owl_host->base + OWL_REG_SD_CTL); |
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} else if ((rate > 26000000) && (rate <= 52000000) && !owl_host->ddr_50) { |
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writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_HIGH_CLK) | |
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OWL_SD_CTL_WDELAY(OWL_SD_DELAY_HIGH_CLK), |
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owl_host->base + OWL_REG_SD_CTL); |
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/* DDR50 mode has special delay chain */ |
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} else if ((rate > 26000000) && (rate <= 52000000) && owl_host->ddr_50) { |
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writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_RDELAY_DDR50) | |
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OWL_SD_CTL_WDELAY(OWL_SD_WDELAY_DDR50), |
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owl_host->base + OWL_REG_SD_CTL); |
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} else { |
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dev_err(owl_host->dev, "SD clock rate not supported\n"); |
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return -EINVAL; |
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} |
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clk_rate = clk_round_rate(owl_host->clk, rate << 1); |
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ret = clk_set_rate(owl_host->clk, clk_rate); |
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|
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return ret; |
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} |
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static void owl_mmc_set_clk(struct owl_mmc_host *owl_host, struct mmc_ios *ios) |
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{ |
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if (!ios->clock) |
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return; |
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owl_host->clock = ios->clock; |
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owl_mmc_set_clk_rate(owl_host, ios->clock); |
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} |
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|
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static void owl_mmc_set_bus_width(struct owl_mmc_host *owl_host, |
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struct mmc_ios *ios) |
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{ |
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u32 reg; |
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|
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reg = readl(owl_host->base + OWL_REG_SD_EN); |
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reg &= ~0x03; |
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switch (ios->bus_width) { |
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case MMC_BUS_WIDTH_1: |
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break; |
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case MMC_BUS_WIDTH_4: |
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reg |= OWL_SD_EN_DATAWID(1); |
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break; |
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case MMC_BUS_WIDTH_8: |
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reg |= OWL_SD_EN_DATAWID(2); |
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break; |
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} |
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|
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writel(reg, owl_host->base + OWL_REG_SD_EN); |
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} |
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|
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static void owl_mmc_ctr_reset(struct owl_mmc_host *owl_host) |
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{ |
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reset_control_assert(owl_host->reset); |
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udelay(20); |
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reset_control_deassert(owl_host->reset); |
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} |
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|
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static void owl_mmc_power_on(struct owl_mmc_host *owl_host) |
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{ |
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u32 mode; |
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init_completion(&owl_host->sdc_complete); |
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|
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/* Enable transfer end IRQ */ |
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owl_mmc_update_reg(owl_host->base + OWL_REG_SD_STATE, |
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OWL_SD_STATE_TEIE, true); |
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|
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/* Send init clk */ |
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mode = (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16)); |
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mode |= OWL_SD_CTL_TS | OWL_SD_CTL_TCN(5) | OWL_SD_CTL_TM(8); |
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writel(mode, owl_host->base + OWL_REG_SD_CTL); |
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|
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if (!wait_for_completion_timeout(&owl_host->sdc_complete, HZ)) { |
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dev_err(owl_host->dev, "CMD interrupt timeout\n"); |
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return; |
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} |
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} |
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|
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static void owl_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
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{ |
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struct owl_mmc_host *owl_host = mmc_priv(mmc); |
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|
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switch (ios->power_mode) { |
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case MMC_POWER_UP: |
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dev_dbg(owl_host->dev, "Powering card up\n"); |
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|
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/* Reset the SDC controller to clear all previous states */ |
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owl_mmc_ctr_reset(owl_host); |
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clk_prepare_enable(owl_host->clk); |
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writel(OWL_SD_ENABLE | OWL_SD_EN_RESE, |
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owl_host->base + OWL_REG_SD_EN); |
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|
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break; |
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|
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case MMC_POWER_ON: |
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dev_dbg(owl_host->dev, "Powering card on\n"); |
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owl_mmc_power_on(owl_host); |
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|
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break; |
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|
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case MMC_POWER_OFF: |
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dev_dbg(owl_host->dev, "Powering card off\n"); |
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clk_disable_unprepare(owl_host->clk); |
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|
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return; |
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|
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default: |
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dev_dbg(owl_host->dev, "Ignoring unknown card power state\n"); |
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break; |
|
} |
|
|
|
if (ios->clock != owl_host->clock) |
|
owl_mmc_set_clk(owl_host, ios); |
|
|
|
owl_mmc_set_bus_width(owl_host, ios); |
|
|
|
/* Enable DDR mode if requested */ |
|
if (ios->timing == MMC_TIMING_UHS_DDR50) { |
|
owl_host->ddr_50 = true; |
|
owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, |
|
OWL_SD_EN_DDREN, true); |
|
} else { |
|
owl_host->ddr_50 = false; |
|
} |
|
} |
|
|
|
static int owl_mmc_start_signal_voltage_switch(struct mmc_host *mmc, |
|
struct mmc_ios *ios) |
|
{ |
|
struct owl_mmc_host *owl_host = mmc_priv(mmc); |
|
|
|
/* It is enough to change the pad ctrl bit for voltage switch */ |
|
switch (ios->signal_voltage) { |
|
case MMC_SIGNAL_VOLTAGE_330: |
|
owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, |
|
OWL_SD_EN_S18EN, false); |
|
break; |
|
case MMC_SIGNAL_VOLTAGE_180: |
|
owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, |
|
OWL_SD_EN_S18EN, true); |
|
break; |
|
default: |
|
return -ENOTSUPP; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static const struct mmc_host_ops owl_mmc_ops = { |
|
.request = owl_mmc_request, |
|
.set_ios = owl_mmc_set_ios, |
|
.get_ro = mmc_gpio_get_ro, |
|
.get_cd = mmc_gpio_get_cd, |
|
.start_signal_voltage_switch = owl_mmc_start_signal_voltage_switch, |
|
}; |
|
|
|
static int owl_mmc_probe(struct platform_device *pdev) |
|
{ |
|
struct owl_mmc_host *owl_host; |
|
struct mmc_host *mmc; |
|
struct resource *res; |
|
int ret; |
|
|
|
mmc = mmc_alloc_host(sizeof(struct owl_mmc_host), &pdev->dev); |
|
if (!mmc) { |
|
dev_err(&pdev->dev, "mmc alloc host failed\n"); |
|
return -ENOMEM; |
|
} |
|
platform_set_drvdata(pdev, mmc); |
|
|
|
owl_host = mmc_priv(mmc); |
|
owl_host->dev = &pdev->dev; |
|
owl_host->mmc = mmc; |
|
spin_lock_init(&owl_host->lock); |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
owl_host->base = devm_ioremap_resource(&pdev->dev, res); |
|
if (IS_ERR(owl_host->base)) { |
|
ret = PTR_ERR(owl_host->base); |
|
goto err_free_host; |
|
} |
|
|
|
owl_host->clk = devm_clk_get(&pdev->dev, NULL); |
|
if (IS_ERR(owl_host->clk)) { |
|
dev_err(&pdev->dev, "No clock defined\n"); |
|
ret = PTR_ERR(owl_host->clk); |
|
goto err_free_host; |
|
} |
|
|
|
owl_host->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); |
|
if (IS_ERR(owl_host->reset)) { |
|
dev_err(&pdev->dev, "Could not get reset control\n"); |
|
ret = PTR_ERR(owl_host->reset); |
|
goto err_free_host; |
|
} |
|
|
|
mmc->ops = &owl_mmc_ops; |
|
mmc->max_blk_count = 512; |
|
mmc->max_blk_size = 512; |
|
mmc->max_segs = 256; |
|
mmc->max_seg_size = 262144; |
|
mmc->max_req_size = 262144; |
|
/* 100kHz ~ 52MHz */ |
|
mmc->f_min = 100000; |
|
mmc->f_max = 52000000; |
|
mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | |
|
MMC_CAP_4_BIT_DATA; |
|
mmc->caps2 = (MMC_CAP2_BOOTPART_NOACC | MMC_CAP2_NO_SDIO); |
|
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | |
|
MMC_VDD_165_195; |
|
|
|
ret = mmc_of_parse(mmc); |
|
if (ret) |
|
goto err_free_host; |
|
|
|
pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); |
|
pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; |
|
owl_host->dma = dma_request_chan(&pdev->dev, "mmc"); |
|
if (IS_ERR(owl_host->dma)) { |
|
dev_err(owl_host->dev, "Failed to get external DMA channel.\n"); |
|
ret = PTR_ERR(owl_host->dma); |
|
goto err_free_host; |
|
} |
|
|
|
dev_info(&pdev->dev, "Using %s for DMA transfers\n", |
|
dma_chan_name(owl_host->dma)); |
|
|
|
owl_host->dma_cfg.src_addr = res->start + OWL_REG_SD_DAT; |
|
owl_host->dma_cfg.dst_addr = res->start + OWL_REG_SD_DAT; |
|
owl_host->dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
|
owl_host->dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
|
owl_host->dma_cfg.device_fc = false; |
|
|
|
owl_host->irq = platform_get_irq(pdev, 0); |
|
if (owl_host->irq < 0) { |
|
ret = -EINVAL; |
|
goto err_release_channel; |
|
} |
|
|
|
ret = devm_request_irq(&pdev->dev, owl_host->irq, owl_irq_handler, |
|
0, dev_name(&pdev->dev), owl_host); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Failed to request irq %d\n", |
|
owl_host->irq); |
|
goto err_release_channel; |
|
} |
|
|
|
ret = mmc_add_host(mmc); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Failed to add host\n"); |
|
goto err_release_channel; |
|
} |
|
|
|
dev_dbg(&pdev->dev, "Owl MMC Controller Initialized\n"); |
|
|
|
return 0; |
|
|
|
err_release_channel: |
|
dma_release_channel(owl_host->dma); |
|
err_free_host: |
|
mmc_free_host(mmc); |
|
|
|
return ret; |
|
} |
|
|
|
static int owl_mmc_remove(struct platform_device *pdev) |
|
{ |
|
struct mmc_host *mmc = platform_get_drvdata(pdev); |
|
struct owl_mmc_host *owl_host = mmc_priv(mmc); |
|
|
|
mmc_remove_host(mmc); |
|
disable_irq(owl_host->irq); |
|
dma_release_channel(owl_host->dma); |
|
mmc_free_host(mmc); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id owl_mmc_of_match[] = { |
|
{.compatible = "actions,owl-mmc",}, |
|
{ /* sentinel */ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, owl_mmc_of_match); |
|
|
|
static struct platform_driver owl_mmc_driver = { |
|
.driver = { |
|
.name = "owl_mmc", |
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS, |
|
.of_match_table = owl_mmc_of_match, |
|
}, |
|
.probe = owl_mmc_probe, |
|
.remove = owl_mmc_remove, |
|
}; |
|
module_platform_driver(owl_mmc_driver); |
|
|
|
MODULE_DESCRIPTION("Actions Semi Owl SoCs SD/MMC Driver"); |
|
MODULE_AUTHOR("Actions Semi"); |
|
MODULE_AUTHOR("Manivannan Sadhasivam <[email protected]>"); |
|
MODULE_LICENSE("GPL");
|
|
|