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1169 lines
29 KiB
1169 lines
29 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2009-2010, Lars-Peter Clausen <[email protected]> |
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* Copyright (C) 2013, Imagination Technologies |
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* |
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* JZ4740 SD/MMC controller driver |
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*/ |
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|
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/dmaengine.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/err.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/mmc/host.h> |
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#include <linux/mmc/slot-gpio.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/pinctrl/consumer.h> |
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#include <linux/platform_device.h> |
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#include <linux/scatterlist.h> |
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#include <asm/cacheflush.h> |
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|
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#define JZ_REG_MMC_STRPCL 0x00 |
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#define JZ_REG_MMC_STATUS 0x04 |
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#define JZ_REG_MMC_CLKRT 0x08 |
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#define JZ_REG_MMC_CMDAT 0x0C |
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#define JZ_REG_MMC_RESTO 0x10 |
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#define JZ_REG_MMC_RDTO 0x14 |
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#define JZ_REG_MMC_BLKLEN 0x18 |
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#define JZ_REG_MMC_NOB 0x1C |
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#define JZ_REG_MMC_SNOB 0x20 |
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#define JZ_REG_MMC_IMASK 0x24 |
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#define JZ_REG_MMC_IREG 0x28 |
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#define JZ_REG_MMC_CMD 0x2C |
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#define JZ_REG_MMC_ARG 0x30 |
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#define JZ_REG_MMC_RESP_FIFO 0x34 |
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#define JZ_REG_MMC_RXFIFO 0x38 |
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#define JZ_REG_MMC_TXFIFO 0x3C |
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#define JZ_REG_MMC_LPM 0x40 |
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#define JZ_REG_MMC_DMAC 0x44 |
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|
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#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7) |
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#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6) |
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#define JZ_MMC_STRPCL_START_READWAIT BIT(5) |
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#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4) |
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#define JZ_MMC_STRPCL_RESET BIT(3) |
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#define JZ_MMC_STRPCL_START_OP BIT(2) |
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#define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0)) |
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#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0) |
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#define JZ_MMC_STRPCL_CLOCK_START BIT(1) |
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|
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#define JZ_MMC_STATUS_IS_RESETTING BIT(15) |
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#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14) |
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#define JZ_MMC_STATUS_PRG_DONE BIT(13) |
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#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12) |
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#define JZ_MMC_STATUS_END_CMD_RES BIT(11) |
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#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10) |
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#define JZ_MMC_STATUS_IS_READWAIT BIT(9) |
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#define JZ_MMC_STATUS_CLK_EN BIT(8) |
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#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7) |
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#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6) |
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#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5) |
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#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4) |
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#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3) |
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#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2) |
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#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1) |
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#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0) |
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|
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#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0)) |
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#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2)) |
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#define JZ_MMC_CMDAT_IO_ABORT BIT(11) |
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#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10) |
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#define JZ_MMC_CMDAT_BUS_WIDTH_8BIT (BIT(10) | BIT(9)) |
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#define JZ_MMC_CMDAT_BUS_WIDTH_MASK (BIT(10) | BIT(9)) |
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#define JZ_MMC_CMDAT_DMA_EN BIT(8) |
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#define JZ_MMC_CMDAT_INIT BIT(7) |
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#define JZ_MMC_CMDAT_BUSY BIT(6) |
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#define JZ_MMC_CMDAT_STREAM BIT(5) |
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#define JZ_MMC_CMDAT_WRITE BIT(4) |
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#define JZ_MMC_CMDAT_DATA_EN BIT(3) |
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#define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0)) |
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#define JZ_MMC_CMDAT_RSP_R1 1 |
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#define JZ_MMC_CMDAT_RSP_R2 2 |
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#define JZ_MMC_CMDAT_RSP_R3 3 |
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|
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#define JZ_MMC_IRQ_SDIO BIT(7) |
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#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6) |
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#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5) |
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#define JZ_MMC_IRQ_END_CMD_RES BIT(2) |
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#define JZ_MMC_IRQ_PRG_DONE BIT(1) |
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#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0) |
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|
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#define JZ_MMC_DMAC_DMA_SEL BIT(1) |
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#define JZ_MMC_DMAC_DMA_EN BIT(0) |
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|
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#define JZ_MMC_LPM_DRV_RISING BIT(31) |
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#define JZ_MMC_LPM_DRV_RISING_QTR_PHASE_DLY BIT(31) |
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#define JZ_MMC_LPM_DRV_RISING_1NS_DLY BIT(30) |
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#define JZ_MMC_LPM_SMP_RISING_QTR_OR_HALF_PHASE_DLY BIT(29) |
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#define JZ_MMC_LPM_LOW_POWER_MODE_EN BIT(0) |
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|
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#define JZ_MMC_CLK_RATE 24000000 |
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#define JZ_MMC_REQ_TIMEOUT_MS 5000 |
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|
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enum jz4740_mmc_version { |
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JZ_MMC_JZ4740, |
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JZ_MMC_JZ4725B, |
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JZ_MMC_JZ4760, |
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JZ_MMC_JZ4780, |
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JZ_MMC_X1000, |
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}; |
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|
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enum jz4740_mmc_state { |
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JZ4740_MMC_STATE_READ_RESPONSE, |
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JZ4740_MMC_STATE_TRANSFER_DATA, |
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JZ4740_MMC_STATE_SEND_STOP, |
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JZ4740_MMC_STATE_DONE, |
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}; |
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|
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/* |
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* The MMC core allows to prepare a mmc_request while another mmc_request |
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* is in-flight. This is used via the pre_req/post_req hooks. |
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* This driver uses the pre_req/post_req hooks to map/unmap the mmc_request. |
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* Following what other drivers do (sdhci, dw_mmc) we use the following cookie |
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* flags to keep track of the mmc_request mapping state. |
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* |
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* COOKIE_UNMAPPED: the request is not mapped. |
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* COOKIE_PREMAPPED: the request was mapped in pre_req, |
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* and should be unmapped in post_req. |
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* COOKIE_MAPPED: the request was mapped in the irq handler, |
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* and should be unmapped before mmc_request_done is called.. |
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*/ |
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enum jz4780_cookie { |
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COOKIE_UNMAPPED = 0, |
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COOKIE_PREMAPPED, |
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COOKIE_MAPPED, |
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}; |
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|
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struct jz4740_mmc_host { |
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struct mmc_host *mmc; |
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struct platform_device *pdev; |
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struct clk *clk; |
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|
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enum jz4740_mmc_version version; |
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|
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int irq; |
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|
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void __iomem *base; |
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struct resource *mem_res; |
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struct mmc_request *req; |
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struct mmc_command *cmd; |
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unsigned long waiting; |
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|
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uint32_t cmdat; |
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uint32_t irq_mask; |
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|
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spinlock_t lock; |
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|
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struct timer_list timeout_timer; |
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struct sg_mapping_iter miter; |
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enum jz4740_mmc_state state; |
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|
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/* DMA support */ |
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struct dma_chan *dma_rx; |
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struct dma_chan *dma_tx; |
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bool use_dma; |
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|
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/* The DMA trigger level is 8 words, that is to say, the DMA read |
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* trigger is when data words in MSC_RXFIFO is >= 8 and the DMA write |
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* trigger is when data words in MSC_TXFIFO is < 8. |
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*/ |
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#define JZ4740_MMC_FIFO_HALF_SIZE 8 |
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}; |
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|
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static void jz4740_mmc_write_irq_mask(struct jz4740_mmc_host *host, |
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uint32_t val) |
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{ |
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if (host->version >= JZ_MMC_JZ4725B) |
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return writel(val, host->base + JZ_REG_MMC_IMASK); |
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else |
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return writew(val, host->base + JZ_REG_MMC_IMASK); |
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} |
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|
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static void jz4740_mmc_write_irq_reg(struct jz4740_mmc_host *host, |
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uint32_t val) |
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{ |
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if (host->version >= JZ_MMC_JZ4780) |
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writel(val, host->base + JZ_REG_MMC_IREG); |
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else |
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writew(val, host->base + JZ_REG_MMC_IREG); |
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} |
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|
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static uint32_t jz4740_mmc_read_irq_reg(struct jz4740_mmc_host *host) |
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{ |
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if (host->version >= JZ_MMC_JZ4780) |
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return readl(host->base + JZ_REG_MMC_IREG); |
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else |
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return readw(host->base + JZ_REG_MMC_IREG); |
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} |
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|
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/*----------------------------------------------------------------------------*/ |
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/* DMA infrastructure */ |
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|
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static void jz4740_mmc_release_dma_channels(struct jz4740_mmc_host *host) |
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{ |
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if (!host->use_dma) |
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return; |
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|
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dma_release_channel(host->dma_tx); |
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if (host->dma_rx) |
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dma_release_channel(host->dma_rx); |
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} |
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|
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static int jz4740_mmc_acquire_dma_channels(struct jz4740_mmc_host *host) |
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{ |
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struct device *dev = mmc_dev(host->mmc); |
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host->dma_tx = dma_request_chan(dev, "tx-rx"); |
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if (!IS_ERR(host->dma_tx)) |
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return 0; |
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if (PTR_ERR(host->dma_tx) != -ENODEV) { |
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dev_err(dev, "Failed to get dma tx-rx channel\n"); |
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return PTR_ERR(host->dma_tx); |
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} |
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host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx"); |
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if (IS_ERR(host->dma_tx)) { |
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dev_err(mmc_dev(host->mmc), "Failed to get dma_tx channel\n"); |
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return PTR_ERR(host->dma_tx); |
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} |
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host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx"); |
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if (IS_ERR(host->dma_rx)) { |
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dev_err(mmc_dev(host->mmc), "Failed to get dma_rx channel\n"); |
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dma_release_channel(host->dma_tx); |
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return PTR_ERR(host->dma_rx); |
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} |
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/* |
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* Limit the maximum segment size in any SG entry according to |
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* the parameters of the DMA engine device. |
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*/ |
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if (host->dma_tx) { |
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struct device *dev = host->dma_tx->device->dev; |
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unsigned int max_seg_size = dma_get_max_seg_size(dev); |
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if (max_seg_size < host->mmc->max_seg_size) |
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host->mmc->max_seg_size = max_seg_size; |
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} |
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if (host->dma_rx) { |
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struct device *dev = host->dma_rx->device->dev; |
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unsigned int max_seg_size = dma_get_max_seg_size(dev); |
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if (max_seg_size < host->mmc->max_seg_size) |
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host->mmc->max_seg_size = max_seg_size; |
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} |
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return 0; |
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} |
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static inline struct dma_chan *jz4740_mmc_get_dma_chan(struct jz4740_mmc_host *host, |
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struct mmc_data *data) |
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{ |
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if ((data->flags & MMC_DATA_READ) && host->dma_rx) |
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return host->dma_rx; |
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else |
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return host->dma_tx; |
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} |
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static void jz4740_mmc_dma_unmap(struct jz4740_mmc_host *host, |
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struct mmc_data *data) |
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{ |
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struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); |
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enum dma_data_direction dir = mmc_get_dma_dir(data); |
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dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); |
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data->host_cookie = COOKIE_UNMAPPED; |
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} |
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/* Prepares DMA data for current or next transfer. |
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* A request can be in-flight when this is called. |
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*/ |
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static int jz4740_mmc_prepare_dma_data(struct jz4740_mmc_host *host, |
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struct mmc_data *data, |
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int cookie) |
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{ |
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struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); |
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enum dma_data_direction dir = mmc_get_dma_dir(data); |
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unsigned int sg_count; |
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if (data->host_cookie == COOKIE_PREMAPPED) |
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return data->sg_count; |
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sg_count = dma_map_sg(chan->device->dev, |
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data->sg, |
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data->sg_len, |
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dir); |
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if (!sg_count) { |
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dev_err(mmc_dev(host->mmc), |
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"Failed to map scatterlist for DMA operation\n"); |
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return -EINVAL; |
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} |
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data->sg_count = sg_count; |
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data->host_cookie = cookie; |
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return data->sg_count; |
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} |
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static int jz4740_mmc_start_dma_transfer(struct jz4740_mmc_host *host, |
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struct mmc_data *data) |
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{ |
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struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); |
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struct dma_async_tx_descriptor *desc; |
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struct dma_slave_config conf = { |
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.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
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.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
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.src_maxburst = JZ4740_MMC_FIFO_HALF_SIZE, |
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.dst_maxburst = JZ4740_MMC_FIFO_HALF_SIZE, |
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}; |
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int sg_count; |
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if (data->flags & MMC_DATA_WRITE) { |
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conf.direction = DMA_MEM_TO_DEV; |
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conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO; |
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} else { |
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conf.direction = DMA_DEV_TO_MEM; |
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conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO; |
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} |
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sg_count = jz4740_mmc_prepare_dma_data(host, data, COOKIE_MAPPED); |
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if (sg_count < 0) |
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return sg_count; |
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dmaengine_slave_config(chan, &conf); |
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desc = dmaengine_prep_slave_sg(chan, data->sg, sg_count, |
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conf.direction, |
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
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if (!desc) { |
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dev_err(mmc_dev(host->mmc), |
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"Failed to allocate DMA %s descriptor", |
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conf.direction == DMA_MEM_TO_DEV ? "TX" : "RX"); |
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goto dma_unmap; |
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} |
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dmaengine_submit(desc); |
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dma_async_issue_pending(chan); |
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return 0; |
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dma_unmap: |
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if (data->host_cookie == COOKIE_MAPPED) |
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jz4740_mmc_dma_unmap(host, data); |
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return -ENOMEM; |
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} |
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|
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static void jz4740_mmc_pre_request(struct mmc_host *mmc, |
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struct mmc_request *mrq) |
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{ |
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struct jz4740_mmc_host *host = mmc_priv(mmc); |
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struct mmc_data *data = mrq->data; |
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|
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if (!host->use_dma) |
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return; |
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data->host_cookie = COOKIE_UNMAPPED; |
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if (jz4740_mmc_prepare_dma_data(host, data, COOKIE_PREMAPPED) < 0) |
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data->host_cookie = COOKIE_UNMAPPED; |
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} |
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static void jz4740_mmc_post_request(struct mmc_host *mmc, |
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struct mmc_request *mrq, |
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int err) |
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{ |
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struct jz4740_mmc_host *host = mmc_priv(mmc); |
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struct mmc_data *data = mrq->data; |
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if (data && data->host_cookie != COOKIE_UNMAPPED) |
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jz4740_mmc_dma_unmap(host, data); |
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|
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if (err) { |
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struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data); |
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|
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dmaengine_terminate_all(chan); |
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} |
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} |
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|
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/*----------------------------------------------------------------------------*/ |
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|
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static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host, |
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unsigned int irq, bool enabled) |
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{ |
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unsigned long flags; |
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|
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spin_lock_irqsave(&host->lock, flags); |
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if (enabled) |
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host->irq_mask &= ~irq; |
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else |
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host->irq_mask |= irq; |
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|
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jz4740_mmc_write_irq_mask(host, host->irq_mask); |
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spin_unlock_irqrestore(&host->lock, flags); |
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} |
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|
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static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, |
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bool start_transfer) |
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{ |
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uint16_t val = JZ_MMC_STRPCL_CLOCK_START; |
|
|
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if (start_transfer) |
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val |= JZ_MMC_STRPCL_START_OP; |
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|
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writew(val, host->base + JZ_REG_MMC_STRPCL); |
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} |
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|
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static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host) |
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{ |
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uint32_t status; |
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unsigned int timeout = 1000; |
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|
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writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL); |
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do { |
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status = readl(host->base + JZ_REG_MMC_STATUS); |
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} while (status & JZ_MMC_STATUS_CLK_EN && --timeout); |
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} |
|
|
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static void jz4740_mmc_reset(struct jz4740_mmc_host *host) |
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{ |
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uint32_t status; |
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unsigned int timeout = 1000; |
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|
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writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL); |
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udelay(10); |
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do { |
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status = readl(host->base + JZ_REG_MMC_STATUS); |
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} while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout); |
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} |
|
|
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static void jz4740_mmc_request_done(struct jz4740_mmc_host *host) |
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{ |
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struct mmc_request *req; |
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struct mmc_data *data; |
|
|
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req = host->req; |
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data = req->data; |
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host->req = NULL; |
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|
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if (data && data->host_cookie == COOKIE_MAPPED) |
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jz4740_mmc_dma_unmap(host, data); |
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mmc_request_done(host->mmc, req); |
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} |
|
|
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static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host, |
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unsigned int irq) |
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{ |
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unsigned int timeout = 0x800; |
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uint32_t status; |
|
|
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do { |
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status = jz4740_mmc_read_irq_reg(host); |
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} while (!(status & irq) && --timeout); |
|
|
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if (timeout == 0) { |
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set_bit(0, &host->waiting); |
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mod_timer(&host->timeout_timer, |
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jiffies + msecs_to_jiffies(JZ_MMC_REQ_TIMEOUT_MS)); |
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jz4740_mmc_set_irq_enabled(host, irq, true); |
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return true; |
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} |
|
|
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return false; |
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} |
|
|
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static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host, |
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struct mmc_data *data) |
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{ |
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int status; |
|
|
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status = readl(host->base + JZ_REG_MMC_STATUS); |
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if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) { |
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if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) { |
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host->req->cmd->error = -ETIMEDOUT; |
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data->error = -ETIMEDOUT; |
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} else { |
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host->req->cmd->error = -EIO; |
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data->error = -EIO; |
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} |
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} else if (status & JZ_MMC_STATUS_READ_ERROR_MASK) { |
|
if (status & (JZ_MMC_STATUS_TIMEOUT_READ)) { |
|
host->req->cmd->error = -ETIMEDOUT; |
|
data->error = -ETIMEDOUT; |
|
} else { |
|
host->req->cmd->error = -EIO; |
|
data->error = -EIO; |
|
} |
|
} |
|
} |
|
|
|
static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host, |
|
struct mmc_data *data) |
|
{ |
|
struct sg_mapping_iter *miter = &host->miter; |
|
void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO; |
|
uint32_t *buf; |
|
bool timeout; |
|
size_t i, j; |
|
|
|
while (sg_miter_next(miter)) { |
|
buf = miter->addr; |
|
i = miter->length / 4; |
|
j = i / 8; |
|
i = i & 0x7; |
|
while (j) { |
|
timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); |
|
if (unlikely(timeout)) |
|
goto poll_timeout; |
|
|
|
writel(buf[0], fifo_addr); |
|
writel(buf[1], fifo_addr); |
|
writel(buf[2], fifo_addr); |
|
writel(buf[3], fifo_addr); |
|
writel(buf[4], fifo_addr); |
|
writel(buf[5], fifo_addr); |
|
writel(buf[6], fifo_addr); |
|
writel(buf[7], fifo_addr); |
|
buf += 8; |
|
--j; |
|
} |
|
if (unlikely(i)) { |
|
timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); |
|
if (unlikely(timeout)) |
|
goto poll_timeout; |
|
|
|
while (i) { |
|
writel(*buf, fifo_addr); |
|
++buf; |
|
--i; |
|
} |
|
} |
|
data->bytes_xfered += miter->length; |
|
} |
|
sg_miter_stop(miter); |
|
|
|
return false; |
|
|
|
poll_timeout: |
|
miter->consumed = (void *)buf - miter->addr; |
|
data->bytes_xfered += miter->consumed; |
|
sg_miter_stop(miter); |
|
|
|
return true; |
|
} |
|
|
|
static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host, |
|
struct mmc_data *data) |
|
{ |
|
struct sg_mapping_iter *miter = &host->miter; |
|
void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO; |
|
uint32_t *buf; |
|
uint32_t d; |
|
uint32_t status; |
|
size_t i, j; |
|
unsigned int timeout; |
|
|
|
while (sg_miter_next(miter)) { |
|
buf = miter->addr; |
|
i = miter->length; |
|
j = i / 32; |
|
i = i & 0x1f; |
|
while (j) { |
|
timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); |
|
if (unlikely(timeout)) |
|
goto poll_timeout; |
|
|
|
buf[0] = readl(fifo_addr); |
|
buf[1] = readl(fifo_addr); |
|
buf[2] = readl(fifo_addr); |
|
buf[3] = readl(fifo_addr); |
|
buf[4] = readl(fifo_addr); |
|
buf[5] = readl(fifo_addr); |
|
buf[6] = readl(fifo_addr); |
|
buf[7] = readl(fifo_addr); |
|
|
|
buf += 8; |
|
--j; |
|
} |
|
|
|
if (unlikely(i)) { |
|
timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); |
|
if (unlikely(timeout)) |
|
goto poll_timeout; |
|
|
|
while (i >= 4) { |
|
*buf++ = readl(fifo_addr); |
|
i -= 4; |
|
} |
|
if (unlikely(i > 0)) { |
|
d = readl(fifo_addr); |
|
memcpy(buf, &d, i); |
|
} |
|
} |
|
data->bytes_xfered += miter->length; |
|
} |
|
sg_miter_stop(miter); |
|
|
|
/* For whatever reason there is sometime one word more in the fifo then |
|
* requested */ |
|
timeout = 1000; |
|
status = readl(host->base + JZ_REG_MMC_STATUS); |
|
while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) { |
|
d = readl(fifo_addr); |
|
status = readl(host->base + JZ_REG_MMC_STATUS); |
|
} |
|
|
|
return false; |
|
|
|
poll_timeout: |
|
miter->consumed = (void *)buf - miter->addr; |
|
data->bytes_xfered += miter->consumed; |
|
sg_miter_stop(miter); |
|
|
|
return true; |
|
} |
|
|
|
static void jz4740_mmc_timeout(struct timer_list *t) |
|
{ |
|
struct jz4740_mmc_host *host = from_timer(host, t, timeout_timer); |
|
|
|
if (!test_and_clear_bit(0, &host->waiting)) |
|
return; |
|
|
|
jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false); |
|
|
|
host->req->cmd->error = -ETIMEDOUT; |
|
jz4740_mmc_request_done(host); |
|
} |
|
|
|
static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, |
|
struct mmc_command *cmd) |
|
{ |
|
int i; |
|
uint16_t tmp; |
|
void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO; |
|
|
|
if (cmd->flags & MMC_RSP_136) { |
|
tmp = readw(fifo_addr); |
|
for (i = 0; i < 4; ++i) { |
|
cmd->resp[i] = tmp << 24; |
|
tmp = readw(fifo_addr); |
|
cmd->resp[i] |= tmp << 8; |
|
tmp = readw(fifo_addr); |
|
cmd->resp[i] |= tmp >> 8; |
|
} |
|
} else { |
|
cmd->resp[0] = readw(fifo_addr) << 24; |
|
cmd->resp[0] |= readw(fifo_addr) << 8; |
|
cmd->resp[0] |= readw(fifo_addr) & 0xff; |
|
} |
|
} |
|
|
|
static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, |
|
struct mmc_command *cmd) |
|
{ |
|
uint32_t cmdat = host->cmdat; |
|
|
|
host->cmdat &= ~JZ_MMC_CMDAT_INIT; |
|
jz4740_mmc_clock_disable(host); |
|
|
|
host->cmd = cmd; |
|
|
|
if (cmd->flags & MMC_RSP_BUSY) |
|
cmdat |= JZ_MMC_CMDAT_BUSY; |
|
|
|
switch (mmc_resp_type(cmd)) { |
|
case MMC_RSP_R1B: |
|
case MMC_RSP_R1: |
|
cmdat |= JZ_MMC_CMDAT_RSP_R1; |
|
break; |
|
case MMC_RSP_R2: |
|
cmdat |= JZ_MMC_CMDAT_RSP_R2; |
|
break; |
|
case MMC_RSP_R3: |
|
cmdat |= JZ_MMC_CMDAT_RSP_R3; |
|
break; |
|
default: |
|
break; |
|
} |
|
|
|
if (cmd->data) { |
|
cmdat |= JZ_MMC_CMDAT_DATA_EN; |
|
if (cmd->data->flags & MMC_DATA_WRITE) |
|
cmdat |= JZ_MMC_CMDAT_WRITE; |
|
if (host->use_dma) { |
|
/* |
|
* The JZ4780's MMC controller has integrated DMA ability |
|
* in addition to being able to use the external DMA |
|
* controller. It moves DMA control bits to a separate |
|
* register. The DMA_SEL bit chooses the external |
|
* controller over the integrated one. Earlier SoCs |
|
* can only use the external controller, and have a |
|
* single DMA enable bit in CMDAT. |
|
*/ |
|
if (host->version >= JZ_MMC_JZ4780) { |
|
writel(JZ_MMC_DMAC_DMA_EN | JZ_MMC_DMAC_DMA_SEL, |
|
host->base + JZ_REG_MMC_DMAC); |
|
} else { |
|
cmdat |= JZ_MMC_CMDAT_DMA_EN; |
|
} |
|
} else if (host->version >= JZ_MMC_JZ4780) { |
|
writel(0, host->base + JZ_REG_MMC_DMAC); |
|
} |
|
|
|
writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN); |
|
writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB); |
|
} |
|
|
|
writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD); |
|
writel(cmd->arg, host->base + JZ_REG_MMC_ARG); |
|
writel(cmdat, host->base + JZ_REG_MMC_CMDAT); |
|
|
|
jz4740_mmc_clock_enable(host, 1); |
|
} |
|
|
|
static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host) |
|
{ |
|
struct mmc_command *cmd = host->req->cmd; |
|
struct mmc_data *data = cmd->data; |
|
int direction; |
|
|
|
if (data->flags & MMC_DATA_READ) |
|
direction = SG_MITER_TO_SG; |
|
else |
|
direction = SG_MITER_FROM_SG; |
|
|
|
sg_miter_start(&host->miter, data->sg, data->sg_len, direction); |
|
} |
|
|
|
|
|
static irqreturn_t jz_mmc_irq_worker(int irq, void *devid) |
|
{ |
|
struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid; |
|
struct mmc_command *cmd = host->req->cmd; |
|
struct mmc_request *req = host->req; |
|
struct mmc_data *data = cmd->data; |
|
bool timeout = false; |
|
|
|
if (cmd->error) |
|
host->state = JZ4740_MMC_STATE_DONE; |
|
|
|
switch (host->state) { |
|
case JZ4740_MMC_STATE_READ_RESPONSE: |
|
if (cmd->flags & MMC_RSP_PRESENT) |
|
jz4740_mmc_read_response(host, cmd); |
|
|
|
if (!data) |
|
break; |
|
|
|
jz_mmc_prepare_data_transfer(host); |
|
fallthrough; |
|
|
|
case JZ4740_MMC_STATE_TRANSFER_DATA: |
|
if (host->use_dma) { |
|
/* Use DMA if enabled. |
|
* Data transfer direction is defined later by |
|
* relying on data flags in |
|
* jz4740_mmc_prepare_dma_data() and |
|
* jz4740_mmc_start_dma_transfer(). |
|
*/ |
|
timeout = jz4740_mmc_start_dma_transfer(host, data); |
|
data->bytes_xfered = data->blocks * data->blksz; |
|
} else if (data->flags & MMC_DATA_READ) |
|
/* Use PIO if DMA is not enabled. |
|
* Data transfer direction was defined before |
|
* by relying on data flags in |
|
* jz_mmc_prepare_data_transfer(). |
|
*/ |
|
timeout = jz4740_mmc_read_data(host, data); |
|
else |
|
timeout = jz4740_mmc_write_data(host, data); |
|
|
|
if (unlikely(timeout)) { |
|
host->state = JZ4740_MMC_STATE_TRANSFER_DATA; |
|
break; |
|
} |
|
|
|
jz4740_mmc_transfer_check_state(host, data); |
|
|
|
timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE); |
|
if (unlikely(timeout)) { |
|
host->state = JZ4740_MMC_STATE_SEND_STOP; |
|
break; |
|
} |
|
jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_DATA_TRAN_DONE); |
|
fallthrough; |
|
|
|
case JZ4740_MMC_STATE_SEND_STOP: |
|
if (!req->stop) |
|
break; |
|
|
|
jz4740_mmc_send_command(host, req->stop); |
|
|
|
if (mmc_resp_type(req->stop) & MMC_RSP_BUSY) { |
|
timeout = jz4740_mmc_poll_irq(host, |
|
JZ_MMC_IRQ_PRG_DONE); |
|
if (timeout) { |
|
host->state = JZ4740_MMC_STATE_DONE; |
|
break; |
|
} |
|
} |
|
fallthrough; |
|
|
|
case JZ4740_MMC_STATE_DONE: |
|
break; |
|
} |
|
|
|
if (!timeout) |
|
jz4740_mmc_request_done(host); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static irqreturn_t jz_mmc_irq(int irq, void *devid) |
|
{ |
|
struct jz4740_mmc_host *host = devid; |
|
struct mmc_command *cmd = host->cmd; |
|
uint32_t irq_reg, status, tmp; |
|
|
|
status = readl(host->base + JZ_REG_MMC_STATUS); |
|
irq_reg = jz4740_mmc_read_irq_reg(host); |
|
|
|
tmp = irq_reg; |
|
irq_reg &= ~host->irq_mask; |
|
|
|
tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ | |
|
JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE); |
|
|
|
if (tmp != irq_reg) |
|
jz4740_mmc_write_irq_reg(host, tmp & ~irq_reg); |
|
|
|
if (irq_reg & JZ_MMC_IRQ_SDIO) { |
|
jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_SDIO); |
|
mmc_signal_sdio_irq(host->mmc); |
|
irq_reg &= ~JZ_MMC_IRQ_SDIO; |
|
} |
|
|
|
if (host->req && cmd && irq_reg) { |
|
if (test_and_clear_bit(0, &host->waiting)) { |
|
del_timer(&host->timeout_timer); |
|
|
|
if (status & JZ_MMC_STATUS_TIMEOUT_RES) { |
|
cmd->error = -ETIMEDOUT; |
|
} else if (status & JZ_MMC_STATUS_CRC_RES_ERR) { |
|
cmd->error = -EIO; |
|
} else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | |
|
JZ_MMC_STATUS_CRC_WRITE_ERROR)) { |
|
if (cmd->data) |
|
cmd->data->error = -EIO; |
|
cmd->error = -EIO; |
|
} |
|
|
|
jz4740_mmc_set_irq_enabled(host, irq_reg, false); |
|
jz4740_mmc_write_irq_reg(host, irq_reg); |
|
|
|
return IRQ_WAKE_THREAD; |
|
} |
|
} |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) |
|
{ |
|
int div = 0; |
|
int real_rate; |
|
|
|
jz4740_mmc_clock_disable(host); |
|
clk_set_rate(host->clk, host->mmc->f_max); |
|
|
|
real_rate = clk_get_rate(host->clk); |
|
|
|
while (real_rate > rate && div < 7) { |
|
++div; |
|
real_rate >>= 1; |
|
} |
|
|
|
writew(div, host->base + JZ_REG_MMC_CLKRT); |
|
|
|
if (real_rate > 25000000) { |
|
if (host->version >= JZ_MMC_JZ4780) { |
|
writel(JZ_MMC_LPM_DRV_RISING_QTR_PHASE_DLY | |
|
JZ_MMC_LPM_SMP_RISING_QTR_OR_HALF_PHASE_DLY | |
|
JZ_MMC_LPM_LOW_POWER_MODE_EN, |
|
host->base + JZ_REG_MMC_LPM); |
|
} else if (host->version >= JZ_MMC_JZ4760) { |
|
writel(JZ_MMC_LPM_DRV_RISING | |
|
JZ_MMC_LPM_LOW_POWER_MODE_EN, |
|
host->base + JZ_REG_MMC_LPM); |
|
} else if (host->version >= JZ_MMC_JZ4725B) |
|
writel(JZ_MMC_LPM_LOW_POWER_MODE_EN, |
|
host->base + JZ_REG_MMC_LPM); |
|
} |
|
|
|
return real_rate; |
|
} |
|
|
|
static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req) |
|
{ |
|
struct jz4740_mmc_host *host = mmc_priv(mmc); |
|
|
|
host->req = req; |
|
|
|
jz4740_mmc_write_irq_reg(host, ~0); |
|
jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true); |
|
|
|
host->state = JZ4740_MMC_STATE_READ_RESPONSE; |
|
set_bit(0, &host->waiting); |
|
mod_timer(&host->timeout_timer, |
|
jiffies + msecs_to_jiffies(JZ_MMC_REQ_TIMEOUT_MS)); |
|
jz4740_mmc_send_command(host, req->cmd); |
|
} |
|
|
|
static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
|
{ |
|
struct jz4740_mmc_host *host = mmc_priv(mmc); |
|
if (ios->clock) |
|
jz4740_mmc_set_clock_rate(host, ios->clock); |
|
|
|
switch (ios->power_mode) { |
|
case MMC_POWER_UP: |
|
jz4740_mmc_reset(host); |
|
if (!IS_ERR(mmc->supply.vmmc)) |
|
mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); |
|
host->cmdat |= JZ_MMC_CMDAT_INIT; |
|
clk_prepare_enable(host->clk); |
|
break; |
|
case MMC_POWER_ON: |
|
break; |
|
default: |
|
if (!IS_ERR(mmc->supply.vmmc)) |
|
mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); |
|
clk_disable_unprepare(host->clk); |
|
break; |
|
} |
|
|
|
switch (ios->bus_width) { |
|
case MMC_BUS_WIDTH_1: |
|
host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK; |
|
break; |
|
case MMC_BUS_WIDTH_4: |
|
host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK; |
|
host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT; |
|
break; |
|
case MMC_BUS_WIDTH_8: |
|
host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK; |
|
host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_8BIT; |
|
break; |
|
default: |
|
break; |
|
} |
|
} |
|
|
|
static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) |
|
{ |
|
struct jz4740_mmc_host *host = mmc_priv(mmc); |
|
jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable); |
|
} |
|
|
|
static const struct mmc_host_ops jz4740_mmc_ops = { |
|
.request = jz4740_mmc_request, |
|
.pre_req = jz4740_mmc_pre_request, |
|
.post_req = jz4740_mmc_post_request, |
|
.set_ios = jz4740_mmc_set_ios, |
|
.get_ro = mmc_gpio_get_ro, |
|
.get_cd = mmc_gpio_get_cd, |
|
.enable_sdio_irq = jz4740_mmc_enable_sdio_irq, |
|
}; |
|
|
|
static const struct of_device_id jz4740_mmc_of_match[] = { |
|
{ .compatible = "ingenic,jz4740-mmc", .data = (void *) JZ_MMC_JZ4740 }, |
|
{ .compatible = "ingenic,jz4725b-mmc", .data = (void *)JZ_MMC_JZ4725B }, |
|
{ .compatible = "ingenic,jz4760-mmc", .data = (void *) JZ_MMC_JZ4760 }, |
|
{ .compatible = "ingenic,jz4775-mmc", .data = (void *) JZ_MMC_JZ4780 }, |
|
{ .compatible = "ingenic,jz4780-mmc", .data = (void *) JZ_MMC_JZ4780 }, |
|
{ .compatible = "ingenic,x1000-mmc", .data = (void *) JZ_MMC_X1000 }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, jz4740_mmc_of_match); |
|
|
|
static int jz4740_mmc_probe(struct platform_device* pdev) |
|
{ |
|
int ret; |
|
struct mmc_host *mmc; |
|
struct jz4740_mmc_host *host; |
|
const struct of_device_id *match; |
|
|
|
mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev); |
|
if (!mmc) { |
|
dev_err(&pdev->dev, "Failed to alloc mmc host structure\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
host = mmc_priv(mmc); |
|
|
|
match = of_match_device(jz4740_mmc_of_match, &pdev->dev); |
|
if (match) { |
|
host->version = (enum jz4740_mmc_version)match->data; |
|
} else { |
|
/* JZ4740 should be the only one using legacy probe */ |
|
host->version = JZ_MMC_JZ4740; |
|
} |
|
|
|
ret = mmc_of_parse(mmc); |
|
if (ret) { |
|
dev_err_probe(&pdev->dev, ret, "could not parse device properties\n"); |
|
goto err_free_host; |
|
} |
|
|
|
mmc_regulator_get_supply(mmc); |
|
|
|
host->irq = platform_get_irq(pdev, 0); |
|
if (host->irq < 0) { |
|
ret = host->irq; |
|
goto err_free_host; |
|
} |
|
|
|
host->clk = devm_clk_get(&pdev->dev, "mmc"); |
|
if (IS_ERR(host->clk)) { |
|
ret = PTR_ERR(host->clk); |
|
dev_err(&pdev->dev, "Failed to get mmc clock\n"); |
|
goto err_free_host; |
|
} |
|
|
|
host->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
host->base = devm_ioremap_resource(&pdev->dev, host->mem_res); |
|
if (IS_ERR(host->base)) { |
|
ret = PTR_ERR(host->base); |
|
goto err_free_host; |
|
} |
|
|
|
mmc->ops = &jz4740_mmc_ops; |
|
if (!mmc->f_max) |
|
mmc->f_max = JZ_MMC_CLK_RATE; |
|
mmc->f_min = mmc->f_max / 128; |
|
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; |
|
|
|
/* |
|
* We use a fixed timeout of 5s, hence inform the core about it. A |
|
* future improvement should instead respect the cmd->busy_timeout. |
|
*/ |
|
mmc->max_busy_timeout = JZ_MMC_REQ_TIMEOUT_MS; |
|
|
|
mmc->max_blk_size = (1 << 10) - 1; |
|
mmc->max_blk_count = (1 << 15) - 1; |
|
mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; |
|
|
|
mmc->max_segs = 128; |
|
mmc->max_seg_size = mmc->max_req_size; |
|
|
|
host->mmc = mmc; |
|
host->pdev = pdev; |
|
spin_lock_init(&host->lock); |
|
host->irq_mask = ~0; |
|
|
|
jz4740_mmc_reset(host); |
|
|
|
ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0, |
|
dev_name(&pdev->dev), host); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); |
|
goto err_free_host; |
|
} |
|
|
|
jz4740_mmc_clock_disable(host); |
|
timer_setup(&host->timeout_timer, jz4740_mmc_timeout, 0); |
|
|
|
ret = jz4740_mmc_acquire_dma_channels(host); |
|
if (ret == -EPROBE_DEFER) |
|
goto err_free_irq; |
|
host->use_dma = !ret; |
|
|
|
platform_set_drvdata(pdev, host); |
|
ret = mmc_add_host(mmc); |
|
|
|
if (ret) { |
|
dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret); |
|
goto err_release_dma; |
|
} |
|
dev_info(&pdev->dev, "Ingenic SD/MMC card driver registered\n"); |
|
|
|
dev_info(&pdev->dev, "Using %s, %d-bit mode\n", |
|
host->use_dma ? "DMA" : "PIO", |
|
(mmc->caps & MMC_CAP_8_BIT_DATA) ? 8 : |
|
((mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1)); |
|
|
|
return 0; |
|
|
|
err_release_dma: |
|
if (host->use_dma) |
|
jz4740_mmc_release_dma_channels(host); |
|
err_free_irq: |
|
free_irq(host->irq, host); |
|
err_free_host: |
|
mmc_free_host(mmc); |
|
|
|
return ret; |
|
} |
|
|
|
static int jz4740_mmc_remove(struct platform_device *pdev) |
|
{ |
|
struct jz4740_mmc_host *host = platform_get_drvdata(pdev); |
|
|
|
del_timer_sync(&host->timeout_timer); |
|
jz4740_mmc_set_irq_enabled(host, 0xff, false); |
|
jz4740_mmc_reset(host); |
|
|
|
mmc_remove_host(host->mmc); |
|
|
|
free_irq(host->irq, host); |
|
|
|
if (host->use_dma) |
|
jz4740_mmc_release_dma_channels(host); |
|
|
|
mmc_free_host(host->mmc); |
|
|
|
return 0; |
|
} |
|
|
|
static int jz4740_mmc_suspend(struct device *dev) |
|
{ |
|
return pinctrl_pm_select_sleep_state(dev); |
|
} |
|
|
|
static int jz4740_mmc_resume(struct device *dev) |
|
{ |
|
return pinctrl_select_default_state(dev); |
|
} |
|
|
|
static DEFINE_SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend, |
|
jz4740_mmc_resume); |
|
|
|
static struct platform_driver jz4740_mmc_driver = { |
|
.probe = jz4740_mmc_probe, |
|
.remove = jz4740_mmc_remove, |
|
.driver = { |
|
.name = "jz4740-mmc", |
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS, |
|
.of_match_table = of_match_ptr(jz4740_mmc_of_match), |
|
.pm = pm_sleep_ptr(&jz4740_mmc_pm_ops), |
|
}, |
|
}; |
|
|
|
module_platform_driver(jz4740_mmc_driver); |
|
|
|
MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
|
|
|