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589 lines
19 KiB
589 lines
19 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Synopsys DesignWare Multimedia Card Interface driver |
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* (Based on NXP driver for lpc 31xx) |
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* |
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* Copyright (C) 2009 NXP Semiconductors |
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* Copyright (C) 2009, 2010 Imagination Technologies Ltd. |
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*/ |
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#ifndef _DW_MMC_H_ |
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#define _DW_MMC_H_ |
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#include <linux/scatterlist.h> |
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#include <linux/mmc/core.h> |
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#include <linux/dmaengine.h> |
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#include <linux/reset.h> |
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#include <linux/fault-inject.h> |
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#include <linux/hrtimer.h> |
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#include <linux/interrupt.h> |
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enum dw_mci_state { |
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STATE_IDLE = 0, |
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STATE_SENDING_CMD, |
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STATE_SENDING_DATA, |
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STATE_DATA_BUSY, |
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STATE_SENDING_STOP, |
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STATE_DATA_ERROR, |
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STATE_SENDING_CMD11, |
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STATE_WAITING_CMD11_DONE, |
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}; |
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enum { |
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EVENT_CMD_COMPLETE = 0, |
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EVENT_XFER_COMPLETE, |
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EVENT_DATA_COMPLETE, |
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EVENT_DATA_ERROR, |
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}; |
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enum dw_mci_cookie { |
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COOKIE_UNMAPPED, |
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COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */ |
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COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */ |
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}; |
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struct mmc_data; |
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enum { |
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TRANS_MODE_PIO = 0, |
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TRANS_MODE_IDMAC, |
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TRANS_MODE_EDMAC |
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}; |
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struct dw_mci_dma_slave { |
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struct dma_chan *ch; |
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enum dma_transfer_direction direction; |
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}; |
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/** |
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* struct dw_mci - MMC controller state shared between all slots |
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* @lock: Spinlock protecting the queue and associated data. |
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* @irq_lock: Spinlock protecting the INTMASK setting. |
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* @regs: Pointer to MMIO registers. |
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* @fifo_reg: Pointer to MMIO registers for data FIFO |
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* @sg: Scatterlist entry currently being processed by PIO code, if any. |
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* @sg_miter: PIO mapping scatterlist iterator. |
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* @mrq: The request currently being processed on @slot, |
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* or NULL if the controller is idle. |
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* @cmd: The command currently being sent to the card, or NULL. |
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* @data: The data currently being transferred, or NULL if no data |
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* transfer is in progress. |
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* @stop_abort: The command currently prepared for stoping transfer. |
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* @prev_blksz: The former transfer blksz record. |
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* @timing: Record of current ios timing. |
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* @use_dma: Which DMA channel is in use for the current transfer, zero |
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* denotes PIO mode. |
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* @using_dma: Whether DMA is in use for the current transfer. |
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* @dma_64bit_address: Whether DMA supports 64-bit address mode or not. |
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* @sg_dma: Bus address of DMA buffer. |
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* @sg_cpu: Virtual address of DMA buffer. |
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* @dma_ops: Pointer to platform-specific DMA callbacks. |
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* @cmd_status: Snapshot of SR taken upon completion of the current |
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* @ring_size: Buffer size for idma descriptors. |
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* command. Only valid when EVENT_CMD_COMPLETE is pending. |
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* @dms: structure of slave-dma private data. |
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* @phy_regs: physical address of controller's register map |
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* @data_status: Snapshot of SR taken upon completion of the current |
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* data transfer. Only valid when EVENT_DATA_COMPLETE or |
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* EVENT_DATA_ERROR is pending. |
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* @stop_cmdr: Value to be loaded into CMDR when the stop command is |
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* to be sent. |
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* @dir_status: Direction of current transfer. |
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* @tasklet: Tasklet running the request state machine. |
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* @pending_events: Bitmask of events flagged by the interrupt handler |
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* to be processed by the tasklet. |
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* @completed_events: Bitmask of events which the state machine has |
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* processed. |
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* @state: Tasklet state. |
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* @queue: List of slots waiting for access to the controller. |
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* @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus |
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* rate and timeout calculations. |
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* @current_speed: Configured rate of the controller. |
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* @minimum_speed: Stored minimum rate of the controller. |
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* @fifoth_val: The value of FIFOTH register. |
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* @verid: Denote Version ID. |
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* @dev: Device associated with the MMC controller. |
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* @pdata: Platform data associated with the MMC controller. |
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* @drv_data: Driver specific data for identified variant of the controller |
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* @priv: Implementation defined private data. |
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* @biu_clk: Pointer to bus interface unit clock instance. |
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* @ciu_clk: Pointer to card interface unit clock instance. |
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* @slot: Slots sharing this MMC controller. |
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* @fifo_depth: depth of FIFO. |
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* @data_addr_override: override fifo reg offset with this value. |
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* @wm_aligned: force fifo watermark equal with data length in PIO mode. |
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* Set as true if alignment is needed. |
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* @data_shift: log2 of FIFO item size. |
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* @part_buf_start: Start index in part_buf. |
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* @part_buf_count: Bytes of partial data in part_buf. |
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* @part_buf: Simple buffer for partial fifo reads/writes. |
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* @push_data: Pointer to FIFO push function. |
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* @pull_data: Pointer to FIFO pull function. |
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* @quirks: Set of quirks that apply to specific versions of the IP. |
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* @vqmmc_enabled: Status of vqmmc, should be true or false. |
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* @irq_flags: The flags to be passed to request_irq. |
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* @irq: The irq value to be passed to request_irq. |
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* @sdio_id0: Number of slot0 in the SDIO interrupt registers. |
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* @cmd11_timer: Timer for SD3.0 voltage switch over scheme. |
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* @cto_timer: Timer for broken command transfer over scheme. |
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* @dto_timer: Timer for broken data transfer over scheme. |
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* |
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* Locking |
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* ======= |
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* |
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* @lock is a softirq-safe spinlock protecting @queue as well as |
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* @slot, @mrq and @state. These must always be updated |
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* at the same time while holding @lock. |
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* The @mrq field of struct dw_mci_slot is also protected by @lock, |
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* and must always be written at the same time as the slot is added to |
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* @queue. |
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* |
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* @irq_lock is an irq-safe spinlock protecting the INTMASK register |
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* to allow the interrupt handler to modify it directly. Held for only long |
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* enough to read-modify-write INTMASK and no other locks are grabbed when |
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* holding this one. |
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* |
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* @pending_events and @completed_events are accessed using atomic bit |
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* operations, so they don't need any locking. |
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* |
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* None of the fields touched by the interrupt handler need any |
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* locking. However, ordering is important: Before EVENT_DATA_ERROR or |
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* EVENT_DATA_COMPLETE is set in @pending_events, all data-related |
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* interrupts must be disabled and @data_status updated with a |
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* snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the |
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* CMDRDY interrupt must be disabled and @cmd_status updated with a |
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* snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the |
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* bytes_xfered field of @data must be written. This is ensured by |
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* using barriers. |
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*/ |
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struct dw_mci { |
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spinlock_t lock; |
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spinlock_t irq_lock; |
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void __iomem *regs; |
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void __iomem *fifo_reg; |
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u32 data_addr_override; |
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bool wm_aligned; |
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struct scatterlist *sg; |
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struct sg_mapping_iter sg_miter; |
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struct mmc_request *mrq; |
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struct mmc_command *cmd; |
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struct mmc_data *data; |
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struct mmc_command stop_abort; |
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unsigned int prev_blksz; |
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unsigned char timing; |
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/* DMA interface members*/ |
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int use_dma; |
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int using_dma; |
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int dma_64bit_address; |
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dma_addr_t sg_dma; |
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void *sg_cpu; |
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const struct dw_mci_dma_ops *dma_ops; |
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/* For idmac */ |
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unsigned int ring_size; |
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/* For edmac */ |
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struct dw_mci_dma_slave *dms; |
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/* Registers's physical base address */ |
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resource_size_t phy_regs; |
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u32 cmd_status; |
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u32 data_status; |
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u32 stop_cmdr; |
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u32 dir_status; |
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struct tasklet_struct tasklet; |
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unsigned long pending_events; |
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unsigned long completed_events; |
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enum dw_mci_state state; |
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struct list_head queue; |
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u32 bus_hz; |
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u32 current_speed; |
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u32 minimum_speed; |
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u32 fifoth_val; |
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u16 verid; |
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struct device *dev; |
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struct dw_mci_board *pdata; |
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const struct dw_mci_drv_data *drv_data; |
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void *priv; |
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struct clk *biu_clk; |
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struct clk *ciu_clk; |
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struct dw_mci_slot *slot; |
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/* FIFO push and pull */ |
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int fifo_depth; |
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int data_shift; |
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u8 part_buf_start; |
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u8 part_buf_count; |
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union { |
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u16 part_buf16; |
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u32 part_buf32; |
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u64 part_buf; |
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}; |
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void (*push_data)(struct dw_mci *host, void *buf, int cnt); |
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void (*pull_data)(struct dw_mci *host, void *buf, int cnt); |
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u32 quirks; |
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bool vqmmc_enabled; |
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unsigned long irq_flags; /* IRQ flags */ |
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int irq; |
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int sdio_id0; |
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struct timer_list cmd11_timer; |
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struct timer_list cto_timer; |
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struct timer_list dto_timer; |
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#ifdef CONFIG_FAULT_INJECTION |
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struct fault_attr fail_data_crc; |
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struct hrtimer fault_timer; |
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#endif |
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}; |
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/* DMA ops for Internal/External DMAC interface */ |
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struct dw_mci_dma_ops { |
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/* DMA Ops */ |
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int (*init)(struct dw_mci *host); |
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int (*start)(struct dw_mci *host, unsigned int sg_len); |
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void (*complete)(void *host); |
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void (*stop)(struct dw_mci *host); |
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void (*cleanup)(struct dw_mci *host); |
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void (*exit)(struct dw_mci *host); |
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}; |
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struct dma_pdata; |
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/* Board platform data */ |
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struct dw_mci_board { |
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unsigned int bus_hz; /* Clock speed at the cclk_in pad */ |
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u32 caps; /* Capabilities */ |
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u32 caps2; /* More capabilities */ |
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u32 pm_caps; /* PM capabilities */ |
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/* |
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* Override fifo depth. If 0, autodetect it from the FIFOTH register, |
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* but note that this may not be reliable after a bootloader has used |
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* it. |
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*/ |
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unsigned int fifo_depth; |
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/* delay in mS before detecting cards after interrupt */ |
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u32 detect_delay_ms; |
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struct reset_control *rstc; |
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struct dw_mci_dma_ops *dma_ops; |
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struct dma_pdata *data; |
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}; |
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/* Support for longer data read timeout */ |
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#define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0) |
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#define DW_MMC_240A 0x240a |
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#define DW_MMC_280A 0x280a |
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#define SDMMC_CTRL 0x000 |
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#define SDMMC_PWREN 0x004 |
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#define SDMMC_CLKDIV 0x008 |
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#define SDMMC_CLKSRC 0x00c |
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#define SDMMC_CLKENA 0x010 |
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#define SDMMC_TMOUT 0x014 |
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#define SDMMC_CTYPE 0x018 |
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#define SDMMC_BLKSIZ 0x01c |
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#define SDMMC_BYTCNT 0x020 |
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#define SDMMC_INTMASK 0x024 |
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#define SDMMC_CMDARG 0x028 |
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#define SDMMC_CMD 0x02c |
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#define SDMMC_RESP0 0x030 |
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#define SDMMC_RESP1 0x034 |
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#define SDMMC_RESP2 0x038 |
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#define SDMMC_RESP3 0x03c |
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#define SDMMC_MINTSTS 0x040 |
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#define SDMMC_RINTSTS 0x044 |
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#define SDMMC_STATUS 0x048 |
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#define SDMMC_FIFOTH 0x04c |
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#define SDMMC_CDETECT 0x050 |
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#define SDMMC_WRTPRT 0x054 |
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#define SDMMC_GPIO 0x058 |
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#define SDMMC_TCBCNT 0x05c |
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#define SDMMC_TBBCNT 0x060 |
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#define SDMMC_DEBNCE 0x064 |
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#define SDMMC_USRID 0x068 |
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#define SDMMC_VERID 0x06c |
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#define SDMMC_HCON 0x070 |
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#define SDMMC_UHS_REG 0x074 |
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#define SDMMC_RST_N 0x078 |
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#define SDMMC_BMOD 0x080 |
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#define SDMMC_PLDMND 0x084 |
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#define SDMMC_DBADDR 0x088 |
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#define SDMMC_IDSTS 0x08c |
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#define SDMMC_IDINTEN 0x090 |
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#define SDMMC_DSCADDR 0x094 |
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#define SDMMC_BUFADDR 0x098 |
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#define SDMMC_CDTHRCTL 0x100 |
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#define SDMMC_UHS_REG_EXT 0x108 |
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#define SDMMC_DDR_REG 0x10c |
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#define SDMMC_ENABLE_SHIFT 0x110 |
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#define SDMMC_DATA(x) (x) |
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/* |
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* Registers to support idmac 64-bit address mode |
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*/ |
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#define SDMMC_DBADDRL 0x088 |
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#define SDMMC_DBADDRU 0x08c |
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#define SDMMC_IDSTS64 0x090 |
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#define SDMMC_IDINTEN64 0x094 |
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#define SDMMC_DSCADDRL 0x098 |
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#define SDMMC_DSCADDRU 0x09c |
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#define SDMMC_BUFADDRL 0x0A0 |
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#define SDMMC_BUFADDRU 0x0A4 |
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/* |
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* Data offset is difference according to Version |
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* Lower than 2.40a : data register offest is 0x100 |
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*/ |
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#define DATA_OFFSET 0x100 |
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#define DATA_240A_OFFSET 0x200 |
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/* shift bit field */ |
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#define _SBF(f, v) ((v) << (f)) |
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/* Control register defines */ |
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#define SDMMC_CTRL_USE_IDMAC BIT(25) |
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#define SDMMC_CTRL_CEATA_INT_EN BIT(11) |
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#define SDMMC_CTRL_SEND_AS_CCSD BIT(10) |
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#define SDMMC_CTRL_SEND_CCSD BIT(9) |
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#define SDMMC_CTRL_ABRT_READ_DATA BIT(8) |
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#define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) |
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#define SDMMC_CTRL_READ_WAIT BIT(6) |
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#define SDMMC_CTRL_DMA_ENABLE BIT(5) |
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#define SDMMC_CTRL_INT_ENABLE BIT(4) |
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#define SDMMC_CTRL_DMA_RESET BIT(2) |
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#define SDMMC_CTRL_FIFO_RESET BIT(1) |
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#define SDMMC_CTRL_RESET BIT(0) |
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/* Clock Enable register defines */ |
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#define SDMMC_CLKEN_LOW_PWR BIT(16) |
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#define SDMMC_CLKEN_ENABLE BIT(0) |
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/* time-out register defines */ |
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#define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) |
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#define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 |
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#define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) |
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#define SDMMC_TMOUT_RESP_MSK 0xFF |
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/* card-type register defines */ |
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#define SDMMC_CTYPE_8BIT BIT(16) |
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#define SDMMC_CTYPE_4BIT BIT(0) |
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#define SDMMC_CTYPE_1BIT 0 |
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/* Interrupt status & mask register defines */ |
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#define SDMMC_INT_SDIO(n) BIT(16 + (n)) |
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#define SDMMC_INT_EBE BIT(15) |
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#define SDMMC_INT_ACD BIT(14) |
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#define SDMMC_INT_SBE BIT(13) |
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#define SDMMC_INT_HLE BIT(12) |
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#define SDMMC_INT_FRUN BIT(11) |
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#define SDMMC_INT_HTO BIT(10) |
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#define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */ |
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#define SDMMC_INT_DRTO BIT(9) |
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#define SDMMC_INT_RTO BIT(8) |
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#define SDMMC_INT_DCRC BIT(7) |
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#define SDMMC_INT_RCRC BIT(6) |
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#define SDMMC_INT_RXDR BIT(5) |
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#define SDMMC_INT_TXDR BIT(4) |
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#define SDMMC_INT_DATA_OVER BIT(3) |
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#define SDMMC_INT_CMD_DONE BIT(2) |
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#define SDMMC_INT_RESP_ERR BIT(1) |
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#define SDMMC_INT_CD BIT(0) |
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#define SDMMC_INT_ERROR 0xbfc2 |
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/* Command register defines */ |
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#define SDMMC_CMD_START BIT(31) |
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#define SDMMC_CMD_USE_HOLD_REG BIT(29) |
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#define SDMMC_CMD_VOLT_SWITCH BIT(28) |
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#define SDMMC_CMD_CCS_EXP BIT(23) |
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#define SDMMC_CMD_CEATA_RD BIT(22) |
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#define SDMMC_CMD_UPD_CLK BIT(21) |
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#define SDMMC_CMD_INIT BIT(15) |
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#define SDMMC_CMD_STOP BIT(14) |
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#define SDMMC_CMD_PRV_DAT_WAIT BIT(13) |
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#define SDMMC_CMD_SEND_STOP BIT(12) |
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#define SDMMC_CMD_STRM_MODE BIT(11) |
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#define SDMMC_CMD_DAT_WR BIT(10) |
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#define SDMMC_CMD_DAT_EXP BIT(9) |
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#define SDMMC_CMD_RESP_CRC BIT(8) |
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#define SDMMC_CMD_RESP_LONG BIT(7) |
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#define SDMMC_CMD_RESP_EXP BIT(6) |
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#define SDMMC_CMD_INDX(n) ((n) & 0x1F) |
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/* Status register defines */ |
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#define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) |
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#define SDMMC_STATUS_DMA_REQ BIT(31) |
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#define SDMMC_STATUS_BUSY BIT(9) |
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/* FIFOTH register defines */ |
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#define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ |
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((r) & 0xFFF) << 16 | \ |
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((t) & 0xFFF)) |
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/* HCON register defines */ |
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#define DMA_INTERFACE_IDMA (0x0) |
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#define DMA_INTERFACE_DWDMA (0x1) |
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#define DMA_INTERFACE_GDMA (0x2) |
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#define DMA_INTERFACE_NODMA (0x3) |
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#define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3) |
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#define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1) |
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#define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7) |
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#define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1) |
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/* Internal DMAC interrupt defines */ |
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#define SDMMC_IDMAC_INT_AI BIT(9) |
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#define SDMMC_IDMAC_INT_NI BIT(8) |
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#define SDMMC_IDMAC_INT_CES BIT(5) |
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#define SDMMC_IDMAC_INT_DU BIT(4) |
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#define SDMMC_IDMAC_INT_FBE BIT(2) |
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#define SDMMC_IDMAC_INT_RI BIT(1) |
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#define SDMMC_IDMAC_INT_TI BIT(0) |
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/* Internal DMAC bus mode bits */ |
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#define SDMMC_IDMAC_ENABLE BIT(7) |
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#define SDMMC_IDMAC_FB BIT(1) |
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#define SDMMC_IDMAC_SWRESET BIT(0) |
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/* H/W reset */ |
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#define SDMMC_RST_HWACTIVE 0x1 |
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/* Version ID register define */ |
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#define SDMMC_GET_VERID(x) ((x) & 0xFFFF) |
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/* Card read threshold */ |
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#define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x)) |
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#define SDMMC_CARD_WR_THR_EN BIT(2) |
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#define SDMMC_CARD_RD_THR_EN BIT(0) |
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/* UHS-1 register defines */ |
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#define SDMMC_UHS_DDR BIT(16) |
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#define SDMMC_UHS_18V BIT(0) |
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/* DDR register defines */ |
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#define SDMMC_DDR_HS400 BIT(31) |
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/* Enable shift register defines */ |
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#define SDMMC_ENABLE_PHASE BIT(0) |
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/* All ctrl reset bits */ |
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#define SDMMC_CTRL_ALL_RESET_FLAGS \ |
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(SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) |
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|
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/* FIFO register access macros. These should not change the data endian-ness |
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* as they are written to memory to be dealt with by the upper layers |
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*/ |
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#define mci_fifo_readw(__reg) __raw_readw(__reg) |
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#define mci_fifo_readl(__reg) __raw_readl(__reg) |
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#define mci_fifo_readq(__reg) __raw_readq(__reg) |
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#define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value) |
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#define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value) |
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#define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value) |
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/* Register access macros */ |
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#define mci_readl(dev, reg) \ |
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readl_relaxed((dev)->regs + SDMMC_##reg) |
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#define mci_writel(dev, reg, value) \ |
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writel_relaxed((value), (dev)->regs + SDMMC_##reg) |
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/* 16-bit FIFO access macros */ |
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#define mci_readw(dev, reg) \ |
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readw_relaxed((dev)->regs + SDMMC_##reg) |
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#define mci_writew(dev, reg, value) \ |
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writew_relaxed((value), (dev)->regs + SDMMC_##reg) |
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|
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/* 64-bit FIFO access macros */ |
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#ifdef readq |
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#define mci_readq(dev, reg) \ |
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readq_relaxed((dev)->regs + SDMMC_##reg) |
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#define mci_writeq(dev, reg, value) \ |
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writeq_relaxed((value), (dev)->regs + SDMMC_##reg) |
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#else |
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/* |
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* Dummy readq implementation for architectures that don't define it. |
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* |
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* We would assume that none of these architectures would configure |
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* the IP block with a 64bit FIFO width, so this code will never be |
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* executed on those machines. Defining these macros here keeps the |
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* rest of the code free from ifdefs. |
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*/ |
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#define mci_readq(dev, reg) \ |
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(*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) |
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#define mci_writeq(dev, reg, value) \ |
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(*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) |
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|
|
#define __raw_writeq(__value, __reg) \ |
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(*(volatile u64 __force *)(__reg) = (__value)) |
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#define __raw_readq(__reg) (*(volatile u64 __force *)(__reg)) |
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#endif |
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|
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extern int dw_mci_probe(struct dw_mci *host); |
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extern void dw_mci_remove(struct dw_mci *host); |
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#ifdef CONFIG_PM |
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extern int dw_mci_runtime_suspend(struct device *device); |
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extern int dw_mci_runtime_resume(struct device *device); |
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#endif |
|
|
|
/** |
|
* struct dw_mci_slot - MMC slot state |
|
* @mmc: The mmc_host representing this slot. |
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* @host: The MMC controller this slot is using. |
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* @ctype: Card type for this slot. |
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* @mrq: mmc_request currently being processed or waiting to be |
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* processed, or NULL when the slot is idle. |
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* @queue_node: List node for placing this node in the @queue list of |
|
* &struct dw_mci. |
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* @clock: Clock rate configured by set_ios(). Protected by host->lock. |
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* @__clk_old: The last clock value that was requested from core. |
|
* Keeping track of this helps us to avoid spamming the console. |
|
* @flags: Random state bits associated with the slot. |
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* @id: Number of this slot. |
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* @sdio_id: Number of this slot in the SDIO interrupt registers. |
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*/ |
|
struct dw_mci_slot { |
|
struct mmc_host *mmc; |
|
struct dw_mci *host; |
|
|
|
u32 ctype; |
|
|
|
struct mmc_request *mrq; |
|
struct list_head queue_node; |
|
|
|
unsigned int clock; |
|
unsigned int __clk_old; |
|
|
|
unsigned long flags; |
|
#define DW_MMC_CARD_PRESENT 0 |
|
#define DW_MMC_CARD_NEED_INIT 1 |
|
#define DW_MMC_CARD_NO_LOW_PWR 2 |
|
#define DW_MMC_CARD_NO_USE_HOLD 3 |
|
#define DW_MMC_CARD_NEEDS_POLL 4 |
|
int id; |
|
int sdio_id; |
|
}; |
|
|
|
/** |
|
* dw_mci driver data - dw-mshc implementation specific driver data. |
|
* @caps: mmc subsystem specified capabilities of the controller(s). |
|
* @num_caps: number of capabilities specified by @caps. |
|
* @common_caps: mmc subsystem specified capabilities applicable to all of |
|
* the controllers |
|
* @init: early implementation specific initialization. |
|
* @set_ios: handle bus specific extensions. |
|
* @parse_dt: parse implementation specific device tree properties. |
|
* @execute_tuning: implementation specific tuning procedure. |
|
* @set_data_timeout: implementation specific timeout. |
|
* @get_drto_clks: implementation specific cycle count for data read timeout. |
|
* |
|
* Provide controller implementation specific extensions. The usage of this |
|
* data structure is fully optional and usage of each member in this structure |
|
* is optional as well. |
|
*/ |
|
struct dw_mci_drv_data { |
|
unsigned long *caps; |
|
u32 num_caps; |
|
u32 common_caps; |
|
int (*init)(struct dw_mci *host); |
|
void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); |
|
int (*parse_dt)(struct dw_mci *host); |
|
int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode); |
|
int (*prepare_hs400_tuning)(struct dw_mci *host, |
|
struct mmc_ios *ios); |
|
int (*switch_voltage)(struct mmc_host *mmc, |
|
struct mmc_ios *ios); |
|
void (*set_data_timeout)(struct dw_mci *host, |
|
unsigned int timeout_ns); |
|
u32 (*get_drto_clks)(struct dw_mci *host); |
|
}; |
|
#endif /* _DW_MMC_H_ */
|
|
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