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324 lines
8.0 KiB
324 lines
8.0 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
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*/ |
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#ifndef LINUX_MMC_CQHCI_H |
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#define LINUX_MMC_CQHCI_H |
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#include <linux/compiler.h> |
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#include <linux/bitops.h> |
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#include <linux/spinlock_types.h> |
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#include <linux/types.h> |
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#include <linux/completion.h> |
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#include <linux/wait.h> |
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#include <linux/irqreturn.h> |
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#include <asm/io.h> |
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/* registers */ |
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/* version */ |
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#define CQHCI_VER 0x00 |
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#define CQHCI_VER_MAJOR(x) (((x) & GENMASK(11, 8)) >> 8) |
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#define CQHCI_VER_MINOR1(x) (((x) & GENMASK(7, 4)) >> 4) |
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#define CQHCI_VER_MINOR2(x) ((x) & GENMASK(3, 0)) |
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/* capabilities */ |
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#define CQHCI_CAP 0x04 |
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#define CQHCI_CAP_CS 0x10000000 /* Crypto Support */ |
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/* configuration */ |
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#define CQHCI_CFG 0x08 |
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#define CQHCI_DCMD 0x00001000 |
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#define CQHCI_TASK_DESC_SZ 0x00000100 |
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#define CQHCI_CRYPTO_GENERAL_ENABLE 0x00000002 |
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#define CQHCI_ENABLE 0x00000001 |
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/* control */ |
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#define CQHCI_CTL 0x0C |
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#define CQHCI_CLEAR_ALL_TASKS 0x00000100 |
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#define CQHCI_HALT 0x00000001 |
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/* interrupt status */ |
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#define CQHCI_IS 0x10 |
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#define CQHCI_IS_HAC BIT(0) |
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#define CQHCI_IS_TCC BIT(1) |
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#define CQHCI_IS_RED BIT(2) |
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#define CQHCI_IS_TCL BIT(3) |
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#define CQHCI_IS_GCE BIT(4) /* General Crypto Error */ |
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#define CQHCI_IS_ICCE BIT(5) /* Invalid Crypto Config Error */ |
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#define CQHCI_IS_MASK (CQHCI_IS_TCC | CQHCI_IS_RED | \ |
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CQHCI_IS_GCE | CQHCI_IS_ICCE) |
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/* interrupt status enable */ |
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#define CQHCI_ISTE 0x14 |
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/* interrupt signal enable */ |
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#define CQHCI_ISGE 0x18 |
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/* interrupt coalescing */ |
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#define CQHCI_IC 0x1C |
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#define CQHCI_IC_ENABLE BIT(31) |
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#define CQHCI_IC_RESET BIT(16) |
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#define CQHCI_IC_ICCTHWEN BIT(15) |
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#define CQHCI_IC_ICCTH(x) (((x) & 0x1F) << 8) |
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#define CQHCI_IC_ICTOVALWEN BIT(7) |
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#define CQHCI_IC_ICTOVAL(x) ((x) & 0x7F) |
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/* task list base address */ |
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#define CQHCI_TDLBA 0x20 |
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/* task list base address upper */ |
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#define CQHCI_TDLBAU 0x24 |
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/* door-bell */ |
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#define CQHCI_TDBR 0x28 |
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/* task completion notification */ |
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#define CQHCI_TCN 0x2C |
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/* device queue status */ |
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#define CQHCI_DQS 0x30 |
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/* device pending tasks */ |
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#define CQHCI_DPT 0x34 |
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/* task clear */ |
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#define CQHCI_TCLR 0x38 |
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/* task descriptor processing error */ |
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#define CQHCI_TDPE 0x3c |
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/* send status config 1 */ |
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#define CQHCI_SSC1 0x40 |
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#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16) |
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/* send status config 2 */ |
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#define CQHCI_SSC2 0x44 |
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/* response for dcmd */ |
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#define CQHCI_CRDCT 0x48 |
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/* response mode error mask */ |
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#define CQHCI_RMEM 0x50 |
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/* task error info */ |
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#define CQHCI_TERRI 0x54 |
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#define CQHCI_TERRI_C_INDEX(x) ((x) & GENMASK(5, 0)) |
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#define CQHCI_TERRI_C_TASK(x) (((x) & GENMASK(12, 8)) >> 8) |
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#define CQHCI_TERRI_C_VALID(x) ((x) & BIT(15)) |
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#define CQHCI_TERRI_D_INDEX(x) (((x) & GENMASK(21, 16)) >> 16) |
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#define CQHCI_TERRI_D_TASK(x) (((x) & GENMASK(28, 24)) >> 24) |
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#define CQHCI_TERRI_D_VALID(x) ((x) & BIT(31)) |
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/* command response index */ |
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#define CQHCI_CRI 0x58 |
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/* command response argument */ |
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#define CQHCI_CRA 0x5C |
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/* crypto capabilities */ |
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#define CQHCI_CCAP 0x100 |
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#define CQHCI_CRYPTOCAP 0x104 |
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#define CQHCI_INT_ALL 0xF |
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#define CQHCI_IC_DEFAULT_ICCTH 31 |
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#define CQHCI_IC_DEFAULT_ICTOVAL 1 |
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/* attribute fields */ |
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#define CQHCI_VALID(x) (((x) & 1) << 0) |
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#define CQHCI_END(x) (((x) & 1) << 1) |
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#define CQHCI_INT(x) (((x) & 1) << 2) |
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#define CQHCI_ACT(x) (((x) & 0x7) << 3) |
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/* data command task descriptor fields */ |
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#define CQHCI_FORCED_PROG(x) (((x) & 1) << 6) |
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#define CQHCI_CONTEXT(x) (((x) & 0xF) << 7) |
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#define CQHCI_DATA_TAG(x) (((x) & 1) << 11) |
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#define CQHCI_DATA_DIR(x) (((x) & 1) << 12) |
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#define CQHCI_PRIORITY(x) (((x) & 1) << 13) |
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#define CQHCI_QBAR(x) (((x) & 1) << 14) |
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#define CQHCI_REL_WRITE(x) (((x) & 1) << 15) |
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#define CQHCI_BLK_COUNT(x) (((x) & 0xFFFF) << 16) |
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#define CQHCI_BLK_ADDR(x) (((x) & 0xFFFFFFFF) << 32) |
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/* direct command task descriptor fields */ |
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#define CQHCI_CMD_INDEX(x) (((x) & 0x3F) << 16) |
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#define CQHCI_CMD_TIMING(x) (((x) & 1) << 22) |
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#define CQHCI_RESP_TYPE(x) (((x) & 0x3) << 23) |
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/* crypto task descriptor fields (for bits 64-127 of task descriptor) */ |
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#define CQHCI_CRYPTO_ENABLE_BIT (1ULL << 47) |
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#define CQHCI_CRYPTO_KEYSLOT(x) ((u64)(x) << 32) |
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/* transfer descriptor fields */ |
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#define CQHCI_DAT_LENGTH(x) (((x) & 0xFFFF) << 16) |
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#define CQHCI_DAT_ADDR_LO(x) (((x) & 0xFFFFFFFF) << 32) |
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#define CQHCI_DAT_ADDR_HI(x) (((x) & 0xFFFFFFFF) << 0) |
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/* CCAP - Crypto Capability 100h */ |
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union cqhci_crypto_capabilities { |
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__le32 reg_val; |
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struct { |
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u8 num_crypto_cap; |
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u8 config_count; |
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u8 reserved; |
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u8 config_array_ptr; |
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}; |
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}; |
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enum cqhci_crypto_key_size { |
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CQHCI_CRYPTO_KEY_SIZE_INVALID = 0, |
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CQHCI_CRYPTO_KEY_SIZE_128 = 1, |
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CQHCI_CRYPTO_KEY_SIZE_192 = 2, |
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CQHCI_CRYPTO_KEY_SIZE_256 = 3, |
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CQHCI_CRYPTO_KEY_SIZE_512 = 4, |
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}; |
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enum cqhci_crypto_alg { |
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CQHCI_CRYPTO_ALG_AES_XTS = 0, |
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CQHCI_CRYPTO_ALG_BITLOCKER_AES_CBC = 1, |
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CQHCI_CRYPTO_ALG_AES_ECB = 2, |
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CQHCI_CRYPTO_ALG_ESSIV_AES_CBC = 3, |
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}; |
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/* x-CRYPTOCAP - Crypto Capability X */ |
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union cqhci_crypto_cap_entry { |
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__le32 reg_val; |
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struct { |
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u8 algorithm_id; |
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u8 sdus_mask; /* Supported data unit size mask */ |
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u8 key_size; |
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u8 reserved; |
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}; |
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}; |
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#define CQHCI_CRYPTO_CONFIGURATION_ENABLE (1 << 7) |
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#define CQHCI_CRYPTO_KEY_MAX_SIZE 64 |
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/* x-CRYPTOCFG - Crypto Configuration X */ |
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union cqhci_crypto_cfg_entry { |
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__le32 reg_val[32]; |
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struct { |
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u8 crypto_key[CQHCI_CRYPTO_KEY_MAX_SIZE]; |
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u8 data_unit_size; |
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u8 crypto_cap_idx; |
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u8 reserved_1; |
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u8 config_enable; |
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u8 reserved_multi_host; |
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u8 reserved_2; |
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u8 vsb[2]; |
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u8 reserved_3[56]; |
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}; |
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}; |
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struct cqhci_host_ops; |
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struct mmc_host; |
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struct mmc_request; |
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struct cqhci_slot; |
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struct cqhci_host { |
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const struct cqhci_host_ops *ops; |
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void __iomem *mmio; |
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struct mmc_host *mmc; |
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spinlock_t lock; |
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/* relative card address of device */ |
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unsigned int rca; |
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/* 64 bit DMA */ |
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bool dma64; |
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int num_slots; |
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int qcnt; |
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u32 dcmd_slot; |
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u32 caps; |
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#define CQHCI_TASK_DESC_SZ_128 0x1 |
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u32 quirks; |
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#define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ 0x1 |
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bool enabled; |
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bool halted; |
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bool init_done; |
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bool activated; |
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bool waiting_for_idle; |
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bool recovery_halt; |
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size_t desc_size; |
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size_t data_size; |
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u8 *desc_base; |
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/* total descriptor size */ |
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u8 slot_sz; |
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/* 64/128 bit depends on CQHCI_CFG */ |
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u8 task_desc_len; |
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/* 64 bit on 32-bit arch, 128 bit on 64-bit */ |
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u8 link_desc_len; |
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u8 *trans_desc_base; |
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/* same length as transfer descriptor */ |
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u8 trans_desc_len; |
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dma_addr_t desc_dma_base; |
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dma_addr_t trans_desc_dma_base; |
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struct completion halt_comp; |
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wait_queue_head_t wait_queue; |
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struct cqhci_slot *slot; |
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#ifdef CONFIG_MMC_CRYPTO |
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union cqhci_crypto_capabilities crypto_capabilities; |
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union cqhci_crypto_cap_entry *crypto_cap_array; |
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u32 crypto_cfg_register; |
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#endif |
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}; |
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struct cqhci_host_ops { |
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void (*dumpregs)(struct mmc_host *mmc); |
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void (*write_l)(struct cqhci_host *host, u32 val, int reg); |
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u32 (*read_l)(struct cqhci_host *host, int reg); |
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void (*enable)(struct mmc_host *mmc); |
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void (*disable)(struct mmc_host *mmc, bool recovery); |
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void (*update_dcmd_desc)(struct mmc_host *mmc, struct mmc_request *mrq, |
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u64 *data); |
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void (*pre_enable)(struct mmc_host *mmc); |
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void (*post_disable)(struct mmc_host *mmc); |
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#ifdef CONFIG_MMC_CRYPTO |
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int (*program_key)(struct cqhci_host *cq_host, |
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const union cqhci_crypto_cfg_entry *cfg, int slot); |
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#endif |
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}; |
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static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg) |
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{ |
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if (unlikely(host->ops->write_l)) |
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host->ops->write_l(host, val, reg); |
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else |
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writel_relaxed(val, host->mmio + reg); |
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} |
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static inline u32 cqhci_readl(struct cqhci_host *host, int reg) |
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{ |
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if (unlikely(host->ops->read_l)) |
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return host->ops->read_l(host, reg); |
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else |
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return readl_relaxed(host->mmio + reg); |
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} |
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struct platform_device; |
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irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error, |
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int data_error); |
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int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64); |
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struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev); |
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int cqhci_deactivate(struct mmc_host *mmc); |
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static inline int cqhci_suspend(struct mmc_host *mmc) |
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{ |
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return cqhci_deactivate(mmc); |
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} |
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int cqhci_resume(struct mmc_host *mmc); |
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#endif
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