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148 lines
3.5 KiB
148 lines
3.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited |
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*/ |
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#include <linux/init.h> |
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#include <linux/kernel.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqdomain.h> |
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#include <asm/loongarch.h> |
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#include <asm/setup.h> |
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static struct irq_domain *irq_domain; |
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struct fwnode_handle *cpuintc_handle; |
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static u32 lpic_gsi_to_irq(u32 gsi) |
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{ |
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/* Only pch irqdomain transferring is required for LoongArch. */ |
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if (gsi >= GSI_MIN_PCH_IRQ && gsi <= GSI_MAX_PCH_IRQ) |
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return acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH); |
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return 0; |
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} |
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static struct fwnode_handle *lpic_get_gsi_domain_id(u32 gsi) |
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{ |
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int id; |
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struct fwnode_handle *domain_handle = NULL; |
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switch (gsi) { |
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case GSI_MIN_CPU_IRQ ... GSI_MAX_CPU_IRQ: |
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if (liointc_handle) |
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domain_handle = liointc_handle; |
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break; |
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case GSI_MIN_LPC_IRQ ... GSI_MAX_LPC_IRQ: |
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if (pch_lpc_handle) |
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domain_handle = pch_lpc_handle; |
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break; |
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case GSI_MIN_PCH_IRQ ... GSI_MAX_PCH_IRQ: |
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id = find_pch_pic(gsi); |
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if (id >= 0 && pch_pic_handle[id]) |
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domain_handle = pch_pic_handle[id]; |
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break; |
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} |
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return domain_handle; |
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} |
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static void mask_loongarch_irq(struct irq_data *d) |
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{ |
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clear_csr_ecfg(ECFGF(d->hwirq)); |
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} |
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static void unmask_loongarch_irq(struct irq_data *d) |
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{ |
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set_csr_ecfg(ECFGF(d->hwirq)); |
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} |
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static struct irq_chip cpu_irq_controller = { |
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.name = "CPUINTC", |
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.irq_mask = mask_loongarch_irq, |
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.irq_unmask = unmask_loongarch_irq, |
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}; |
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static void handle_cpu_irq(struct pt_regs *regs) |
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{ |
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int hwirq; |
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unsigned int estat = read_csr_estat() & CSR_ESTAT_IS; |
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while ((hwirq = ffs(estat))) { |
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estat &= ~BIT(hwirq - 1); |
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generic_handle_domain_irq(irq_domain, hwirq - 1); |
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} |
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} |
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static int loongarch_cpu_intc_map(struct irq_domain *d, unsigned int irq, |
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irq_hw_number_t hwirq) |
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{ |
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irq_set_noprobe(irq); |
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irq_set_chip_and_handler(irq, &cpu_irq_controller, handle_percpu_irq); |
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return 0; |
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} |
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static const struct irq_domain_ops loongarch_cpu_intc_irq_domain_ops = { |
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.map = loongarch_cpu_intc_map, |
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.xlate = irq_domain_xlate_onecell, |
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}; |
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static int __init |
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liointc_parse_madt(union acpi_subtable_headers *header, |
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const unsigned long end) |
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{ |
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struct acpi_madt_lio_pic *liointc_entry = (struct acpi_madt_lio_pic *)header; |
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return liointc_acpi_init(irq_domain, liointc_entry); |
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} |
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static int __init |
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eiointc_parse_madt(union acpi_subtable_headers *header, |
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const unsigned long end) |
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{ |
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struct acpi_madt_eio_pic *eiointc_entry = (struct acpi_madt_eio_pic *)header; |
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return eiointc_acpi_init(irq_domain, eiointc_entry); |
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} |
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static int __init acpi_cascade_irqdomain_init(void) |
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{ |
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acpi_table_parse_madt(ACPI_MADT_TYPE_LIO_PIC, |
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liointc_parse_madt, 0); |
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acpi_table_parse_madt(ACPI_MADT_TYPE_EIO_PIC, |
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eiointc_parse_madt, 0); |
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return 0; |
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} |
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static int __init cpuintc_acpi_init(union acpi_subtable_headers *header, |
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const unsigned long end) |
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{ |
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if (irq_domain) |
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return 0; |
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/* Mask interrupts. */ |
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clear_csr_ecfg(ECFG0_IM); |
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clear_csr_estat(ESTATF_IP); |
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cpuintc_handle = irq_domain_alloc_named_fwnode("CPUINTC"); |
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irq_domain = irq_domain_create_linear(cpuintc_handle, EXCCODE_INT_NUM, |
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&loongarch_cpu_intc_irq_domain_ops, NULL); |
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if (!irq_domain) |
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panic("Failed to add irqdomain for LoongArch CPU"); |
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set_handle_irq(&handle_cpu_irq); |
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acpi_set_irq_model(ACPI_IRQ_MODEL_LPIC, lpic_get_gsi_domain_id); |
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acpi_set_gsi_to_irq_fallback(lpic_gsi_to_irq); |
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acpi_cascade_irqdomain_init(); |
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return 0; |
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} |
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IRQCHIP_ACPI_DECLARE(cpuintc_v1, ACPI_MADT_TYPE_CORE_PIC, |
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NULL, ACPI_MADT_CORE_PIC_VERSION_V1, cpuintc_acpi_init);
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