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1022 lines
30 KiB
1022 lines
30 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Driver for FPGA Management Engine (FME) Global Performance Reporting |
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* |
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* Copyright 2019 Intel Corporation, Inc. |
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* |
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* Authors: |
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* Kang Luwei <[email protected]> |
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* Xiao Guangrong <[email protected]> |
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* Wu Hao <[email protected]> |
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* Xu Yilun <[email protected]> |
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* Joseph Grecco <[email protected]> |
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* Enno Luebbers <[email protected]> |
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* Tim Whisonant <[email protected]> |
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* Ananda Ravuri <[email protected]> |
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* Mitchel, Henry <[email protected]> |
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*/ |
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|
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#include <linux/perf_event.h> |
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#include "dfl.h" |
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#include "dfl-fme.h" |
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|
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/* |
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* Performance Counter Registers for Cache. |
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* |
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* Cache Events are listed below as CACHE_EVNT_*. |
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*/ |
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#define CACHE_CTRL 0x8 |
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#define CACHE_RESET_CNTR BIT_ULL(0) |
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#define CACHE_FREEZE_CNTR BIT_ULL(8) |
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#define CACHE_CTRL_EVNT GENMASK_ULL(19, 16) |
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#define CACHE_EVNT_RD_HIT 0x0 |
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#define CACHE_EVNT_WR_HIT 0x1 |
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#define CACHE_EVNT_RD_MISS 0x2 |
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#define CACHE_EVNT_WR_MISS 0x3 |
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#define CACHE_EVNT_RSVD 0x4 |
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#define CACHE_EVNT_HOLD_REQ 0x5 |
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#define CACHE_EVNT_DATA_WR_PORT_CONTEN 0x6 |
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#define CACHE_EVNT_TAG_WR_PORT_CONTEN 0x7 |
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#define CACHE_EVNT_TX_REQ_STALL 0x8 |
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#define CACHE_EVNT_RX_REQ_STALL 0x9 |
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#define CACHE_EVNT_EVICTIONS 0xa |
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#define CACHE_EVNT_MAX CACHE_EVNT_EVICTIONS |
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#define CACHE_CHANNEL_SEL BIT_ULL(20) |
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#define CACHE_CHANNEL_RD 0 |
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#define CACHE_CHANNEL_WR 1 |
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#define CACHE_CNTR0 0x10 |
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#define CACHE_CNTR1 0x18 |
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#define CACHE_CNTR_EVNT_CNTR GENMASK_ULL(47, 0) |
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#define CACHE_CNTR_EVNT GENMASK_ULL(63, 60) |
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|
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/* |
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* Performance Counter Registers for Fabric. |
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* |
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* Fabric Events are listed below as FAB_EVNT_* |
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*/ |
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#define FAB_CTRL 0x20 |
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#define FAB_RESET_CNTR BIT_ULL(0) |
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#define FAB_FREEZE_CNTR BIT_ULL(8) |
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#define FAB_CTRL_EVNT GENMASK_ULL(19, 16) |
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#define FAB_EVNT_PCIE0_RD 0x0 |
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#define FAB_EVNT_PCIE0_WR 0x1 |
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#define FAB_EVNT_PCIE1_RD 0x2 |
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#define FAB_EVNT_PCIE1_WR 0x3 |
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#define FAB_EVNT_UPI_RD 0x4 |
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#define FAB_EVNT_UPI_WR 0x5 |
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#define FAB_EVNT_MMIO_RD 0x6 |
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#define FAB_EVNT_MMIO_WR 0x7 |
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#define FAB_EVNT_MAX FAB_EVNT_MMIO_WR |
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#define FAB_PORT_ID GENMASK_ULL(21, 20) |
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#define FAB_PORT_FILTER BIT_ULL(23) |
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#define FAB_PORT_FILTER_DISABLE 0 |
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#define FAB_PORT_FILTER_ENABLE 1 |
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#define FAB_CNTR 0x28 |
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#define FAB_CNTR_EVNT_CNTR GENMASK_ULL(59, 0) |
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#define FAB_CNTR_EVNT GENMASK_ULL(63, 60) |
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|
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/* |
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* Performance Counter Registers for Clock. |
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* |
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* Clock Counter can't be reset or frozen by SW. |
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*/ |
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#define CLK_CNTR 0x30 |
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#define BASIC_EVNT_CLK 0x0 |
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#define BASIC_EVNT_MAX BASIC_EVNT_CLK |
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|
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/* |
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* Performance Counter Registers for IOMMU / VT-D. |
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* |
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* VT-D Events are listed below as VTD_EVNT_* and VTD_SIP_EVNT_* |
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*/ |
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#define VTD_CTRL 0x38 |
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#define VTD_RESET_CNTR BIT_ULL(0) |
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#define VTD_FREEZE_CNTR BIT_ULL(8) |
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#define VTD_CTRL_EVNT GENMASK_ULL(19, 16) |
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#define VTD_EVNT_AFU_MEM_RD_TRANS 0x0 |
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#define VTD_EVNT_AFU_MEM_WR_TRANS 0x1 |
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#define VTD_EVNT_AFU_DEVTLB_RD_HIT 0x2 |
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#define VTD_EVNT_AFU_DEVTLB_WR_HIT 0x3 |
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#define VTD_EVNT_DEVTLB_4K_FILL 0x4 |
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#define VTD_EVNT_DEVTLB_2M_FILL 0x5 |
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#define VTD_EVNT_DEVTLB_1G_FILL 0x6 |
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#define VTD_EVNT_MAX VTD_EVNT_DEVTLB_1G_FILL |
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#define VTD_CNTR 0x40 |
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#define VTD_CNTR_EVNT_CNTR GENMASK_ULL(47, 0) |
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#define VTD_CNTR_EVNT GENMASK_ULL(63, 60) |
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|
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#define VTD_SIP_CTRL 0x48 |
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#define VTD_SIP_RESET_CNTR BIT_ULL(0) |
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#define VTD_SIP_FREEZE_CNTR BIT_ULL(8) |
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#define VTD_SIP_CTRL_EVNT GENMASK_ULL(19, 16) |
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#define VTD_SIP_EVNT_IOTLB_4K_HIT 0x0 |
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#define VTD_SIP_EVNT_IOTLB_2M_HIT 0x1 |
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#define VTD_SIP_EVNT_IOTLB_1G_HIT 0x2 |
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#define VTD_SIP_EVNT_SLPWC_L3_HIT 0x3 |
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#define VTD_SIP_EVNT_SLPWC_L4_HIT 0x4 |
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#define VTD_SIP_EVNT_RCC_HIT 0x5 |
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#define VTD_SIP_EVNT_IOTLB_4K_MISS 0x6 |
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#define VTD_SIP_EVNT_IOTLB_2M_MISS 0x7 |
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#define VTD_SIP_EVNT_IOTLB_1G_MISS 0x8 |
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#define VTD_SIP_EVNT_SLPWC_L3_MISS 0x9 |
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#define VTD_SIP_EVNT_SLPWC_L4_MISS 0xa |
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#define VTD_SIP_EVNT_RCC_MISS 0xb |
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#define VTD_SIP_EVNT_MAX VTD_SIP_EVNT_SLPWC_L4_MISS |
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#define VTD_SIP_CNTR 0X50 |
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#define VTD_SIP_CNTR_EVNT_CNTR GENMASK_ULL(47, 0) |
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#define VTD_SIP_CNTR_EVNT GENMASK_ULL(63, 60) |
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|
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#define PERF_TIMEOUT 30 |
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|
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#define PERF_MAX_PORT_NUM 1U |
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|
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/** |
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* struct fme_perf_priv - priv data structure for fme perf driver |
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* |
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* @dev: parent device. |
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* @ioaddr: mapped base address of mmio region. |
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* @pmu: pmu data structure for fme perf counters. |
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* @id: id of this fme performance report private feature. |
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* @fab_users: current user number on fabric counters. |
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* @fab_port_id: used to indicate current working mode of fabric counters. |
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* @fab_lock: lock to protect fabric counters working mode. |
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* @cpu: active CPU to which the PMU is bound for accesses. |
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* @cpuhp_node: node for CPU hotplug notifier link. |
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* @cpuhp_state: state for CPU hotplug notification; |
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*/ |
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struct fme_perf_priv { |
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struct device *dev; |
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void __iomem *ioaddr; |
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struct pmu pmu; |
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u16 id; |
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|
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u32 fab_users; |
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u32 fab_port_id; |
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spinlock_t fab_lock; |
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|
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unsigned int cpu; |
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struct hlist_node node; |
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enum cpuhp_state cpuhp_state; |
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}; |
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|
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/** |
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* struct fme_perf_event_ops - callbacks for fme perf events |
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* |
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* @event_init: callback invoked during event init. |
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* @event_destroy: callback invoked during event destroy. |
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* @read_counter: callback to read hardware counters. |
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*/ |
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struct fme_perf_event_ops { |
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int (*event_init)(struct fme_perf_priv *priv, u32 event, u32 portid); |
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void (*event_destroy)(struct fme_perf_priv *priv, u32 event, |
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u32 portid); |
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u64 (*read_counter)(struct fme_perf_priv *priv, u32 event, u32 portid); |
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}; |
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|
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#define to_fme_perf_priv(_pmu) container_of(_pmu, struct fme_perf_priv, pmu) |
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|
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static ssize_t cpumask_show(struct device *dev, |
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struct device_attribute *attr, char *buf) |
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{ |
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struct pmu *pmu = dev_get_drvdata(dev); |
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struct fme_perf_priv *priv; |
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|
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priv = to_fme_perf_priv(pmu); |
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|
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return cpumap_print_to_pagebuf(true, buf, cpumask_of(priv->cpu)); |
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} |
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static DEVICE_ATTR_RO(cpumask); |
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|
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static struct attribute *fme_perf_cpumask_attrs[] = { |
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&dev_attr_cpumask.attr, |
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NULL, |
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}; |
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|
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static const struct attribute_group fme_perf_cpumask_group = { |
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.attrs = fme_perf_cpumask_attrs, |
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}; |
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|
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#define FME_EVENT_MASK GENMASK_ULL(11, 0) |
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#define FME_EVENT_SHIFT 0 |
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#define FME_EVTYPE_MASK GENMASK_ULL(15, 12) |
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#define FME_EVTYPE_SHIFT 12 |
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#define FME_EVTYPE_BASIC 0 |
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#define FME_EVTYPE_CACHE 1 |
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#define FME_EVTYPE_FABRIC 2 |
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#define FME_EVTYPE_VTD 3 |
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#define FME_EVTYPE_VTD_SIP 4 |
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#define FME_EVTYPE_MAX FME_EVTYPE_VTD_SIP |
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#define FME_PORTID_MASK GENMASK_ULL(23, 16) |
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#define FME_PORTID_SHIFT 16 |
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#define FME_PORTID_ROOT (0xffU) |
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|
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#define get_event(_config) FIELD_GET(FME_EVENT_MASK, _config) |
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#define get_evtype(_config) FIELD_GET(FME_EVTYPE_MASK, _config) |
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#define get_portid(_config) FIELD_GET(FME_PORTID_MASK, _config) |
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|
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PMU_FORMAT_ATTR(event, "config:0-11"); |
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PMU_FORMAT_ATTR(evtype, "config:12-15"); |
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PMU_FORMAT_ATTR(portid, "config:16-23"); |
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|
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static struct attribute *fme_perf_format_attrs[] = { |
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&format_attr_event.attr, |
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&format_attr_evtype.attr, |
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&format_attr_portid.attr, |
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NULL, |
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}; |
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|
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static const struct attribute_group fme_perf_format_group = { |
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.name = "format", |
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.attrs = fme_perf_format_attrs, |
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}; |
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|
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/* |
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* There are no default events, but we need to create |
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* "events" group (with empty attrs) before updating |
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* it with detected events (using pmu->attr_update). |
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*/ |
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static struct attribute *fme_perf_events_attrs_empty[] = { |
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NULL, |
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}; |
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static const struct attribute_group fme_perf_events_group = { |
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.name = "events", |
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.attrs = fme_perf_events_attrs_empty, |
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}; |
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|
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static const struct attribute_group *fme_perf_groups[] = { |
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&fme_perf_format_group, |
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&fme_perf_cpumask_group, |
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&fme_perf_events_group, |
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NULL, |
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}; |
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static bool is_portid_root(u32 portid) |
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{ |
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return portid == FME_PORTID_ROOT; |
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} |
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static bool is_portid_port(u32 portid) |
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{ |
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return portid < PERF_MAX_PORT_NUM; |
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} |
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static bool is_portid_root_or_port(u32 portid) |
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{ |
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return is_portid_root(portid) || is_portid_port(portid); |
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} |
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static u64 fme_read_perf_cntr_reg(void __iomem *addr) |
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{ |
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u32 low; |
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u64 v; |
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|
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/* |
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* For 64bit counter registers, the counter may increases and carries |
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* out of bit [31] between 2 32bit reads. So add extra reads to help |
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* to prevent this issue. This only happens in platforms which don't |
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* support 64bit read - readq is split into 2 readl. |
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*/ |
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do { |
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v = readq(addr); |
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low = readl(addr); |
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} while (((u32)v) > low); |
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return v; |
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} |
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static int basic_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) |
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{ |
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if (event <= BASIC_EVNT_MAX && is_portid_root(portid)) |
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return 0; |
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return -EINVAL; |
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} |
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static u64 basic_read_event_counter(struct fme_perf_priv *priv, |
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u32 event, u32 portid) |
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{ |
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void __iomem *base = priv->ioaddr; |
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|
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return fme_read_perf_cntr_reg(base + CLK_CNTR); |
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} |
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|
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static int cache_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) |
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{ |
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if (priv->id == FME_FEATURE_ID_GLOBAL_IPERF && |
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event <= CACHE_EVNT_MAX && is_portid_root(portid)) |
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return 0; |
|
|
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return -EINVAL; |
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} |
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|
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static u64 cache_read_event_counter(struct fme_perf_priv *priv, |
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u32 event, u32 portid) |
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{ |
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void __iomem *base = priv->ioaddr; |
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u64 v, count; |
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u8 channel; |
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|
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if (event == CACHE_EVNT_WR_HIT || event == CACHE_EVNT_WR_MISS || |
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event == CACHE_EVNT_DATA_WR_PORT_CONTEN || |
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event == CACHE_EVNT_TAG_WR_PORT_CONTEN) |
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channel = CACHE_CHANNEL_WR; |
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else |
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channel = CACHE_CHANNEL_RD; |
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|
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/* set channel access type and cache event code. */ |
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v = readq(base + CACHE_CTRL); |
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v &= ~(CACHE_CHANNEL_SEL | CACHE_CTRL_EVNT); |
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v |= FIELD_PREP(CACHE_CHANNEL_SEL, channel); |
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v |= FIELD_PREP(CACHE_CTRL_EVNT, event); |
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writeq(v, base + CACHE_CTRL); |
|
|
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if (readq_poll_timeout_atomic(base + CACHE_CNTR0, v, |
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FIELD_GET(CACHE_CNTR_EVNT, v) == event, |
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1, PERF_TIMEOUT)) { |
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dev_err(priv->dev, "timeout, unmatched cache event code in counter register.\n"); |
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return 0; |
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} |
|
|
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v = fme_read_perf_cntr_reg(base + CACHE_CNTR0); |
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count = FIELD_GET(CACHE_CNTR_EVNT_CNTR, v); |
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v = fme_read_perf_cntr_reg(base + CACHE_CNTR1); |
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count += FIELD_GET(CACHE_CNTR_EVNT_CNTR, v); |
|
|
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return count; |
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} |
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|
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static bool is_fabric_event_supported(struct fme_perf_priv *priv, u32 event, |
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u32 portid) |
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{ |
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if (event > FAB_EVNT_MAX || !is_portid_root_or_port(portid)) |
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return false; |
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|
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if (priv->id == FME_FEATURE_ID_GLOBAL_DPERF && |
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(event == FAB_EVNT_PCIE1_RD || event == FAB_EVNT_UPI_RD || |
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event == FAB_EVNT_PCIE1_WR || event == FAB_EVNT_UPI_WR)) |
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return false; |
|
|
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return true; |
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} |
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|
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static int fabric_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) |
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{ |
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void __iomem *base = priv->ioaddr; |
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int ret = 0; |
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u64 v; |
|
|
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if (!is_fabric_event_supported(priv, event, portid)) |
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return -EINVAL; |
|
|
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/* |
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* as fabric counter set only can be in either overall or port mode. |
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* In overall mode, it counts overall data for FPGA, and in port mode, |
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* it is configured to monitor on one individual port. |
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* |
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* so every time, a new event is initialized, driver checks |
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* current working mode and if someone is using this counter set. |
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*/ |
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spin_lock(&priv->fab_lock); |
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if (priv->fab_users && priv->fab_port_id != portid) { |
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dev_dbg(priv->dev, "conflict fabric event monitoring mode.\n"); |
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ret = -EOPNOTSUPP; |
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goto exit; |
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} |
|
|
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priv->fab_users++; |
|
|
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/* |
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* skip if current working mode matches, otherwise change the working |
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* mode per input port_id, to monitor overall data or another port. |
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*/ |
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if (priv->fab_port_id == portid) |
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goto exit; |
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|
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priv->fab_port_id = portid; |
|
|
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v = readq(base + FAB_CTRL); |
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v &= ~(FAB_PORT_FILTER | FAB_PORT_ID); |
|
|
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if (is_portid_root(portid)) { |
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v |= FIELD_PREP(FAB_PORT_FILTER, FAB_PORT_FILTER_DISABLE); |
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} else { |
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v |= FIELD_PREP(FAB_PORT_FILTER, FAB_PORT_FILTER_ENABLE); |
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v |= FIELD_PREP(FAB_PORT_ID, portid); |
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} |
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writeq(v, base + FAB_CTRL); |
|
|
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exit: |
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spin_unlock(&priv->fab_lock); |
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return ret; |
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} |
|
|
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static void fabric_event_destroy(struct fme_perf_priv *priv, u32 event, |
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u32 portid) |
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{ |
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spin_lock(&priv->fab_lock); |
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priv->fab_users--; |
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spin_unlock(&priv->fab_lock); |
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} |
|
|
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static u64 fabric_read_event_counter(struct fme_perf_priv *priv, u32 event, |
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u32 portid) |
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{ |
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void __iomem *base = priv->ioaddr; |
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u64 v; |
|
|
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v = readq(base + FAB_CTRL); |
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v &= ~FAB_CTRL_EVNT; |
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v |= FIELD_PREP(FAB_CTRL_EVNT, event); |
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writeq(v, base + FAB_CTRL); |
|
|
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if (readq_poll_timeout_atomic(base + FAB_CNTR, v, |
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FIELD_GET(FAB_CNTR_EVNT, v) == event, |
|
1, PERF_TIMEOUT)) { |
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dev_err(priv->dev, "timeout, unmatched fab event code in counter register.\n"); |
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return 0; |
|
} |
|
|
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v = fme_read_perf_cntr_reg(base + FAB_CNTR); |
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return FIELD_GET(FAB_CNTR_EVNT_CNTR, v); |
|
} |
|
|
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static int vtd_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) |
|
{ |
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if (priv->id == FME_FEATURE_ID_GLOBAL_IPERF && |
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event <= VTD_EVNT_MAX && is_portid_port(portid)) |
|
return 0; |
|
|
|
return -EINVAL; |
|
} |
|
|
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static u64 vtd_read_event_counter(struct fme_perf_priv *priv, u32 event, |
|
u32 portid) |
|
{ |
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void __iomem *base = priv->ioaddr; |
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u64 v; |
|
|
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event += (portid * (VTD_EVNT_MAX + 1)); |
|
|
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v = readq(base + VTD_CTRL); |
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v &= ~VTD_CTRL_EVNT; |
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v |= FIELD_PREP(VTD_CTRL_EVNT, event); |
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writeq(v, base + VTD_CTRL); |
|
|
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if (readq_poll_timeout_atomic(base + VTD_CNTR, v, |
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FIELD_GET(VTD_CNTR_EVNT, v) == event, |
|
1, PERF_TIMEOUT)) { |
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dev_err(priv->dev, "timeout, unmatched vtd event code in counter register.\n"); |
|
return 0; |
|
} |
|
|
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v = fme_read_perf_cntr_reg(base + VTD_CNTR); |
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return FIELD_GET(VTD_CNTR_EVNT_CNTR, v); |
|
} |
|
|
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static int vtd_sip_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) |
|
{ |
|
if (priv->id == FME_FEATURE_ID_GLOBAL_IPERF && |
|
event <= VTD_SIP_EVNT_MAX && is_portid_root(portid)) |
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return 0; |
|
|
|
return -EINVAL; |
|
} |
|
|
|
static u64 vtd_sip_read_event_counter(struct fme_perf_priv *priv, u32 event, |
|
u32 portid) |
|
{ |
|
void __iomem *base = priv->ioaddr; |
|
u64 v; |
|
|
|
v = readq(base + VTD_SIP_CTRL); |
|
v &= ~VTD_SIP_CTRL_EVNT; |
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v |= FIELD_PREP(VTD_SIP_CTRL_EVNT, event); |
|
writeq(v, base + VTD_SIP_CTRL); |
|
|
|
if (readq_poll_timeout_atomic(base + VTD_SIP_CNTR, v, |
|
FIELD_GET(VTD_SIP_CNTR_EVNT, v) == event, |
|
1, PERF_TIMEOUT)) { |
|
dev_err(priv->dev, "timeout, unmatched vtd sip event code in counter register\n"); |
|
return 0; |
|
} |
|
|
|
v = fme_read_perf_cntr_reg(base + VTD_SIP_CNTR); |
|
return FIELD_GET(VTD_SIP_CNTR_EVNT_CNTR, v); |
|
} |
|
|
|
static struct fme_perf_event_ops fme_perf_event_ops[] = { |
|
[FME_EVTYPE_BASIC] = {.event_init = basic_event_init, |
|
.read_counter = basic_read_event_counter,}, |
|
[FME_EVTYPE_CACHE] = {.event_init = cache_event_init, |
|
.read_counter = cache_read_event_counter,}, |
|
[FME_EVTYPE_FABRIC] = {.event_init = fabric_event_init, |
|
.event_destroy = fabric_event_destroy, |
|
.read_counter = fabric_read_event_counter,}, |
|
[FME_EVTYPE_VTD] = {.event_init = vtd_event_init, |
|
.read_counter = vtd_read_event_counter,}, |
|
[FME_EVTYPE_VTD_SIP] = {.event_init = vtd_sip_event_init, |
|
.read_counter = vtd_sip_read_event_counter,}, |
|
}; |
|
|
|
static ssize_t fme_perf_event_show(struct device *dev, |
|
struct device_attribute *attr, char *buf) |
|
{ |
|
struct dev_ext_attribute *eattr; |
|
unsigned long config; |
|
char *ptr = buf; |
|
|
|
eattr = container_of(attr, struct dev_ext_attribute, attr); |
|
config = (unsigned long)eattr->var; |
|
|
|
ptr += sprintf(ptr, "event=0x%02x", (unsigned int)get_event(config)); |
|
ptr += sprintf(ptr, ",evtype=0x%02x", (unsigned int)get_evtype(config)); |
|
|
|
if (is_portid_root(get_portid(config))) |
|
ptr += sprintf(ptr, ",portid=0x%02x\n", FME_PORTID_ROOT); |
|
else |
|
ptr += sprintf(ptr, ",portid=?\n"); |
|
|
|
return (ssize_t)(ptr - buf); |
|
} |
|
|
|
#define FME_EVENT_ATTR(_name) \ |
|
__ATTR(_name, 0444, fme_perf_event_show, NULL) |
|
|
|
#define FME_PORT_EVENT_CONFIG(_event, _type) \ |
|
(void *)((((_event) << FME_EVENT_SHIFT) & FME_EVENT_MASK) | \ |
|
(((_type) << FME_EVTYPE_SHIFT) & FME_EVTYPE_MASK)) |
|
|
|
#define FME_EVENT_CONFIG(_event, _type) \ |
|
(void *)((((_event) << FME_EVENT_SHIFT) & FME_EVENT_MASK) | \ |
|
(((_type) << FME_EVTYPE_SHIFT) & FME_EVTYPE_MASK) | \ |
|
(FME_PORTID_ROOT << FME_PORTID_SHIFT)) |
|
|
|
/* FME Perf Basic Events */ |
|
#define FME_EVENT_BASIC(_name, _event) \ |
|
static struct dev_ext_attribute fme_perf_event_##_name = { \ |
|
.attr = FME_EVENT_ATTR(_name), \ |
|
.var = FME_EVENT_CONFIG(_event, FME_EVTYPE_BASIC), \ |
|
} |
|
|
|
FME_EVENT_BASIC(clock, BASIC_EVNT_CLK); |
|
|
|
static struct attribute *fme_perf_basic_events_attrs[] = { |
|
&fme_perf_event_clock.attr.attr, |
|
NULL, |
|
}; |
|
|
|
static const struct attribute_group fme_perf_basic_events_group = { |
|
.name = "events", |
|
.attrs = fme_perf_basic_events_attrs, |
|
}; |
|
|
|
/* FME Perf Cache Events */ |
|
#define FME_EVENT_CACHE(_name, _event) \ |
|
static struct dev_ext_attribute fme_perf_event_cache_##_name = { \ |
|
.attr = FME_EVENT_ATTR(cache_##_name), \ |
|
.var = FME_EVENT_CONFIG(_event, FME_EVTYPE_CACHE), \ |
|
} |
|
|
|
FME_EVENT_CACHE(read_hit, CACHE_EVNT_RD_HIT); |
|
FME_EVENT_CACHE(read_miss, CACHE_EVNT_RD_MISS); |
|
FME_EVENT_CACHE(write_hit, CACHE_EVNT_WR_HIT); |
|
FME_EVENT_CACHE(write_miss, CACHE_EVNT_WR_MISS); |
|
FME_EVENT_CACHE(hold_request, CACHE_EVNT_HOLD_REQ); |
|
FME_EVENT_CACHE(tx_req_stall, CACHE_EVNT_TX_REQ_STALL); |
|
FME_EVENT_CACHE(rx_req_stall, CACHE_EVNT_RX_REQ_STALL); |
|
FME_EVENT_CACHE(eviction, CACHE_EVNT_EVICTIONS); |
|
FME_EVENT_CACHE(data_write_port_contention, CACHE_EVNT_DATA_WR_PORT_CONTEN); |
|
FME_EVENT_CACHE(tag_write_port_contention, CACHE_EVNT_TAG_WR_PORT_CONTEN); |
|
|
|
static struct attribute *fme_perf_cache_events_attrs[] = { |
|
&fme_perf_event_cache_read_hit.attr.attr, |
|
&fme_perf_event_cache_read_miss.attr.attr, |
|
&fme_perf_event_cache_write_hit.attr.attr, |
|
&fme_perf_event_cache_write_miss.attr.attr, |
|
&fme_perf_event_cache_hold_request.attr.attr, |
|
&fme_perf_event_cache_tx_req_stall.attr.attr, |
|
&fme_perf_event_cache_rx_req_stall.attr.attr, |
|
&fme_perf_event_cache_eviction.attr.attr, |
|
&fme_perf_event_cache_data_write_port_contention.attr.attr, |
|
&fme_perf_event_cache_tag_write_port_contention.attr.attr, |
|
NULL, |
|
}; |
|
|
|
static umode_t fme_perf_events_visible(struct kobject *kobj, |
|
struct attribute *attr, int n) |
|
{ |
|
struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj)); |
|
struct fme_perf_priv *priv = to_fme_perf_priv(pmu); |
|
|
|
return (priv->id == FME_FEATURE_ID_GLOBAL_IPERF) ? attr->mode : 0; |
|
} |
|
|
|
static const struct attribute_group fme_perf_cache_events_group = { |
|
.name = "events", |
|
.attrs = fme_perf_cache_events_attrs, |
|
.is_visible = fme_perf_events_visible, |
|
}; |
|
|
|
/* FME Perf Fabric Events */ |
|
#define FME_EVENT_FABRIC(_name, _event) \ |
|
static struct dev_ext_attribute fme_perf_event_fab_##_name = { \ |
|
.attr = FME_EVENT_ATTR(fab_##_name), \ |
|
.var = FME_EVENT_CONFIG(_event, FME_EVTYPE_FABRIC), \ |
|
} |
|
|
|
#define FME_EVENT_FABRIC_PORT(_name, _event) \ |
|
static struct dev_ext_attribute fme_perf_event_fab_port_##_name = { \ |
|
.attr = FME_EVENT_ATTR(fab_port_##_name), \ |
|
.var = FME_PORT_EVENT_CONFIG(_event, FME_EVTYPE_FABRIC), \ |
|
} |
|
|
|
FME_EVENT_FABRIC(pcie0_read, FAB_EVNT_PCIE0_RD); |
|
FME_EVENT_FABRIC(pcie0_write, FAB_EVNT_PCIE0_WR); |
|
FME_EVENT_FABRIC(pcie1_read, FAB_EVNT_PCIE1_RD); |
|
FME_EVENT_FABRIC(pcie1_write, FAB_EVNT_PCIE1_WR); |
|
FME_EVENT_FABRIC(upi_read, FAB_EVNT_UPI_RD); |
|
FME_EVENT_FABRIC(upi_write, FAB_EVNT_UPI_WR); |
|
FME_EVENT_FABRIC(mmio_read, FAB_EVNT_MMIO_RD); |
|
FME_EVENT_FABRIC(mmio_write, FAB_EVNT_MMIO_WR); |
|
|
|
FME_EVENT_FABRIC_PORT(pcie0_read, FAB_EVNT_PCIE0_RD); |
|
FME_EVENT_FABRIC_PORT(pcie0_write, FAB_EVNT_PCIE0_WR); |
|
FME_EVENT_FABRIC_PORT(pcie1_read, FAB_EVNT_PCIE1_RD); |
|
FME_EVENT_FABRIC_PORT(pcie1_write, FAB_EVNT_PCIE1_WR); |
|
FME_EVENT_FABRIC_PORT(upi_read, FAB_EVNT_UPI_RD); |
|
FME_EVENT_FABRIC_PORT(upi_write, FAB_EVNT_UPI_WR); |
|
FME_EVENT_FABRIC_PORT(mmio_read, FAB_EVNT_MMIO_RD); |
|
FME_EVENT_FABRIC_PORT(mmio_write, FAB_EVNT_MMIO_WR); |
|
|
|
static struct attribute *fme_perf_fabric_events_attrs[] = { |
|
&fme_perf_event_fab_pcie0_read.attr.attr, |
|
&fme_perf_event_fab_pcie0_write.attr.attr, |
|
&fme_perf_event_fab_pcie1_read.attr.attr, |
|
&fme_perf_event_fab_pcie1_write.attr.attr, |
|
&fme_perf_event_fab_upi_read.attr.attr, |
|
&fme_perf_event_fab_upi_write.attr.attr, |
|
&fme_perf_event_fab_mmio_read.attr.attr, |
|
&fme_perf_event_fab_mmio_write.attr.attr, |
|
&fme_perf_event_fab_port_pcie0_read.attr.attr, |
|
&fme_perf_event_fab_port_pcie0_write.attr.attr, |
|
&fme_perf_event_fab_port_pcie1_read.attr.attr, |
|
&fme_perf_event_fab_port_pcie1_write.attr.attr, |
|
&fme_perf_event_fab_port_upi_read.attr.attr, |
|
&fme_perf_event_fab_port_upi_write.attr.attr, |
|
&fme_perf_event_fab_port_mmio_read.attr.attr, |
|
&fme_perf_event_fab_port_mmio_write.attr.attr, |
|
NULL, |
|
}; |
|
|
|
static umode_t fme_perf_fabric_events_visible(struct kobject *kobj, |
|
struct attribute *attr, int n) |
|
{ |
|
struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj)); |
|
struct fme_perf_priv *priv = to_fme_perf_priv(pmu); |
|
struct dev_ext_attribute *eattr; |
|
unsigned long var; |
|
|
|
eattr = container_of(attr, struct dev_ext_attribute, attr.attr); |
|
var = (unsigned long)eattr->var; |
|
|
|
if (is_fabric_event_supported(priv, get_event(var), get_portid(var))) |
|
return attr->mode; |
|
|
|
return 0; |
|
} |
|
|
|
static const struct attribute_group fme_perf_fabric_events_group = { |
|
.name = "events", |
|
.attrs = fme_perf_fabric_events_attrs, |
|
.is_visible = fme_perf_fabric_events_visible, |
|
}; |
|
|
|
/* FME Perf VTD Events */ |
|
#define FME_EVENT_VTD_PORT(_name, _event) \ |
|
static struct dev_ext_attribute fme_perf_event_vtd_port_##_name = { \ |
|
.attr = FME_EVENT_ATTR(vtd_port_##_name), \ |
|
.var = FME_PORT_EVENT_CONFIG(_event, FME_EVTYPE_VTD), \ |
|
} |
|
|
|
FME_EVENT_VTD_PORT(read_transaction, VTD_EVNT_AFU_MEM_RD_TRANS); |
|
FME_EVENT_VTD_PORT(write_transaction, VTD_EVNT_AFU_MEM_WR_TRANS); |
|
FME_EVENT_VTD_PORT(devtlb_read_hit, VTD_EVNT_AFU_DEVTLB_RD_HIT); |
|
FME_EVENT_VTD_PORT(devtlb_write_hit, VTD_EVNT_AFU_DEVTLB_WR_HIT); |
|
FME_EVENT_VTD_PORT(devtlb_4k_fill, VTD_EVNT_DEVTLB_4K_FILL); |
|
FME_EVENT_VTD_PORT(devtlb_2m_fill, VTD_EVNT_DEVTLB_2M_FILL); |
|
FME_EVENT_VTD_PORT(devtlb_1g_fill, VTD_EVNT_DEVTLB_1G_FILL); |
|
|
|
static struct attribute *fme_perf_vtd_events_attrs[] = { |
|
&fme_perf_event_vtd_port_read_transaction.attr.attr, |
|
&fme_perf_event_vtd_port_write_transaction.attr.attr, |
|
&fme_perf_event_vtd_port_devtlb_read_hit.attr.attr, |
|
&fme_perf_event_vtd_port_devtlb_write_hit.attr.attr, |
|
&fme_perf_event_vtd_port_devtlb_4k_fill.attr.attr, |
|
&fme_perf_event_vtd_port_devtlb_2m_fill.attr.attr, |
|
&fme_perf_event_vtd_port_devtlb_1g_fill.attr.attr, |
|
NULL, |
|
}; |
|
|
|
static const struct attribute_group fme_perf_vtd_events_group = { |
|
.name = "events", |
|
.attrs = fme_perf_vtd_events_attrs, |
|
.is_visible = fme_perf_events_visible, |
|
}; |
|
|
|
/* FME Perf VTD SIP Events */ |
|
#define FME_EVENT_VTD_SIP(_name, _event) \ |
|
static struct dev_ext_attribute fme_perf_event_vtd_sip_##_name = { \ |
|
.attr = FME_EVENT_ATTR(vtd_sip_##_name), \ |
|
.var = FME_EVENT_CONFIG(_event, FME_EVTYPE_VTD_SIP), \ |
|
} |
|
|
|
FME_EVENT_VTD_SIP(iotlb_4k_hit, VTD_SIP_EVNT_IOTLB_4K_HIT); |
|
FME_EVENT_VTD_SIP(iotlb_2m_hit, VTD_SIP_EVNT_IOTLB_2M_HIT); |
|
FME_EVENT_VTD_SIP(iotlb_1g_hit, VTD_SIP_EVNT_IOTLB_1G_HIT); |
|
FME_EVENT_VTD_SIP(slpwc_l3_hit, VTD_SIP_EVNT_SLPWC_L3_HIT); |
|
FME_EVENT_VTD_SIP(slpwc_l4_hit, VTD_SIP_EVNT_SLPWC_L4_HIT); |
|
FME_EVENT_VTD_SIP(rcc_hit, VTD_SIP_EVNT_RCC_HIT); |
|
FME_EVENT_VTD_SIP(iotlb_4k_miss, VTD_SIP_EVNT_IOTLB_4K_MISS); |
|
FME_EVENT_VTD_SIP(iotlb_2m_miss, VTD_SIP_EVNT_IOTLB_2M_MISS); |
|
FME_EVENT_VTD_SIP(iotlb_1g_miss, VTD_SIP_EVNT_IOTLB_1G_MISS); |
|
FME_EVENT_VTD_SIP(slpwc_l3_miss, VTD_SIP_EVNT_SLPWC_L3_MISS); |
|
FME_EVENT_VTD_SIP(slpwc_l4_miss, VTD_SIP_EVNT_SLPWC_L4_MISS); |
|
FME_EVENT_VTD_SIP(rcc_miss, VTD_SIP_EVNT_RCC_MISS); |
|
|
|
static struct attribute *fme_perf_vtd_sip_events_attrs[] = { |
|
&fme_perf_event_vtd_sip_iotlb_4k_hit.attr.attr, |
|
&fme_perf_event_vtd_sip_iotlb_2m_hit.attr.attr, |
|
&fme_perf_event_vtd_sip_iotlb_1g_hit.attr.attr, |
|
&fme_perf_event_vtd_sip_slpwc_l3_hit.attr.attr, |
|
&fme_perf_event_vtd_sip_slpwc_l4_hit.attr.attr, |
|
&fme_perf_event_vtd_sip_rcc_hit.attr.attr, |
|
&fme_perf_event_vtd_sip_iotlb_4k_miss.attr.attr, |
|
&fme_perf_event_vtd_sip_iotlb_2m_miss.attr.attr, |
|
&fme_perf_event_vtd_sip_iotlb_1g_miss.attr.attr, |
|
&fme_perf_event_vtd_sip_slpwc_l3_miss.attr.attr, |
|
&fme_perf_event_vtd_sip_slpwc_l4_miss.attr.attr, |
|
&fme_perf_event_vtd_sip_rcc_miss.attr.attr, |
|
NULL, |
|
}; |
|
|
|
static const struct attribute_group fme_perf_vtd_sip_events_group = { |
|
.name = "events", |
|
.attrs = fme_perf_vtd_sip_events_attrs, |
|
.is_visible = fme_perf_events_visible, |
|
}; |
|
|
|
static const struct attribute_group *fme_perf_events_groups[] = { |
|
&fme_perf_basic_events_group, |
|
&fme_perf_cache_events_group, |
|
&fme_perf_fabric_events_group, |
|
&fme_perf_vtd_events_group, |
|
&fme_perf_vtd_sip_events_group, |
|
NULL, |
|
}; |
|
|
|
static struct fme_perf_event_ops *get_event_ops(u32 evtype) |
|
{ |
|
if (evtype > FME_EVTYPE_MAX) |
|
return NULL; |
|
|
|
return &fme_perf_event_ops[evtype]; |
|
} |
|
|
|
static void fme_perf_event_destroy(struct perf_event *event) |
|
{ |
|
struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); |
|
struct fme_perf_priv *priv = to_fme_perf_priv(event->pmu); |
|
|
|
if (ops->event_destroy) |
|
ops->event_destroy(priv, event->hw.idx, event->hw.config_base); |
|
} |
|
|
|
static int fme_perf_event_init(struct perf_event *event) |
|
{ |
|
struct fme_perf_priv *priv = to_fme_perf_priv(event->pmu); |
|
struct hw_perf_event *hwc = &event->hw; |
|
struct fme_perf_event_ops *ops; |
|
u32 eventid, evtype, portid; |
|
|
|
/* test the event attr type check for PMU enumeration */ |
|
if (event->attr.type != event->pmu->type) |
|
return -ENOENT; |
|
|
|
/* |
|
* fme counters are shared across all cores. |
|
* Therefore, it does not support per-process mode. |
|
* Also, it does not support event sampling mode. |
|
*/ |
|
if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) |
|
return -EINVAL; |
|
|
|
if (event->cpu < 0) |
|
return -EINVAL; |
|
|
|
if (event->cpu != priv->cpu) |
|
return -EINVAL; |
|
|
|
eventid = get_event(event->attr.config); |
|
portid = get_portid(event->attr.config); |
|
evtype = get_evtype(event->attr.config); |
|
if (evtype > FME_EVTYPE_MAX) |
|
return -EINVAL; |
|
|
|
hwc->event_base = evtype; |
|
hwc->idx = (int)eventid; |
|
hwc->config_base = portid; |
|
|
|
event->destroy = fme_perf_event_destroy; |
|
|
|
dev_dbg(priv->dev, "%s event=0x%x, evtype=0x%x, portid=0x%x,\n", |
|
__func__, eventid, evtype, portid); |
|
|
|
ops = get_event_ops(evtype); |
|
if (ops->event_init) |
|
return ops->event_init(priv, eventid, portid); |
|
|
|
return 0; |
|
} |
|
|
|
static void fme_perf_event_update(struct perf_event *event) |
|
{ |
|
struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); |
|
struct fme_perf_priv *priv = to_fme_perf_priv(event->pmu); |
|
struct hw_perf_event *hwc = &event->hw; |
|
u64 now, prev, delta; |
|
|
|
now = ops->read_counter(priv, (u32)hwc->idx, hwc->config_base); |
|
prev = local64_read(&hwc->prev_count); |
|
delta = now - prev; |
|
|
|
local64_add(delta, &event->count); |
|
} |
|
|
|
static void fme_perf_event_start(struct perf_event *event, int flags) |
|
{ |
|
struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); |
|
struct fme_perf_priv *priv = to_fme_perf_priv(event->pmu); |
|
struct hw_perf_event *hwc = &event->hw; |
|
u64 count; |
|
|
|
count = ops->read_counter(priv, (u32)hwc->idx, hwc->config_base); |
|
local64_set(&hwc->prev_count, count); |
|
} |
|
|
|
static void fme_perf_event_stop(struct perf_event *event, int flags) |
|
{ |
|
fme_perf_event_update(event); |
|
} |
|
|
|
static int fme_perf_event_add(struct perf_event *event, int flags) |
|
{ |
|
if (flags & PERF_EF_START) |
|
fme_perf_event_start(event, flags); |
|
|
|
return 0; |
|
} |
|
|
|
static void fme_perf_event_del(struct perf_event *event, int flags) |
|
{ |
|
fme_perf_event_stop(event, PERF_EF_UPDATE); |
|
} |
|
|
|
static void fme_perf_event_read(struct perf_event *event) |
|
{ |
|
fme_perf_event_update(event); |
|
} |
|
|
|
static void fme_perf_setup_hardware(struct fme_perf_priv *priv) |
|
{ |
|
void __iomem *base = priv->ioaddr; |
|
u64 v; |
|
|
|
/* read and save current working mode for fabric counters */ |
|
v = readq(base + FAB_CTRL); |
|
|
|
if (FIELD_GET(FAB_PORT_FILTER, v) == FAB_PORT_FILTER_DISABLE) |
|
priv->fab_port_id = FME_PORTID_ROOT; |
|
else |
|
priv->fab_port_id = FIELD_GET(FAB_PORT_ID, v); |
|
} |
|
|
|
static int fme_perf_pmu_register(struct platform_device *pdev, |
|
struct fme_perf_priv *priv) |
|
{ |
|
struct pmu *pmu = &priv->pmu; |
|
char *name; |
|
int ret; |
|
|
|
spin_lock_init(&priv->fab_lock); |
|
|
|
fme_perf_setup_hardware(priv); |
|
|
|
pmu->task_ctx_nr = perf_invalid_context; |
|
pmu->attr_groups = fme_perf_groups; |
|
pmu->attr_update = fme_perf_events_groups; |
|
pmu->event_init = fme_perf_event_init; |
|
pmu->add = fme_perf_event_add; |
|
pmu->del = fme_perf_event_del; |
|
pmu->start = fme_perf_event_start; |
|
pmu->stop = fme_perf_event_stop; |
|
pmu->read = fme_perf_event_read; |
|
pmu->capabilities = PERF_PMU_CAP_NO_INTERRUPT | |
|
PERF_PMU_CAP_NO_EXCLUDE; |
|
|
|
name = devm_kasprintf(priv->dev, GFP_KERNEL, "dfl_fme%d", pdev->id); |
|
|
|
ret = perf_pmu_register(pmu, name, -1); |
|
if (ret) |
|
return ret; |
|
|
|
return 0; |
|
} |
|
|
|
static void fme_perf_pmu_unregister(struct fme_perf_priv *priv) |
|
{ |
|
perf_pmu_unregister(&priv->pmu); |
|
} |
|
|
|
static int fme_perf_offline_cpu(unsigned int cpu, struct hlist_node *node) |
|
{ |
|
struct fme_perf_priv *priv; |
|
int target; |
|
|
|
priv = hlist_entry_safe(node, struct fme_perf_priv, node); |
|
|
|
if (cpu != priv->cpu) |
|
return 0; |
|
|
|
target = cpumask_any_but(cpu_online_mask, cpu); |
|
if (target >= nr_cpu_ids) |
|
return 0; |
|
|
|
priv->cpu = target; |
|
perf_pmu_migrate_context(&priv->pmu, cpu, target); |
|
|
|
return 0; |
|
} |
|
|
|
static int fme_perf_init(struct platform_device *pdev, |
|
struct dfl_feature *feature) |
|
{ |
|
struct fme_perf_priv *priv; |
|
int ret; |
|
|
|
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
|
if (!priv) |
|
return -ENOMEM; |
|
|
|
priv->dev = &pdev->dev; |
|
priv->ioaddr = feature->ioaddr; |
|
priv->id = feature->id; |
|
priv->cpu = raw_smp_processor_id(); |
|
|
|
ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, |
|
"perf/fpga/dfl_fme:online", |
|
NULL, fme_perf_offline_cpu); |
|
if (ret < 0) |
|
return ret; |
|
|
|
priv->cpuhp_state = ret; |
|
|
|
/* Register the pmu instance for cpu hotplug */ |
|
ret = cpuhp_state_add_instance_nocalls(priv->cpuhp_state, &priv->node); |
|
if (ret) |
|
goto cpuhp_instance_err; |
|
|
|
ret = fme_perf_pmu_register(pdev, priv); |
|
if (ret) |
|
goto pmu_register_err; |
|
|
|
feature->priv = priv; |
|
return 0; |
|
|
|
pmu_register_err: |
|
cpuhp_state_remove_instance_nocalls(priv->cpuhp_state, &priv->node); |
|
cpuhp_instance_err: |
|
cpuhp_remove_multi_state(priv->cpuhp_state); |
|
return ret; |
|
} |
|
|
|
static void fme_perf_uinit(struct platform_device *pdev, |
|
struct dfl_feature *feature) |
|
{ |
|
struct fme_perf_priv *priv = feature->priv; |
|
|
|
fme_perf_pmu_unregister(priv); |
|
cpuhp_state_remove_instance_nocalls(priv->cpuhp_state, &priv->node); |
|
cpuhp_remove_multi_state(priv->cpuhp_state); |
|
} |
|
|
|
const struct dfl_feature_id fme_perf_id_table[] = { |
|
{.id = FME_FEATURE_ID_GLOBAL_IPERF,}, |
|
{.id = FME_FEATURE_ID_GLOBAL_DPERF,}, |
|
{0,} |
|
}; |
|
|
|
const struct dfl_feature_ops fme_perf_ops = { |
|
.init = fme_perf_init, |
|
.uinit = fme_perf_uinit, |
|
};
|
|
|