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235 lines
6.5 KiB
235 lines
6.5 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2008 Marvell International Ltd. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/sched.h> |
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#include <linux/init.h> |
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#include <linux/cpufreq.h> |
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#include <linux/soc/pxa/cpu.h> |
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#include <linux/clk/pxa.h> |
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#include <linux/slab.h> |
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#include <linux/io.h> |
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#define HSS_104M (0) |
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#define HSS_156M (1) |
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#define HSS_208M (2) |
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#define HSS_312M (3) |
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#define SMCFS_78M (0) |
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#define SMCFS_104M (2) |
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#define SMCFS_208M (5) |
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#define SFLFS_104M (0) |
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#define SFLFS_156M (1) |
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#define SFLFS_208M (2) |
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#define SFLFS_312M (3) |
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#define XSPCLK_156M (0) |
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#define XSPCLK_NONE (3) |
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#define DMCFS_26M (0) |
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#define DMCFS_260M (3) |
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#define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ |
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#define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */ |
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#define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */ |
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#define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */ |
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#define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */ |
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#define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */ |
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#define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */ |
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#define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */ |
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#define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */ |
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#define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */ |
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#define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */ |
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#define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */ |
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#define ACCR_SMCFS(x) (((x) & 0x7) << 23) |
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#define ACCR_SFLFS(x) (((x) & 0x3) << 18) |
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#define ACCR_XSPCLK(x) (((x) & 0x3) << 16) |
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#define ACCR_HSS(x) (((x) & 0x3) << 14) |
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#define ACCR_DMCFS(x) (((x) & 0x3) << 12) |
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#define ACCR_XN(x) (((x) & 0x7) << 8) |
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#define ACCR_XL(x) ((x) & 0x1f) |
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struct pxa3xx_freq_info { |
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unsigned int cpufreq_mhz; |
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unsigned int core_xl : 5; |
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unsigned int core_xn : 3; |
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unsigned int hss : 2; |
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unsigned int dmcfs : 2; |
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unsigned int smcfs : 3; |
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unsigned int sflfs : 2; |
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unsigned int df_clkdiv : 3; |
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int vcc_core; /* in mV */ |
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int vcc_sram; /* in mV */ |
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}; |
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#define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \ |
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{ \ |
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.cpufreq_mhz = cpufreq, \ |
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.core_xl = _xl, \ |
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.core_xn = _xn, \ |
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.hss = HSS_##_hss##M, \ |
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.dmcfs = DMCFS_##_dmc##M, \ |
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.smcfs = SMCFS_##_smc##M, \ |
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.sflfs = SFLFS_##_sfl##M, \ |
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.df_clkdiv = _dfi, \ |
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.vcc_core = vcore, \ |
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.vcc_sram = vsram, \ |
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} |
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static struct pxa3xx_freq_info pxa300_freqs[] = { |
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/* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */ |
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OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */ |
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OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */ |
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OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */ |
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OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */ |
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}; |
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static struct pxa3xx_freq_info pxa320_freqs[] = { |
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/* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */ |
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OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */ |
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OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */ |
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OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */ |
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OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */ |
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OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */ |
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}; |
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static unsigned int pxa3xx_freqs_num; |
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static struct pxa3xx_freq_info *pxa3xx_freqs; |
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static struct cpufreq_frequency_table *pxa3xx_freqs_table; |
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static int setup_freqs_table(struct cpufreq_policy *policy, |
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struct pxa3xx_freq_info *freqs, int num) |
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{ |
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struct cpufreq_frequency_table *table; |
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int i; |
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table = kcalloc(num + 1, sizeof(*table), GFP_KERNEL); |
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if (table == NULL) |
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return -ENOMEM; |
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for (i = 0; i < num; i++) { |
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table[i].driver_data = i; |
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table[i].frequency = freqs[i].cpufreq_mhz * 1000; |
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} |
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table[num].driver_data = i; |
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table[num].frequency = CPUFREQ_TABLE_END; |
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pxa3xx_freqs = freqs; |
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pxa3xx_freqs_num = num; |
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pxa3xx_freqs_table = table; |
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policy->freq_table = table; |
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return 0; |
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} |
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static void __update_core_freq(struct pxa3xx_freq_info *info) |
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{ |
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u32 mask, disable, enable, xclkcfg; |
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mask = ACCR_XN_MASK | ACCR_XL_MASK; |
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disable = mask | ACCR_XSPCLK_MASK; |
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enable = ACCR_XN(info->core_xn) | ACCR_XL(info->core_xl); |
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/* No clock until core PLL is re-locked */ |
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enable |= ACCR_XSPCLK(XSPCLK_NONE); |
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xclkcfg = (info->core_xn == 2) ? 0x3 : 0x2; /* turbo bit */ |
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pxa3xx_clk_update_accr(disable, enable, xclkcfg, mask); |
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} |
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static void __update_bus_freq(struct pxa3xx_freq_info *info) |
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{ |
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u32 mask, disable, enable; |
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mask = ACCR_SMCFS_MASK | ACCR_SFLFS_MASK | ACCR_HSS_MASK | |
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ACCR_DMCFS_MASK; |
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disable = mask; |
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enable = ACCR_SMCFS(info->smcfs) | ACCR_SFLFS(info->sflfs) | |
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ACCR_HSS(info->hss) | ACCR_DMCFS(info->dmcfs); |
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pxa3xx_clk_update_accr(disable, enable, 0, mask); |
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} |
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static unsigned int pxa3xx_cpufreq_get(unsigned int cpu) |
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{ |
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return pxa3xx_get_clk_frequency_khz(0); |
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} |
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static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy, unsigned int index) |
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{ |
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struct pxa3xx_freq_info *next; |
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unsigned long flags; |
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if (policy->cpu != 0) |
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return -EINVAL; |
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next = &pxa3xx_freqs[index]; |
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local_irq_save(flags); |
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__update_core_freq(next); |
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__update_bus_freq(next); |
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local_irq_restore(flags); |
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return 0; |
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} |
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static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy) |
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{ |
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int ret = -EINVAL; |
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/* set default policy and cpuinfo */ |
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policy->min = policy->cpuinfo.min_freq = 104000; |
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policy->max = policy->cpuinfo.max_freq = |
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(cpu_is_pxa320()) ? 806000 : 624000; |
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policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ |
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if (cpu_is_pxa300() || cpu_is_pxa310()) |
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ret = setup_freqs_table(policy, pxa300_freqs, |
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ARRAY_SIZE(pxa300_freqs)); |
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if (cpu_is_pxa320()) |
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ret = setup_freqs_table(policy, pxa320_freqs, |
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ARRAY_SIZE(pxa320_freqs)); |
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if (ret) { |
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pr_err("failed to setup frequency table\n"); |
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return ret; |
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} |
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pr_info("CPUFREQ support for PXA3xx initialized\n"); |
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return 0; |
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} |
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static struct cpufreq_driver pxa3xx_cpufreq_driver = { |
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.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
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.verify = cpufreq_generic_frequency_table_verify, |
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.target_index = pxa3xx_cpufreq_set, |
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.init = pxa3xx_cpufreq_init, |
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.get = pxa3xx_cpufreq_get, |
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.name = "pxa3xx-cpufreq", |
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}; |
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static int __init cpufreq_init(void) |
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{ |
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if (cpu_is_pxa3xx()) |
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return cpufreq_register_driver(&pxa3xx_cpufreq_driver); |
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return 0; |
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} |
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module_init(cpufreq_init); |
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static void __exit cpufreq_exit(void) |
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{ |
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cpufreq_unregister_driver(&pxa3xx_cpufreq_driver); |
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} |
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module_exit(cpufreq_exit); |
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MODULE_DESCRIPTION("CPU frequency scaling driver for PXA3xx"); |
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MODULE_LICENSE("GPL");
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