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446 lines
10 KiB
446 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright 2014 Linaro Ltd. |
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* Copyright (C) 2014 ZTE Corporation. |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/err.h> |
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#include <linux/gcd.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <asm/div64.h> |
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#include "clk.h" |
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#define to_clk_zx_pll(_hw) container_of(_hw, struct clk_zx_pll, hw) |
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#define to_clk_zx_audio(_hw) container_of(_hw, struct clk_zx_audio, hw) |
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#define CFG0_CFG1_OFFSET 4 |
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#define LOCK_FLAG 30 |
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#define POWER_DOWN 31 |
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static int rate_to_idx(struct clk_zx_pll *zx_pll, unsigned long rate) |
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{ |
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const struct zx_pll_config *config = zx_pll->lookup_table; |
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int i; |
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for (i = 0; i < zx_pll->count; i++) { |
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if (config[i].rate > rate) |
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return i > 0 ? i - 1 : 0; |
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if (config[i].rate == rate) |
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return i; |
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} |
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return i - 1; |
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} |
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static int hw_to_idx(struct clk_zx_pll *zx_pll) |
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{ |
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const struct zx_pll_config *config = zx_pll->lookup_table; |
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u32 hw_cfg0, hw_cfg1; |
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int i; |
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hw_cfg0 = readl_relaxed(zx_pll->reg_base); |
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hw_cfg1 = readl_relaxed(zx_pll->reg_base + CFG0_CFG1_OFFSET); |
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/* For matching the value in lookup table */ |
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hw_cfg0 &= ~BIT(zx_pll->lock_bit); |
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/* Check availability of pd_bit */ |
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if (zx_pll->pd_bit < 32) |
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hw_cfg0 |= BIT(zx_pll->pd_bit); |
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for (i = 0; i < zx_pll->count; i++) { |
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if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1) |
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return i; |
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} |
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return -EINVAL; |
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} |
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static unsigned long zx_pll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw); |
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int idx; |
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idx = hw_to_idx(zx_pll); |
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if (unlikely(idx == -EINVAL)) |
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return 0; |
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return zx_pll->lookup_table[idx].rate; |
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} |
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static long zx_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *prate) |
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{ |
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struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw); |
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int idx; |
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idx = rate_to_idx(zx_pll, rate); |
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return zx_pll->lookup_table[idx].rate; |
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} |
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static int zx_pll_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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/* Assume current cpu is not running on current PLL */ |
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struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw); |
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const struct zx_pll_config *config; |
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int idx; |
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idx = rate_to_idx(zx_pll, rate); |
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config = &zx_pll->lookup_table[idx]; |
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writel_relaxed(config->cfg0, zx_pll->reg_base); |
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writel_relaxed(config->cfg1, zx_pll->reg_base + CFG0_CFG1_OFFSET); |
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return 0; |
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} |
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static int zx_pll_enable(struct clk_hw *hw) |
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{ |
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struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw); |
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u32 reg; |
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/* If pd_bit is not available, simply return success. */ |
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if (zx_pll->pd_bit > 31) |
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return 0; |
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reg = readl_relaxed(zx_pll->reg_base); |
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writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base); |
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return readl_relaxed_poll_timeout(zx_pll->reg_base, reg, |
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reg & BIT(zx_pll->lock_bit), 0, 100); |
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} |
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static void zx_pll_disable(struct clk_hw *hw) |
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{ |
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struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw); |
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u32 reg; |
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if (zx_pll->pd_bit > 31) |
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return; |
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reg = readl_relaxed(zx_pll->reg_base); |
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writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base); |
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} |
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static int zx_pll_is_enabled(struct clk_hw *hw) |
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{ |
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struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw); |
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u32 reg; |
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reg = readl_relaxed(zx_pll->reg_base); |
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return !(reg & BIT(zx_pll->pd_bit)); |
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} |
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const struct clk_ops zx_pll_ops = { |
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.recalc_rate = zx_pll_recalc_rate, |
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.round_rate = zx_pll_round_rate, |
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.set_rate = zx_pll_set_rate, |
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.enable = zx_pll_enable, |
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.disable = zx_pll_disable, |
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.is_enabled = zx_pll_is_enabled, |
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}; |
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EXPORT_SYMBOL(zx_pll_ops); |
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struct clk *clk_register_zx_pll(const char *name, const char *parent_name, |
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unsigned long flags, void __iomem *reg_base, |
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const struct zx_pll_config *lookup_table, |
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int count, spinlock_t *lock) |
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{ |
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struct clk_zx_pll *zx_pll; |
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struct clk *clk; |
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struct clk_init_data init; |
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zx_pll = kzalloc(sizeof(*zx_pll), GFP_KERNEL); |
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if (!zx_pll) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.ops = &zx_pll_ops; |
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init.flags = flags; |
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init.parent_names = parent_name ? &parent_name : NULL; |
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init.num_parents = parent_name ? 1 : 0; |
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zx_pll->reg_base = reg_base; |
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zx_pll->lookup_table = lookup_table; |
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zx_pll->count = count; |
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zx_pll->lock_bit = LOCK_FLAG; |
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zx_pll->pd_bit = POWER_DOWN; |
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zx_pll->lock = lock; |
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zx_pll->hw.init = &init; |
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clk = clk_register(NULL, &zx_pll->hw); |
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if (IS_ERR(clk)) |
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kfree(zx_pll); |
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return clk; |
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} |
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#define BPAR 1000000 |
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static u32 calc_reg(u32 parent_rate, u32 rate) |
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{ |
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u32 sel, integ, fra_div, tmp; |
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u64 tmp64 = (u64)parent_rate * BPAR; |
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do_div(tmp64, rate); |
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integ = (u32)tmp64 / BPAR; |
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integ = integ >> 1; |
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tmp = (u32)tmp64 % BPAR; |
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sel = tmp / BPAR; |
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tmp = tmp % BPAR; |
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fra_div = tmp * 0xff / BPAR; |
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tmp = (sel << 24) | (integ << 16) | (0xff << 8) | fra_div; |
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/* Set I2S integer divider as 1. This bit is reserved for SPDIF |
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* and do no harm. |
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*/ |
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tmp |= BIT(28); |
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return tmp; |
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} |
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static u32 calc_rate(u32 reg, u32 parent_rate) |
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{ |
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u32 sel, integ, fra_div, tmp; |
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u64 tmp64 = (u64)parent_rate * BPAR; |
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tmp = reg; |
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sel = (tmp >> 24) & BIT(0); |
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integ = (tmp >> 16) & 0xff; |
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fra_div = tmp & 0xff; |
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tmp = fra_div * BPAR; |
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tmp = tmp / 0xff; |
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tmp += sel * BPAR; |
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tmp += 2 * integ * BPAR; |
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do_div(tmp64, tmp); |
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return (u32)tmp64; |
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} |
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static unsigned long zx_audio_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw); |
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u32 reg; |
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reg = readl_relaxed(zx_audio->reg_base); |
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return calc_rate(reg, parent_rate); |
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} |
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static long zx_audio_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *prate) |
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{ |
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u32 reg; |
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if (rate * 2 > *prate) |
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return -EINVAL; |
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reg = calc_reg(*prate, rate); |
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return calc_rate(reg, *prate); |
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} |
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static int zx_audio_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw); |
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u32 reg; |
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reg = calc_reg(parent_rate, rate); |
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writel_relaxed(reg, zx_audio->reg_base); |
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return 0; |
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} |
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#define ZX_AUDIO_EN BIT(25) |
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static int zx_audio_enable(struct clk_hw *hw) |
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{ |
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struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw); |
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u32 reg; |
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reg = readl_relaxed(zx_audio->reg_base); |
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writel_relaxed(reg & ~ZX_AUDIO_EN, zx_audio->reg_base); |
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return 0; |
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} |
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static void zx_audio_disable(struct clk_hw *hw) |
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{ |
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struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw); |
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u32 reg; |
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reg = readl_relaxed(zx_audio->reg_base); |
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writel_relaxed(reg | ZX_AUDIO_EN, zx_audio->reg_base); |
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} |
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static const struct clk_ops zx_audio_ops = { |
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.recalc_rate = zx_audio_recalc_rate, |
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.round_rate = zx_audio_round_rate, |
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.set_rate = zx_audio_set_rate, |
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.enable = zx_audio_enable, |
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.disable = zx_audio_disable, |
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}; |
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struct clk *clk_register_zx_audio(const char *name, |
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const char * const parent_name, |
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unsigned long flags, |
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void __iomem *reg_base) |
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{ |
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struct clk_zx_audio *zx_audio; |
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struct clk *clk; |
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struct clk_init_data init; |
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zx_audio = kzalloc(sizeof(*zx_audio), GFP_KERNEL); |
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if (!zx_audio) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.ops = &zx_audio_ops; |
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init.flags = flags; |
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init.parent_names = parent_name ? &parent_name : NULL; |
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init.num_parents = parent_name ? 1 : 0; |
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zx_audio->reg_base = reg_base; |
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zx_audio->hw.init = &init; |
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clk = clk_register(NULL, &zx_audio->hw); |
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if (IS_ERR(clk)) |
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kfree(zx_audio); |
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return clk; |
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} |
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#define CLK_AUDIO_DIV_FRAC BIT(0) |
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#define CLK_AUDIO_DIV_INT BIT(1) |
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#define CLK_AUDIO_DIV_UNCOMMON BIT(1) |
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#define CLK_AUDIO_DIV_FRAC_NSHIFT 16 |
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#define CLK_AUDIO_DIV_INT_FRAC_RE BIT(16) |
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#define CLK_AUDIO_DIV_INT_FRAC_MAX (0xffff) |
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#define CLK_AUDIO_DIV_INT_FRAC_MIN (0x2) |
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#define CLK_AUDIO_DIV_INT_INT_SHIFT 24 |
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#define CLK_AUDIO_DIV_INT_INT_WIDTH 4 |
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struct zx_clk_audio_div_table { |
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unsigned long rate; |
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unsigned int int_reg; |
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unsigned int frac_reg; |
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}; |
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#define to_clk_zx_audio_div(_hw) container_of(_hw, struct clk_zx_audio_divider, hw) |
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static unsigned long audio_calc_rate(struct clk_zx_audio_divider *audio_div, |
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u32 reg_frac, u32 reg_int, |
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unsigned long parent_rate) |
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{ |
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unsigned long rate, m, n; |
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m = reg_frac & 0xffff; |
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n = (reg_frac >> 16) & 0xffff; |
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m = (reg_int & 0xffff) * n + m; |
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rate = (parent_rate * n) / m; |
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return rate; |
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} |
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static void audio_calc_reg(struct clk_zx_audio_divider *audio_div, |
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struct zx_clk_audio_div_table *div_table, |
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unsigned long rate, unsigned long parent_rate) |
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{ |
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unsigned int reg_int, reg_frac; |
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unsigned long m, n, div; |
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reg_int = parent_rate / rate; |
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if (reg_int > CLK_AUDIO_DIV_INT_FRAC_MAX) |
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reg_int = CLK_AUDIO_DIV_INT_FRAC_MAX; |
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else if (reg_int < CLK_AUDIO_DIV_INT_FRAC_MIN) |
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reg_int = 0; |
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m = parent_rate - rate * reg_int; |
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n = rate; |
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div = gcd(m, n); |
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m = m / div; |
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n = n / div; |
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if ((m >> 16) || (n >> 16)) { |
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if (m > n) { |
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n = n * 0xffff / m; |
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m = 0xffff; |
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} else { |
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m = m * 0xffff / n; |
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n = 0xffff; |
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} |
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} |
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reg_frac = m | (n << 16); |
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div_table->rate = parent_rate * n / (reg_int * n + m); |
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div_table->int_reg = reg_int; |
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div_table->frac_reg = reg_frac; |
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} |
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static unsigned long zx_audio_div_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw); |
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u32 reg_frac, reg_int; |
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reg_frac = readl_relaxed(zx_audio_div->reg_base); |
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reg_int = readl_relaxed(zx_audio_div->reg_base + 0x4); |
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return audio_calc_rate(zx_audio_div, reg_frac, reg_int, parent_rate); |
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} |
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static long zx_audio_div_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *prate) |
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{ |
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struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw); |
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struct zx_clk_audio_div_table divt; |
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audio_calc_reg(zx_audio_div, &divt, rate, *prate); |
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return audio_calc_rate(zx_audio_div, divt.frac_reg, divt.int_reg, *prate); |
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} |
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static int zx_audio_div_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw); |
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struct zx_clk_audio_div_table divt; |
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unsigned int val; |
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audio_calc_reg(zx_audio_div, &divt, rate, parent_rate); |
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if (divt.rate != rate) |
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pr_debug("the real rate is:%ld", divt.rate); |
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writel_relaxed(divt.frac_reg, zx_audio_div->reg_base); |
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val = readl_relaxed(zx_audio_div->reg_base + 0x4); |
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val &= ~0xffff; |
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val |= divt.int_reg | CLK_AUDIO_DIV_INT_FRAC_RE; |
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writel_relaxed(val, zx_audio_div->reg_base + 0x4); |
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mdelay(1); |
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val = readl_relaxed(zx_audio_div->reg_base + 0x4); |
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val &= ~CLK_AUDIO_DIV_INT_FRAC_RE; |
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writel_relaxed(val, zx_audio_div->reg_base + 0x4); |
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return 0; |
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} |
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const struct clk_ops zx_audio_div_ops = { |
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.recalc_rate = zx_audio_div_recalc_rate, |
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.round_rate = zx_audio_div_round_rate, |
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.set_rate = zx_audio_div_set_rate, |
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};
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