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186 lines
4.3 KiB
186 lines
4.3 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/io.h> |
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#include <linux/err.h> |
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#include <linux/slab.h> |
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#include <linux/clk-provider.h> |
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#include "clk.h" |
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#define pll_out_override(p) (BIT((p->shift - 6))) |
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#define div_mask(d) ((1 << (d->width)) - 1) |
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#define get_mul(d) (1 << d->frac_width) |
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#define get_max_div(d) div_mask(d) |
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#define PERIPH_CLK_UART_DIV_ENB BIT(24) |
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static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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int div; |
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div = div_frac_get(rate, parent_rate, divider->width, |
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divider->frac_width, divider->flags); |
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if (div < 0) |
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return 0; |
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return div; |
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} |
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static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); |
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u32 reg; |
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int div, mul; |
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u64 rate = parent_rate; |
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reg = readl_relaxed(divider->reg); |
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if ((divider->flags & TEGRA_DIVIDER_UART) && |
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!(reg & PERIPH_CLK_UART_DIV_ENB)) |
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return rate; |
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div = (reg >> divider->shift) & div_mask(divider); |
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mul = get_mul(divider); |
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div += mul; |
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rate *= mul; |
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rate += div - 1; |
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do_div(rate, div); |
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return rate; |
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} |
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static long clk_frac_div_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *prate) |
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{ |
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struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); |
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int div, mul; |
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unsigned long output_rate = *prate; |
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if (!rate) |
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return output_rate; |
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div = get_div(divider, rate, output_rate); |
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if (div < 0) |
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return *prate; |
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mul = get_mul(divider); |
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return DIV_ROUND_UP(output_rate * mul, div + mul); |
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} |
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static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); |
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int div; |
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unsigned long flags = 0; |
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u32 val; |
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div = get_div(divider, rate, parent_rate); |
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if (div < 0) |
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return div; |
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if (divider->lock) |
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spin_lock_irqsave(divider->lock, flags); |
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val = readl_relaxed(divider->reg); |
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val &= ~(div_mask(divider) << divider->shift); |
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val |= div << divider->shift; |
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if (divider->flags & TEGRA_DIVIDER_UART) { |
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if (div) |
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val |= PERIPH_CLK_UART_DIV_ENB; |
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else |
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val &= ~PERIPH_CLK_UART_DIV_ENB; |
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} |
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if (divider->flags & TEGRA_DIVIDER_FIXED) |
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val |= pll_out_override(divider); |
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writel_relaxed(val, divider->reg); |
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if (divider->lock) |
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spin_unlock_irqrestore(divider->lock, flags); |
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return 0; |
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} |
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static void clk_divider_restore_context(struct clk_hw *hw) |
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{ |
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struct clk_hw *parent = clk_hw_get_parent(hw); |
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unsigned long parent_rate = clk_hw_get_rate(parent); |
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unsigned long rate = clk_hw_get_rate(hw); |
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if (clk_frac_div_set_rate(hw, rate, parent_rate) < 0) |
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WARN_ON(1); |
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} |
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const struct clk_ops tegra_clk_frac_div_ops = { |
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.recalc_rate = clk_frac_div_recalc_rate, |
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.set_rate = clk_frac_div_set_rate, |
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.round_rate = clk_frac_div_round_rate, |
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.restore_context = clk_divider_restore_context, |
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}; |
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struct clk *tegra_clk_register_divider(const char *name, |
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const char *parent_name, void __iomem *reg, |
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unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, |
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u8 frac_width, spinlock_t *lock) |
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{ |
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struct tegra_clk_frac_div *divider; |
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struct clk *clk; |
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struct clk_init_data init; |
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divider = kzalloc(sizeof(*divider), GFP_KERNEL); |
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if (!divider) { |
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pr_err("%s: could not allocate fractional divider clk\n", |
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__func__); |
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return ERR_PTR(-ENOMEM); |
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} |
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init.name = name; |
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init.ops = &tegra_clk_frac_div_ops; |
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init.flags = flags; |
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init.parent_names = parent_name ? &parent_name : NULL; |
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init.num_parents = parent_name ? 1 : 0; |
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divider->reg = reg; |
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divider->shift = shift; |
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divider->width = width; |
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divider->frac_width = frac_width; |
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divider->lock = lock; |
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divider->flags = clk_divider_flags; |
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/* Data in .init is copied by clk_register(), so stack variable OK */ |
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divider->hw.init = &init; |
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clk = clk_register(NULL, ÷r->hw); |
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if (IS_ERR(clk)) |
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kfree(divider); |
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return clk; |
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} |
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static const struct clk_div_table mc_div_table[] = { |
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{ .val = 0, .div = 2 }, |
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{ .val = 1, .div = 1 }, |
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{ .val = 0, .div = 0 }, |
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}; |
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struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, |
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void __iomem *reg, spinlock_t *lock) |
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{ |
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return clk_register_divider_table(NULL, name, parent_name, |
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CLK_IS_CRITICAL, |
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reg, 16, 1, CLK_DIVIDER_READ_ONLY, |
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mc_div_table, lock); |
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}
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