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382 lines
9.5 KiB
382 lines
9.5 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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// |
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// Copyright (c) 2021 Samuel Holland <[email protected]> |
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// |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/clk/sunxi-ng.h> |
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#include "ccu_common.h" |
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#include "ccu_div.h" |
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#include "ccu_gate.h" |
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#include "ccu_mux.h" |
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#include "ccu-sun6i-rtc.h" |
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#define IOSC_ACCURACY 300000000 /* 30% */ |
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#define IOSC_RATE 16000000 |
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#define LOSC_RATE 32768 |
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#define LOSC_RATE_SHIFT 15 |
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#define LOSC_CTRL_REG 0x0 |
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#define LOSC_CTRL_KEY 0x16aa0000 |
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#define IOSC_32K_CLK_DIV_REG 0x8 |
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#define IOSC_32K_CLK_DIV GENMASK(4, 0) |
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#define IOSC_32K_PRE_DIV 32 |
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#define IOSC_CLK_CALI_REG 0xc |
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#define IOSC_CLK_CALI_DIV_ONES 22 |
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#define IOSC_CLK_CALI_EN BIT(1) |
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#define IOSC_CLK_CALI_SRC_SEL BIT(0) |
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#define LOSC_OUT_GATING_REG 0x60 |
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#define DCXO_CTRL_REG 0x160 |
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#define DCXO_CTRL_CLK16M_RC_EN BIT(0) |
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struct sun6i_rtc_match_data { |
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bool have_ext_osc32k : 1; |
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bool have_iosc_calibration : 1; |
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bool rtc_32k_single_parent : 1; |
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const struct clk_parent_data *osc32k_fanout_parents; |
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u8 osc32k_fanout_nparents; |
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}; |
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static bool have_iosc_calibration; |
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static int ccu_iosc_enable(struct clk_hw *hw) |
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{ |
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struct ccu_common *cm = hw_to_ccu_common(hw); |
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return ccu_gate_helper_enable(cm, DCXO_CTRL_CLK16M_RC_EN); |
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} |
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static void ccu_iosc_disable(struct clk_hw *hw) |
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{ |
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struct ccu_common *cm = hw_to_ccu_common(hw); |
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return ccu_gate_helper_disable(cm, DCXO_CTRL_CLK16M_RC_EN); |
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} |
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static int ccu_iosc_is_enabled(struct clk_hw *hw) |
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{ |
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struct ccu_common *cm = hw_to_ccu_common(hw); |
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return ccu_gate_helper_is_enabled(cm, DCXO_CTRL_CLK16M_RC_EN); |
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} |
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static unsigned long ccu_iosc_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct ccu_common *cm = hw_to_ccu_common(hw); |
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if (have_iosc_calibration) { |
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u32 reg = readl(cm->base + IOSC_CLK_CALI_REG); |
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/* |
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* Recover the IOSC frequency by shifting the ones place of |
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* (fixed-point divider * 32768) into bit zero. |
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*/ |
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if (reg & IOSC_CLK_CALI_EN) |
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return reg >> (IOSC_CLK_CALI_DIV_ONES - LOSC_RATE_SHIFT); |
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} |
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return IOSC_RATE; |
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} |
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static unsigned long ccu_iosc_recalc_accuracy(struct clk_hw *hw, |
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unsigned long parent_accuracy) |
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{ |
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return IOSC_ACCURACY; |
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} |
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static const struct clk_ops ccu_iosc_ops = { |
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.enable = ccu_iosc_enable, |
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.disable = ccu_iosc_disable, |
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.is_enabled = ccu_iosc_is_enabled, |
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.recalc_rate = ccu_iosc_recalc_rate, |
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.recalc_accuracy = ccu_iosc_recalc_accuracy, |
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}; |
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static struct ccu_common iosc_clk = { |
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.reg = DCXO_CTRL_REG, |
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.hw.init = CLK_HW_INIT_NO_PARENT("iosc", &ccu_iosc_ops, |
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CLK_GET_RATE_NOCACHE), |
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}; |
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static int ccu_iosc_32k_prepare(struct clk_hw *hw) |
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{ |
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struct ccu_common *cm = hw_to_ccu_common(hw); |
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u32 val; |
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if (!have_iosc_calibration) |
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return 0; |
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val = readl(cm->base + IOSC_CLK_CALI_REG); |
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writel(val | IOSC_CLK_CALI_EN | IOSC_CLK_CALI_SRC_SEL, |
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cm->base + IOSC_CLK_CALI_REG); |
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return 0; |
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} |
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static void ccu_iosc_32k_unprepare(struct clk_hw *hw) |
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{ |
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struct ccu_common *cm = hw_to_ccu_common(hw); |
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u32 val; |
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if (!have_iosc_calibration) |
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return; |
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val = readl(cm->base + IOSC_CLK_CALI_REG); |
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writel(val & ~(IOSC_CLK_CALI_EN | IOSC_CLK_CALI_SRC_SEL), |
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cm->base + IOSC_CLK_CALI_REG); |
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} |
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static unsigned long ccu_iosc_32k_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct ccu_common *cm = hw_to_ccu_common(hw); |
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u32 val; |
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if (have_iosc_calibration) { |
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val = readl(cm->base + IOSC_CLK_CALI_REG); |
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/* Assume the calibrated 32k clock is accurate. */ |
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if (val & IOSC_CLK_CALI_SRC_SEL) |
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return LOSC_RATE; |
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} |
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val = readl(cm->base + IOSC_32K_CLK_DIV_REG) & IOSC_32K_CLK_DIV; |
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return parent_rate / IOSC_32K_PRE_DIV / (val + 1); |
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} |
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static unsigned long ccu_iosc_32k_recalc_accuracy(struct clk_hw *hw, |
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unsigned long parent_accuracy) |
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{ |
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struct ccu_common *cm = hw_to_ccu_common(hw); |
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u32 val; |
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if (have_iosc_calibration) { |
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val = readl(cm->base + IOSC_CLK_CALI_REG); |
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/* Assume the calibrated 32k clock is accurate. */ |
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if (val & IOSC_CLK_CALI_SRC_SEL) |
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return 0; |
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} |
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return parent_accuracy; |
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} |
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static const struct clk_ops ccu_iosc_32k_ops = { |
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.prepare = ccu_iosc_32k_prepare, |
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.unprepare = ccu_iosc_32k_unprepare, |
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.recalc_rate = ccu_iosc_32k_recalc_rate, |
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.recalc_accuracy = ccu_iosc_32k_recalc_accuracy, |
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}; |
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static struct ccu_common iosc_32k_clk = { |
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.hw.init = CLK_HW_INIT_HW("iosc-32k", &iosc_clk.hw, |
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&ccu_iosc_32k_ops, |
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CLK_GET_RATE_NOCACHE), |
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}; |
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static const struct clk_hw *ext_osc32k[] = { NULL }; /* updated during probe */ |
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static SUNXI_CCU_GATE_HWS(ext_osc32k_gate_clk, "ext-osc32k-gate", |
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ext_osc32k, 0x0, BIT(4), 0); |
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static const struct clk_hw *osc32k_parents[] = { |
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&iosc_32k_clk.hw, |
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&ext_osc32k_gate_clk.common.hw |
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}; |
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static struct clk_init_data osc32k_init_data = { |
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.name = "osc32k", |
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.ops = &ccu_mux_ops, |
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.parent_hws = osc32k_parents, |
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.num_parents = ARRAY_SIZE(osc32k_parents), /* updated during probe */ |
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}; |
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static struct ccu_mux osc32k_clk = { |
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.mux = _SUNXI_CCU_MUX(0, 1), |
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.common = { |
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.reg = LOSC_CTRL_REG, |
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.features = CCU_FEATURE_KEY_FIELD, |
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.hw.init = &osc32k_init_data, |
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}, |
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}; |
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/* This falls back to the global name for fwnodes without a named reference. */ |
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static const struct clk_parent_data osc24M[] = { |
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{ .fw_name = "hosc", .name = "osc24M" } |
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}; |
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static struct ccu_gate osc24M_32k_clk = { |
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.enable = BIT(16), |
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.common = { |
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.reg = LOSC_OUT_GATING_REG, |
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.prediv = 750, |
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.features = CCU_FEATURE_ALL_PREDIV, |
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.hw.init = CLK_HW_INIT_PARENTS_DATA("osc24M-32k", osc24M, |
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&ccu_gate_ops, 0), |
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}, |
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}; |
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static const struct clk_hw *rtc_32k_parents[] = { |
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&osc32k_clk.common.hw, |
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&osc24M_32k_clk.common.hw |
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}; |
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static struct clk_init_data rtc_32k_init_data = { |
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.name = "rtc-32k", |
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.ops = &ccu_mux_ops, |
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.parent_hws = rtc_32k_parents, |
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.num_parents = ARRAY_SIZE(rtc_32k_parents), /* updated during probe */ |
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.flags = CLK_IS_CRITICAL, |
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}; |
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static struct ccu_mux rtc_32k_clk = { |
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.mux = _SUNXI_CCU_MUX(1, 1), |
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.common = { |
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.reg = LOSC_CTRL_REG, |
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.features = CCU_FEATURE_KEY_FIELD, |
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.hw.init = &rtc_32k_init_data, |
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}, |
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}; |
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static struct clk_init_data osc32k_fanout_init_data = { |
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.name = "osc32k-fanout", |
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.ops = &ccu_mux_ops, |
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/* parents are set during probe */ |
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}; |
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static struct ccu_mux osc32k_fanout_clk = { |
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.enable = BIT(0), |
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.mux = _SUNXI_CCU_MUX(1, 2), |
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.common = { |
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.reg = LOSC_OUT_GATING_REG, |
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.hw.init = &osc32k_fanout_init_data, |
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}, |
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}; |
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static struct ccu_common *sun6i_rtc_ccu_clks[] = { |
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&iosc_clk, |
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&iosc_32k_clk, |
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&ext_osc32k_gate_clk.common, |
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&osc32k_clk.common, |
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&osc24M_32k_clk.common, |
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&rtc_32k_clk.common, |
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&osc32k_fanout_clk.common, |
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}; |
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static struct clk_hw_onecell_data sun6i_rtc_ccu_hw_clks = { |
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.num = CLK_NUMBER, |
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.hws = { |
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[CLK_OSC32K] = &osc32k_clk.common.hw, |
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[CLK_OSC32K_FANOUT] = &osc32k_fanout_clk.common.hw, |
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[CLK_IOSC] = &iosc_clk.hw, |
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[CLK_IOSC_32K] = &iosc_32k_clk.hw, |
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[CLK_EXT_OSC32K_GATE] = &ext_osc32k_gate_clk.common.hw, |
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[CLK_OSC24M_32K] = &osc24M_32k_clk.common.hw, |
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[CLK_RTC_32K] = &rtc_32k_clk.common.hw, |
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}, |
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}; |
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static const struct sunxi_ccu_desc sun6i_rtc_ccu_desc = { |
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.ccu_clks = sun6i_rtc_ccu_clks, |
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.num_ccu_clks = ARRAY_SIZE(sun6i_rtc_ccu_clks), |
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.hw_clks = &sun6i_rtc_ccu_hw_clks, |
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}; |
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static const struct clk_parent_data sun50i_h616_osc32k_fanout_parents[] = { |
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{ .hw = &osc32k_clk.common.hw }, |
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{ .fw_name = "pll-32k" }, |
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{ .hw = &osc24M_32k_clk.common.hw } |
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}; |
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static const struct clk_parent_data sun50i_r329_osc32k_fanout_parents[] = { |
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{ .hw = &osc32k_clk.common.hw }, |
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{ .hw = &ext_osc32k_gate_clk.common.hw }, |
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{ .hw = &osc24M_32k_clk.common.hw } |
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}; |
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static const struct sun6i_rtc_match_data sun50i_h616_rtc_ccu_data = { |
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.have_iosc_calibration = true, |
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.rtc_32k_single_parent = true, |
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.osc32k_fanout_parents = sun50i_h616_osc32k_fanout_parents, |
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.osc32k_fanout_nparents = ARRAY_SIZE(sun50i_h616_osc32k_fanout_parents), |
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}; |
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static const struct sun6i_rtc_match_data sun50i_r329_rtc_ccu_data = { |
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.have_ext_osc32k = true, |
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.osc32k_fanout_parents = sun50i_r329_osc32k_fanout_parents, |
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.osc32k_fanout_nparents = ARRAY_SIZE(sun50i_r329_osc32k_fanout_parents), |
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}; |
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static const struct of_device_id sun6i_rtc_ccu_match[] = { |
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{ |
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.compatible = "allwinner,sun50i-h616-rtc", |
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.data = &sun50i_h616_rtc_ccu_data, |
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}, |
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{ |
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.compatible = "allwinner,sun50i-r329-rtc", |
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.data = &sun50i_r329_rtc_ccu_data, |
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}, |
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{}, |
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}; |
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int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg) |
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{ |
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const struct sun6i_rtc_match_data *data; |
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struct clk *ext_osc32k_clk = NULL; |
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const struct of_device_id *match; |
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/* This driver is only used for newer variants of the hardware. */ |
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match = of_match_device(sun6i_rtc_ccu_match, dev); |
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if (!match) |
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return 0; |
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data = match->data; |
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have_iosc_calibration = data->have_iosc_calibration; |
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if (data->have_ext_osc32k) { |
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const char *fw_name; |
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/* ext-osc32k was the only input clock in the old binding. */ |
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fw_name = of_property_read_bool(dev->of_node, "clock-names") |
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? "ext-osc32k" : NULL; |
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ext_osc32k_clk = devm_clk_get_optional(dev, fw_name); |
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if (IS_ERR(ext_osc32k_clk)) |
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return PTR_ERR(ext_osc32k_clk); |
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} |
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if (ext_osc32k_clk) { |
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/* Link ext-osc32k-gate to its parent. */ |
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*ext_osc32k = __clk_get_hw(ext_osc32k_clk); |
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} else { |
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/* ext-osc32k-gate is an orphan, so do not register it. */ |
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sun6i_rtc_ccu_hw_clks.hws[CLK_EXT_OSC32K_GATE] = NULL; |
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osc32k_init_data.num_parents = 1; |
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} |
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if (data->rtc_32k_single_parent) |
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rtc_32k_init_data.num_parents = 1; |
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osc32k_fanout_init_data.parent_data = data->osc32k_fanout_parents; |
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osc32k_fanout_init_data.num_parents = data->osc32k_fanout_nparents; |
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return devm_sunxi_ccu_probe(dev, reg, &sun6i_rtc_ccu_desc); |
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} |
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MODULE_IMPORT_NS(SUNXI_CCU); |
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MODULE_LICENSE("GPL");
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