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143 lines
4.1 KiB
143 lines
4.1 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (C) 2020-2021 SiFive, Inc. |
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* Copyright (C) 2020-2021 Zong Li |
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*/ |
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#ifndef __SIFIVE_CLK_FU740_PRCI_H |
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#define __SIFIVE_CLK_FU740_PRCI_H |
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#include <linux/module.h> |
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#include <dt-bindings/clock/sifive-fu740-prci.h> |
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#include "sifive-prci.h" |
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/* PRCI integration data for each WRPLL instance */ |
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static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = { |
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.cfg0_offs = PRCI_COREPLLCFG0_OFFSET, |
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.cfg1_offs = PRCI_COREPLLCFG1_OFFSET, |
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.enable_bypass = sifive_prci_coreclksel_use_hfclk, |
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.disable_bypass = sifive_prci_coreclksel_use_final_corepll, |
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}; |
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static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = { |
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.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, |
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.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, |
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}; |
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static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = { |
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.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, |
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.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, |
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}; |
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static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = { |
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.cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET, |
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.cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET, |
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.enable_bypass = sifive_prci_corepllsel_use_corepll, |
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.disable_bypass = sifive_prci_corepllsel_use_dvfscorepll, |
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}; |
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static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = { |
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.cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET, |
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.cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET, |
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.enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk, |
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.disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll, |
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}; |
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static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = { |
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.cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET, |
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.cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET, |
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}; |
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/* Linux clock framework integration */ |
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static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = { |
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.set_rate = sifive_prci_wrpll_set_rate, |
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.round_rate = sifive_prci_wrpll_round_rate, |
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.recalc_rate = sifive_prci_wrpll_recalc_rate, |
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.enable = sifive_prci_clock_enable, |
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.disable = sifive_prci_clock_disable, |
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.is_enabled = sifive_clk_is_enabled, |
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}; |
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static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = { |
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.recalc_rate = sifive_prci_wrpll_recalc_rate, |
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}; |
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static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = { |
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.recalc_rate = sifive_prci_tlclksel_recalc_rate, |
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}; |
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static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = { |
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.recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate, |
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}; |
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static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = { |
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.enable = sifive_prci_pcie_aux_clock_enable, |
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.disable = sifive_prci_pcie_aux_clock_disable, |
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.is_enabled = sifive_prci_pcie_aux_clock_is_enabled, |
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}; |
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/* List of clock controls provided by the PRCI */ |
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static struct __prci_clock __prci_init_clocks_fu740[] = { |
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[FU740_PRCI_CLK_COREPLL] = { |
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.name = "corepll", |
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.parent_name = "hfclk", |
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.ops = &sifive_fu740_prci_wrpll_clk_ops, |
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.pwd = &sifive_fu740_prci_corepll_data, |
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}, |
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[FU740_PRCI_CLK_DDRPLL] = { |
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.name = "ddrpll", |
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.parent_name = "hfclk", |
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.ops = &sifive_fu740_prci_wrpll_ro_clk_ops, |
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.pwd = &sifive_fu740_prci_ddrpll_data, |
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}, |
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[FU740_PRCI_CLK_GEMGXLPLL] = { |
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.name = "gemgxlpll", |
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.parent_name = "hfclk", |
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.ops = &sifive_fu740_prci_wrpll_clk_ops, |
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.pwd = &sifive_fu740_prci_gemgxlpll_data, |
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}, |
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[FU740_PRCI_CLK_DVFSCOREPLL] = { |
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.name = "dvfscorepll", |
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.parent_name = "hfclk", |
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.ops = &sifive_fu740_prci_wrpll_clk_ops, |
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.pwd = &sifive_fu740_prci_dvfscorepll_data, |
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}, |
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[FU740_PRCI_CLK_HFPCLKPLL] = { |
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.name = "hfpclkpll", |
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.parent_name = "hfclk", |
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.ops = &sifive_fu740_prci_wrpll_clk_ops, |
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.pwd = &sifive_fu740_prci_hfpclkpll_data, |
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}, |
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[FU740_PRCI_CLK_CLTXPLL] = { |
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.name = "cltxpll", |
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.parent_name = "hfclk", |
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.ops = &sifive_fu740_prci_wrpll_clk_ops, |
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.pwd = &sifive_fu740_prci_cltxpll_data, |
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}, |
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[FU740_PRCI_CLK_TLCLK] = { |
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.name = "tlclk", |
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.parent_name = "corepll", |
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.ops = &sifive_fu740_prci_tlclksel_clk_ops, |
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}, |
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[FU740_PRCI_CLK_PCLK] = { |
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.name = "pclk", |
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.parent_name = "hfpclkpll", |
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.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, |
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}, |
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[FU740_PRCI_CLK_PCIE_AUX] = { |
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.name = "pcie_aux", |
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.parent_name = "hfclk", |
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.ops = &sifive_fu740_prci_pcie_aux_clk_ops, |
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}, |
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}; |
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static const struct prci_clk_desc prci_clk_fu740 = { |
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.clks = __prci_init_clocks_fu740, |
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.num_clks = ARRAY_SIZE(__prci_init_clocks_fu740), |
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}; |
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#endif /* __SIFIVE_CLK_FU740_PRCI_H */
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