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57 lines
1.4 KiB
57 lines
1.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* H8/300 divide clock driver |
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* |
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* Copyright 2015 Yoshinori Sato <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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static DEFINE_SPINLOCK(clklock); |
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static void __init h8300_div_clk_setup(struct device_node *node) |
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{ |
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unsigned int num_parents; |
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struct clk_hw *hw; |
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const char *clk_name = node->name; |
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const char *parent_name; |
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void __iomem *divcr = NULL; |
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int width; |
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int offset; |
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num_parents = of_clk_get_parent_count(node); |
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if (!num_parents) { |
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pr_err("%s: no parent found\n", clk_name); |
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return; |
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} |
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divcr = of_iomap(node, 0); |
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if (divcr == NULL) { |
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pr_err("%s: failed to map divide register\n", clk_name); |
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goto error; |
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} |
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offset = (unsigned long)divcr & 3; |
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offset = (3 - offset) * 8; |
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divcr = (void __iomem *)((unsigned long)divcr & ~3); |
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parent_name = of_clk_get_parent_name(node, 0); |
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of_property_read_u32(node, "renesas,width", &width); |
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hw = clk_hw_register_divider(NULL, clk_name, parent_name, |
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CLK_SET_RATE_GATE, divcr, offset, width, |
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CLK_DIVIDER_POWER_OF_TWO, &clklock); |
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if (!IS_ERR(hw)) { |
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of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); |
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return; |
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} |
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pr_err("%s: failed to register %s div clock (%ld)\n", |
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__func__, clk_name, PTR_ERR(hw)); |
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error: |
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if (divcr) |
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iounmap(divcr); |
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} |
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CLK_OF_DECLARE(h8300_div_clk, "renesas,h8300-div-clock", h8300_div_clk_setup);
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