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389 lines
10 KiB
389 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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// Copyright (c) 2021, Michael Srba |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_clock.h> |
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#include <linux/pm_domain.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regmap.h> |
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#include <linux/reset.h> |
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/* AXI Halt Register Offsets */ |
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#define AXI_HALTREQ_REG 0x0 |
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#define AXI_HALTACK_REG 0x4 |
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#define AXI_IDLE_REG 0x8 |
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#define SSCAON_CONFIG0_CLAMP_EN_OVRD BIT(4) |
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#define SSCAON_CONFIG0_CLAMP_EN_OVRD_VAL BIT(5) |
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static const char *const qcom_ssc_block_pd_names[] = { |
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"ssc_cx", |
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"ssc_mx" |
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}; |
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struct qcom_ssc_block_bus_data { |
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const char *const *pd_names; |
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struct device *pds[ARRAY_SIZE(qcom_ssc_block_pd_names)]; |
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char __iomem *reg_mpm_sscaon_config0; |
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char __iomem *reg_mpm_sscaon_config1; |
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struct regmap *halt_map; |
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struct clk *xo_clk; |
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struct clk *aggre2_clk; |
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struct clk *gcc_im_sleep_clk; |
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struct clk *aggre2_north_clk; |
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struct clk *ssc_xo_clk; |
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struct clk *ssc_ahbs_clk; |
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struct reset_control *ssc_bcr; |
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struct reset_control *ssc_reset; |
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u32 ssc_axi_halt; |
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int num_pds; |
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}; |
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static void reg32_set_bits(char __iomem *reg, u32 value) |
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{ |
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u32 tmp = ioread32(reg); |
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iowrite32(tmp | value, reg); |
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} |
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static void reg32_clear_bits(char __iomem *reg, u32 value) |
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{ |
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u32 tmp = ioread32(reg); |
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iowrite32(tmp & (~value), reg); |
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} |
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static int qcom_ssc_block_bus_init(struct device *dev) |
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{ |
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int ret; |
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struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev); |
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ret = clk_prepare_enable(data->xo_clk); |
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if (ret) { |
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dev_err(dev, "error enabling xo_clk: %d\n", ret); |
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goto err_xo_clk; |
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} |
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ret = clk_prepare_enable(data->aggre2_clk); |
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if (ret) { |
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dev_err(dev, "error enabling aggre2_clk: %d\n", ret); |
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goto err_aggre2_clk; |
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} |
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ret = clk_prepare_enable(data->gcc_im_sleep_clk); |
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if (ret) { |
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dev_err(dev, "error enabling gcc_im_sleep_clk: %d\n", ret); |
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goto err_gcc_im_sleep_clk; |
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} |
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/* |
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* We need to intervene here because the HW logic driving these signals cannot handle |
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* initialization after power collapse by itself. |
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*/ |
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reg32_clear_bits(data->reg_mpm_sscaon_config0, |
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SSCAON_CONFIG0_CLAMP_EN_OVRD | SSCAON_CONFIG0_CLAMP_EN_OVRD_VAL); |
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/* override few_ack/rest_ack */ |
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reg32_clear_bits(data->reg_mpm_sscaon_config1, BIT(31)); |
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ret = clk_prepare_enable(data->aggre2_north_clk); |
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if (ret) { |
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dev_err(dev, "error enabling aggre2_north_clk: %d\n", ret); |
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goto err_aggre2_north_clk; |
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} |
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ret = reset_control_deassert(data->ssc_reset); |
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if (ret) { |
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dev_err(dev, "error deasserting ssc_reset: %d\n", ret); |
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goto err_ssc_reset; |
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} |
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ret = reset_control_deassert(data->ssc_bcr); |
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if (ret) { |
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dev_err(dev, "error deasserting ssc_bcr: %d\n", ret); |
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goto err_ssc_bcr; |
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} |
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regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 0); |
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ret = clk_prepare_enable(data->ssc_xo_clk); |
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if (ret) { |
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dev_err(dev, "error deasserting ssc_xo_clk: %d\n", ret); |
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goto err_ssc_xo_clk; |
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} |
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ret = clk_prepare_enable(data->ssc_ahbs_clk); |
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if (ret) { |
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dev_err(dev, "error deasserting ssc_ahbs_clk: %d\n", ret); |
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goto err_ssc_ahbs_clk; |
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} |
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return 0; |
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err_ssc_ahbs_clk: |
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clk_disable(data->ssc_xo_clk); |
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err_ssc_xo_clk: |
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regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 1); |
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reset_control_assert(data->ssc_bcr); |
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err_ssc_bcr: |
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reset_control_assert(data->ssc_reset); |
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err_ssc_reset: |
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clk_disable(data->aggre2_north_clk); |
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err_aggre2_north_clk: |
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reg32_set_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5)); |
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reg32_set_bits(data->reg_mpm_sscaon_config1, BIT(31)); |
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clk_disable(data->gcc_im_sleep_clk); |
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err_gcc_im_sleep_clk: |
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clk_disable(data->aggre2_clk); |
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err_aggre2_clk: |
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clk_disable(data->xo_clk); |
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err_xo_clk: |
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return ret; |
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} |
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static void qcom_ssc_block_bus_deinit(struct device *dev) |
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{ |
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int ret; |
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struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev); |
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clk_disable(data->ssc_xo_clk); |
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clk_disable(data->ssc_ahbs_clk); |
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ret = reset_control_assert(data->ssc_bcr); |
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if (ret) |
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dev_err(dev, "error asserting ssc_bcr: %d\n", ret); |
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regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 1); |
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reg32_set_bits(data->reg_mpm_sscaon_config1, BIT(31)); |
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reg32_set_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5)); |
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ret = reset_control_assert(data->ssc_reset); |
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if (ret) |
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dev_err(dev, "error asserting ssc_reset: %d\n", ret); |
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clk_disable(data->gcc_im_sleep_clk); |
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clk_disable(data->aggre2_north_clk); |
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clk_disable(data->aggre2_clk); |
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clk_disable(data->xo_clk); |
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} |
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static int qcom_ssc_block_bus_pds_attach(struct device *dev, struct device **pds, |
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const char *const *pd_names, size_t num_pds) |
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{ |
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int ret; |
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int i; |
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for (i = 0; i < num_pds; i++) { |
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pds[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]); |
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if (IS_ERR_OR_NULL(pds[i])) { |
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ret = PTR_ERR(pds[i]) ? : -ENODATA; |
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goto unroll_attach; |
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} |
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} |
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return num_pds; |
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unroll_attach: |
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for (i--; i >= 0; i--) |
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dev_pm_domain_detach(pds[i], false); |
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return ret; |
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}; |
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static void qcom_ssc_block_bus_pds_detach(struct device *dev, struct device **pds, size_t num_pds) |
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{ |
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int i; |
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for (i = 0; i < num_pds; i++) |
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dev_pm_domain_detach(pds[i], false); |
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} |
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static int qcom_ssc_block_bus_pds_enable(struct device **pds, size_t num_pds) |
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{ |
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int ret; |
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int i; |
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for (i = 0; i < num_pds; i++) { |
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dev_pm_genpd_set_performance_state(pds[i], INT_MAX); |
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ret = pm_runtime_get_sync(pds[i]); |
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if (ret < 0) |
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goto unroll_pd_votes; |
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} |
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return 0; |
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unroll_pd_votes: |
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for (i--; i >= 0; i--) { |
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dev_pm_genpd_set_performance_state(pds[i], 0); |
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pm_runtime_put(pds[i]); |
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} |
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return ret; |
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}; |
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static void qcom_ssc_block_bus_pds_disable(struct device **pds, size_t num_pds) |
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{ |
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int i; |
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for (i = 0; i < num_pds; i++) { |
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dev_pm_genpd_set_performance_state(pds[i], 0); |
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pm_runtime_put(pds[i]); |
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} |
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} |
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static int qcom_ssc_block_bus_probe(struct platform_device *pdev) |
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{ |
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struct qcom_ssc_block_bus_data *data; |
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struct device_node *np = pdev->dev.of_node; |
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struct of_phandle_args halt_args; |
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struct resource *res; |
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int ret; |
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); |
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if (!data) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, data); |
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data->pd_names = qcom_ssc_block_pd_names; |
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data->num_pds = ARRAY_SIZE(qcom_ssc_block_pd_names); |
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/* power domains */ |
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ret = qcom_ssc_block_bus_pds_attach(&pdev->dev, data->pds, data->pd_names, data->num_pds); |
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if (ret < 0) |
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return dev_err_probe(&pdev->dev, ret, "error when attaching power domains\n"); |
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ret = qcom_ssc_block_bus_pds_enable(data->pds, data->num_pds); |
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if (ret < 0) |
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return dev_err_probe(&pdev->dev, ret, "error when enabling power domains\n"); |
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/* low level overrides for when the HW logic doesn't "just work" */ |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpm_sscaon_config0"); |
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data->reg_mpm_sscaon_config0 = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(data->reg_mpm_sscaon_config0)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(data->reg_mpm_sscaon_config0), |
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"Failed to ioremap mpm_sscaon_config0\n"); |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpm_sscaon_config1"); |
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data->reg_mpm_sscaon_config1 = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(data->reg_mpm_sscaon_config1)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(data->reg_mpm_sscaon_config1), |
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"Failed to ioremap mpm_sscaon_config1\n"); |
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/* resets */ |
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data->ssc_bcr = devm_reset_control_get_exclusive(&pdev->dev, "ssc_bcr"); |
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if (IS_ERR(data->ssc_bcr)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(data->ssc_bcr), |
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"Failed to acquire reset: scc_bcr\n"); |
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data->ssc_reset = devm_reset_control_get_exclusive(&pdev->dev, "ssc_reset"); |
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if (IS_ERR(data->ssc_reset)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(data->ssc_reset), |
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"Failed to acquire reset: ssc_reset:\n"); |
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/* clocks */ |
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data->xo_clk = devm_clk_get(&pdev->dev, "xo"); |
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if (IS_ERR(data->xo_clk)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(data->xo_clk), |
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"Failed to get clock: xo\n"); |
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data->aggre2_clk = devm_clk_get(&pdev->dev, "aggre2"); |
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if (IS_ERR(data->aggre2_clk)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(data->aggre2_clk), |
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"Failed to get clock: aggre2\n"); |
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data->gcc_im_sleep_clk = devm_clk_get(&pdev->dev, "gcc_im_sleep"); |
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if (IS_ERR(data->gcc_im_sleep_clk)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(data->gcc_im_sleep_clk), |
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"Failed to get clock: gcc_im_sleep\n"); |
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data->aggre2_north_clk = devm_clk_get(&pdev->dev, "aggre2_north"); |
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if (IS_ERR(data->aggre2_north_clk)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(data->aggre2_north_clk), |
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"Failed to get clock: aggre2_north\n"); |
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data->ssc_xo_clk = devm_clk_get(&pdev->dev, "ssc_xo"); |
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if (IS_ERR(data->ssc_xo_clk)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(data->ssc_xo_clk), |
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"Failed to get clock: ssc_xo\n"); |
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data->ssc_ahbs_clk = devm_clk_get(&pdev->dev, "ssc_ahbs"); |
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if (IS_ERR(data->ssc_ahbs_clk)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(data->ssc_ahbs_clk), |
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"Failed to get clock: ssc_ahbs\n"); |
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ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, "qcom,halt-regs", 1, 0, |
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&halt_args); |
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if (ret < 0) |
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return dev_err_probe(&pdev->dev, ret, "Failed to parse qcom,halt-regs\n"); |
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data->halt_map = syscon_node_to_regmap(halt_args.np); |
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of_node_put(halt_args.np); |
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if (IS_ERR(data->halt_map)) |
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return PTR_ERR(data->halt_map); |
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data->ssc_axi_halt = halt_args.args[0]; |
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qcom_ssc_block_bus_init(&pdev->dev); |
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of_platform_populate(np, NULL, NULL, &pdev->dev); |
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return 0; |
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} |
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static int qcom_ssc_block_bus_remove(struct platform_device *pdev) |
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{ |
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struct qcom_ssc_block_bus_data *data = platform_get_drvdata(pdev); |
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qcom_ssc_block_bus_deinit(&pdev->dev); |
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iounmap(data->reg_mpm_sscaon_config0); |
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iounmap(data->reg_mpm_sscaon_config1); |
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qcom_ssc_block_bus_pds_disable(data->pds, data->num_pds); |
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qcom_ssc_block_bus_pds_detach(&pdev->dev, data->pds, data->num_pds); |
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pm_runtime_disable(&pdev->dev); |
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pm_clk_destroy(&pdev->dev); |
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return 0; |
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} |
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static const struct of_device_id qcom_ssc_block_bus_of_match[] = { |
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{ .compatible = "qcom,ssc-block-bus", }, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, qcom_ssc_block_bus_of_match); |
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static struct platform_driver qcom_ssc_block_bus_driver = { |
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.probe = qcom_ssc_block_bus_probe, |
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.remove = qcom_ssc_block_bus_remove, |
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.driver = { |
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.name = "qcom-ssc-block-bus", |
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.of_match_table = qcom_ssc_block_bus_of_match, |
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}, |
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}; |
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module_platform_driver(qcom_ssc_block_bus_driver); |
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MODULE_DESCRIPTION("A driver for handling the init sequence needed for accessing the SSC block on (some) qcom SoCs over AHB"); |
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MODULE_AUTHOR("Michael Srba <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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