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68 lines
2.6 KiB
68 lines
2.6 KiB
Binding for MTK SPI controller |
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Required properties: |
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- compatible: should be one of the following. |
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- mediatek,mt2701-spi: for mt2701 platforms |
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- mediatek,mt2712-spi: for mt2712 platforms |
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- mediatek,mt6589-spi: for mt6589 platforms |
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- mediatek,mt6765-spi: for mt6765 platforms |
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- mediatek,mt7622-spi: for mt7622 platforms |
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- "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms |
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- mediatek,mt8135-spi: for mt8135 platforms |
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- mediatek,mt8173-spi: for mt8173 platforms |
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- mediatek,mt8183-spi: for mt8183 platforms |
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- mediatek,mt6893-spi: for mt6893 platforms |
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- "mediatek,mt8192-spi", "mediatek,mt6765-spi": for mt8192 platforms |
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- "mediatek,mt8195-spi", "mediatek,mt6765-spi": for mt8195 platforms |
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- "mediatek,mt8516-spi", "mediatek,mt2712-spi": for mt8516 platforms |
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- "mediatek,mt6779-spi", "mediatek,mt6765-spi": for mt6779 platforms |
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- #address-cells: should be 1. |
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- #size-cells: should be 0. |
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- reg: Address and length of the register set for the device |
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- interrupts: Should contain spi interrupt |
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- clocks: phandles to input clocks. |
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The first should be one of the following. It's PLL. |
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- <&clk26m>: specify parent clock 26MHZ. |
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- <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ. |
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It's the default one. |
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- <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ. |
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- <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ. |
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- <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ. |
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The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux. |
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The third is <&pericfg CLK_PERI_SPI0>. It's clock gate. |
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- clock-names: shall be "parent-clk" for the parent clock, "sel-clk" for the |
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muxes clock, and "spi-clk" for the clock gate. |
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Optional properties: |
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-cs-gpios: see spi-bus.txt. |
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- mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi |
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controller used. This is an array, the element value should be 0~3, |
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only required for MT8173. |
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0: specify GPIO69,70,71,72 for spi pins. |
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1: specify GPIO102,103,104,105 for spi pins. |
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2: specify GPIO128,129,130,131 for spi pins. |
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3: specify GPIO5,6,7,8 for spi pins. |
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Example: |
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- SoC Specific Portion: |
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spi: spi@1100a000 { |
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compatible = "mediatek,mt8173-spi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0 0x1100a000 0 0x1000>; |
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, |
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<&topckgen CLK_TOP_SPI_SEL>, |
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<&pericfg CLK_PERI_SPI0>; |
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clock-names = "parent-clk", "sel-clk", "spi-clk"; |
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cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>; |
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mediatek,pad-select = <1>, <0>; |
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};
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