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36 lines
1.2 KiB
36 lines
1.2 KiB
Keystone 2 IRQ controller IP |
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On Keystone SOCs, DSP cores can send interrupts to ARM |
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host using the IRQ controller IP. It provides 28 IRQ signals to ARM. |
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The IRQ handler running on HOST OS can identify DSP signal source by |
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analyzing SRCCx bits in IPCARx registers. This is one of the component |
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used by the IPC mechanism used on Keystone SOCs. |
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Required Properties: |
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- compatible: should be "ti,keystone-irq" |
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- ti,syscon-dev : phandle and offset pair. The phandle to syscon used to |
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access device control registers and the offset inside |
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device control registers range. |
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- interrupt-controller : Identifies the node as an interrupt controller |
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- #interrupt-cells : Specifies the number of cells needed to encode interrupt |
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source should be 1. |
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- interrupts: interrupt reference to primary interrupt controller |
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Please refer to interrupts.txt in this directory for details of the common |
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Interrupt Controllers bindings used by client devices. |
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Example: |
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kirq0: keystone_irq0@26202a0 { |
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compatible = "ti,keystone-irq"; |
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ti,syscon-dev = <&devctrl 0x2a0>; |
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interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; |
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interrupt-controller; |
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#interrupt-cells = <1>; |
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}; |
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dsp0: dsp0 { |
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compatible = "linux,rproc-user"; |
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... |
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interrupt-parent = <&kirq0>; |
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interrupts = <10 2>; |
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};
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