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41 lines
1.4 KiB
41 lines
1.4 KiB
NVIDIA Legacy Interrupt Controller |
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All Tegra SoCs contain a legacy interrupt controller that routes |
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interrupts to the GIC, and also serves as a wakeup source. It is also |
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referred to as "ictlr", hence the name of the binding. |
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The HW block exposes a number of interrupt controllers, each |
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implementing a set of 32 interrupts. |
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Required properties: |
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- compatible : should be: "nvidia,tegra<chip>-ictlr". The LIC on |
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subsequent SoCs remained backwards-compatible with Tegra30, so on |
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Tegra generations later than Tegra30 the compatible value should |
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include "nvidia,tegra30-ictlr". |
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- reg : Specifies base physical address and size of the registers. |
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Each controller must be described separately (Tegra20 has 4 of them, |
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whereas Tegra30 and later have 5). |
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- interrupt-controller : Identifies the node as an interrupt controller. |
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- #interrupt-cells : Specifies the number of cells needed to encode an |
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interrupt source. The value must be 3. |
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Notes: |
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- Because this HW ultimately routes interrupts to the GIC, the |
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interrupt specifier must be that of the GIC. |
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- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs |
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are explicitly forbidden. |
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Example: |
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ictlr: interrupt-controller@60004000 { |
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compatible = "nvidia,tegra20-ictlr", "nvidia,tegra-ictlr"; |
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reg = <0x60004000 64>, |
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<0x60004100 64>, |
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<0x60004200 64>, |
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<0x60004300 64>; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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interrupt-parent = <&intc>; |
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};
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