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88 lines
3.2 KiB
88 lines
3.2 KiB
Broadcom BCM7120-style Level 2 interrupt controller |
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This interrupt controller hardware is a second level interrupt controller that |
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is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based |
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platforms. It can be found on BCM7xxx products starting with BCM7120. |
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Such an interrupt controller has the following hardware design: |
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- outputs multiple interrupts signals towards its interrupt controller parent |
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- controls how some of the interrupts will be flowing, whether they will |
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directly output an interrupt signal towards the interrupt controller parent, |
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or if they will output an interrupt signal at this 2nd level interrupt |
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controller, in particular for UARTs |
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- has one 32-bit enable word and one 32-bit status word |
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- no atomic set/clear operations |
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- not all bits within the interrupt controller actually map to an interrupt |
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The typical hardware layout for this controller is represented below: |
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2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC) |
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0 -----[ MUX ] ------------|==========> GIC interrupt 75 |
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\-----------\ |
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1 -----[ MUX ] --------)---|==========> GIC interrupt 76 |
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\------------| |
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2 -----[ MUX ] --------)---|==========> GIC interrupt 77 |
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\------------| |
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3 ---------------------| |
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4 ---------------------| |
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5 ---------------------| |
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7 ---------------------|---|===========> GIC interrupt 66 |
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9 ---------------------| |
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10 --------------------| |
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11 --------------------/ |
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6 ------------------------\ |
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|===========> GIC interrupt 64 |
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8 ------------------------/ |
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12 ........................ X |
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13 ........................ X (not connected) |
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.. |
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31 ........................ X |
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Required properties: |
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- compatible: should be "brcm,bcm7120-l2-intc" |
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- reg: specifies the base physical address and size of the registers |
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- interrupt-controller: identifies the node as an interrupt controller |
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- #interrupt-cells: specifies the number of cells needed to encode an interrupt |
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source, should be 1. |
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- interrupts: specifies the interrupt line(s) in the interrupt-parent controller |
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node, valid values depend on the type of parent interrupt controller |
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- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts |
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are wired to this 2nd level interrupt controller, and how they match their |
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respective interrupt parents. Should match exactly the number of interrupts |
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specified in the 'interrupts' property. |
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Optional properties: |
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- brcm,irq-can-wake: if present, this means the L2 controller can be used as a |
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wakeup source for system suspend/resume. |
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- brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which |
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have a mux gate, typically UARTs. Setting these bits will make their |
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respective interrupt outputs bypass this 2nd level interrupt controller |
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completely; it is completely transparent for the interrupt controller |
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parent. This should have one 32-bit word per enable/status pair. |
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Example: |
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irq0_intc: interrupt-controller@f0406800 { |
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compatible = "brcm,bcm7120-l2-intc"; |
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interrupt-parent = <&intc>; |
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#interrupt-cells = <1>; |
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reg = <0xf0406800 0x8>; |
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interrupt-controller; |
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interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>; |
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brcm,int-map-mask = <0xeb8>, <0x140>; |
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brcm,int-fwd-mask = <0x7>; |
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};
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