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156 lines
4.1 KiB
156 lines
4.1 KiB
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Arm CoreSight Embedded Trace MacroCell |
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maintainers: |
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- Mathieu Poirier <[email protected]> |
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- Mike Leach <[email protected]> |
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- Leo Yan <[email protected]> |
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- Suzuki K Poulose <[email protected]> |
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description: | |
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CoreSight components are compliant with the ARM CoreSight architecture |
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specification and can be connected in various topologies to suit a particular |
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SoCs tracing needs. These trace components can generally be classified as |
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sinks, links and sources. Trace data produced by one or more sources flows |
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through the intermediate links connecting the source to the currently selected |
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sink. |
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The Embedded Trace Macrocell (ETM) is a real-time trace module providing |
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instruction and data tracing of a processor. |
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select: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- arm,coresight-etm3x |
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- arm,coresight-etm4x |
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- arm,coresight-etm4x-sysreg |
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required: |
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- compatible |
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allOf: |
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- if: |
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not: |
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properties: |
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compatible: |
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contains: |
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const: arm,coresight-etm4x-sysreg |
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then: |
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$ref: /schemas/arm/primecell.yaml# |
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required: |
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- reg |
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properties: |
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compatible: |
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oneOf: |
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- description: |
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Embedded Trace Macrocell with memory mapped access. |
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items: |
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- enum: |
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- arm,coresight-etm3x |
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- arm,coresight-etm4x |
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- const: arm,primecell |
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- description: |
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Embedded Trace Macrocell (version 4.x), with system register access only |
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const: arm,coresight-etm4x-sysreg |
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reg: |
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maxItems: 1 |
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clocks: |
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minItems: 1 |
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maxItems: 2 |
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clock-names: |
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minItems: 1 |
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items: |
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- const: apb_pclk |
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- const: atclk |
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arm,coresight-loses-context-with-cpu: |
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type: boolean |
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description: |
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Indicates that the hardware will lose register context on CPU power down |
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(e.g. CPUIdle). An example of where this may be needed are systems which |
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contain a coresight component and CPU in the same power domain. When the |
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CPU powers down the coresight component also powers down and loses its |
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context. |
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arm,cp14: |
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type: boolean |
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description: |
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Must be present if the system accesses ETM/PTM management registers via |
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co-processor 14. |
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qcom,skip-power-up: |
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type: boolean |
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description: |
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Indicates that an implementation can skip powering up the trace unit. |
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TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems |
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since ETMs are in the same power domain as their CPU cores. This property |
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is required to identify such systems with hardware errata where the CPU |
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watchdog counter is stopped when TRCPDCR.PU is set. |
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cpu: |
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description: |
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phandle to the cpu this ETM is bound to. |
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$ref: /schemas/types.yaml#/definitions/phandle |
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out-ports: |
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$ref: /schemas/graph.yaml#/properties/ports |
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additionalProperties: false |
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properties: |
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port: |
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description: Output connection from the ETM to CoreSight Trace bus. |
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$ref: /schemas/graph.yaml#/properties/port |
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required: |
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- compatible |
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- clocks |
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- clock-names |
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- cpu |
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- out-ports |
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unevaluatedProperties: false |
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examples: |
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- | |
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ptm@2201c000 { |
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compatible = "arm,coresight-etm3x", "arm,primecell"; |
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reg = <0x2201c000 0x1000>; |
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cpu = <&cpu0>; |
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clocks = <&oscclk6a>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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ptm0_out_port: endpoint { |
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remote-endpoint = <&funnel_in_port0>; |
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}; |
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}; |
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}; |
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}; |
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ptm@2201d000 { |
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compatible = "arm,coresight-etm3x", "arm,primecell"; |
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reg = <0x2201d000 0x1000>; |
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cpu = <&cpu1>; |
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clocks = <&oscclk6a>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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ptm1_out_port: endpoint { |
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remote-endpoint = <&funnel_in_port1>; |
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}; |
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}; |
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}; |
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}; |
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...
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