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110 lines
2.8 KiB
110 lines
2.8 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* wm8753.h -- audio driver for WM8753 |
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* |
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* Copyright 2003 Wolfson Microelectronics PLC. |
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* Author: Liam Girdwood <[email protected]> |
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*/ |
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#ifndef _WM8753_H |
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#define _WM8753_H |
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/* WM8753 register space */ |
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#define WM8753_DAC 0x01 |
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#define WM8753_ADC 0x02 |
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#define WM8753_PCM 0x03 |
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#define WM8753_HIFI 0x04 |
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#define WM8753_IOCTL 0x05 |
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#define WM8753_SRATE1 0x06 |
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#define WM8753_SRATE2 0x07 |
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#define WM8753_LDAC 0x08 |
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#define WM8753_RDAC 0x09 |
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#define WM8753_BASS 0x0a |
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#define WM8753_TREBLE 0x0b |
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#define WM8753_ALC1 0x0c |
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#define WM8753_ALC2 0x0d |
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#define WM8753_ALC3 0x0e |
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#define WM8753_NGATE 0x0f |
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#define WM8753_LADC 0x10 |
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#define WM8753_RADC 0x11 |
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#define WM8753_ADCTL1 0x12 |
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#define WM8753_3D 0x13 |
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#define WM8753_PWR1 0x14 |
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#define WM8753_PWR2 0x15 |
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#define WM8753_PWR3 0x16 |
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#define WM8753_PWR4 0x17 |
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#define WM8753_ID 0x18 |
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#define WM8753_INTPOL 0x19 |
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#define WM8753_INTEN 0x1a |
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#define WM8753_GPIO1 0x1b |
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#define WM8753_GPIO2 0x1c |
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#define WM8753_RESET 0x1f |
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#define WM8753_RECMIX1 0x20 |
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#define WM8753_RECMIX2 0x21 |
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#define WM8753_LOUTM1 0x22 |
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#define WM8753_LOUTM2 0x23 |
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#define WM8753_ROUTM1 0x24 |
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#define WM8753_ROUTM2 0x25 |
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#define WM8753_MOUTM1 0x26 |
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#define WM8753_MOUTM2 0x27 |
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#define WM8753_LOUT1V 0x28 |
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#define WM8753_ROUT1V 0x29 |
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#define WM8753_LOUT2V 0x2a |
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#define WM8753_ROUT2V 0x2b |
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#define WM8753_MOUTV 0x2c |
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#define WM8753_OUTCTL 0x2d |
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#define WM8753_ADCIN 0x2e |
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#define WM8753_INCTL1 0x2f |
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#define WM8753_INCTL2 0x30 |
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#define WM8753_LINVOL 0x31 |
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#define WM8753_RINVOL 0x32 |
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#define WM8753_MICBIAS 0x33 |
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#define WM8753_CLOCK 0x34 |
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#define WM8753_PLL1CTL1 0x35 |
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#define WM8753_PLL1CTL2 0x36 |
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#define WM8753_PLL1CTL3 0x37 |
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#define WM8753_PLL1CTL4 0x38 |
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#define WM8753_PLL2CTL1 0x39 |
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#define WM8753_PLL2CTL2 0x3a |
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#define WM8753_PLL2CTL3 0x3b |
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#define WM8753_PLL2CTL4 0x3c |
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#define WM8753_BIASCTL 0x3d |
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#define WM8753_ADCTL2 0x3f |
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#define WM8753_PLL1 0 |
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#define WM8753_PLL2 1 |
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/* clock inputs */ |
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#define WM8753_MCLK 0 |
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#define WM8753_PCMCLK 1 |
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/* clock divider id's */ |
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#define WM8753_PCMDIV 0 |
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#define WM8753_BCLKDIV 1 |
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#define WM8753_VXCLKDIV 2 |
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/* PCM clock dividers */ |
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#define WM8753_PCM_DIV_1 (0 << 6) |
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#define WM8753_PCM_DIV_3 (2 << 6) |
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#define WM8753_PCM_DIV_5_5 (3 << 6) |
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#define WM8753_PCM_DIV_2 (4 << 6) |
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#define WM8753_PCM_DIV_4 (5 << 6) |
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#define WM8753_PCM_DIV_6 (6 << 6) |
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#define WM8753_PCM_DIV_8 (7 << 6) |
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/* BCLK clock dividers */ |
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#define WM8753_BCLK_DIV_1 (0 << 3) |
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#define WM8753_BCLK_DIV_2 (1 << 3) |
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#define WM8753_BCLK_DIV_4 (2 << 3) |
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#define WM8753_BCLK_DIV_8 (3 << 3) |
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#define WM8753_BCLK_DIV_16 (4 << 3) |
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/* VXCLK clock dividers */ |
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#define WM8753_VXCLK_DIV_1 (0 << 6) |
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#define WM8753_VXCLK_DIV_2 (1 << 6) |
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#define WM8753_VXCLK_DIV_4 (2 << 6) |
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#define WM8753_VXCLK_DIV_8 (3 << 6) |
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#define WM8753_VXCLK_DIV_16 (4 << 6) |
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#endif
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