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508 lines
14 KiB
508 lines
14 KiB
/* |
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* Xilinx TFT frame buffer driver |
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* |
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* Author: MontaVista Software, Inc. |
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* [email protected] |
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* |
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* 2002-2007 (c) MontaVista Software, Inc. |
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* 2007 (c) Secret Lab Technologies, Ltd. |
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* 2009 (c) Xilinx Inc. |
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* |
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* This file is licensed under the terms of the GNU General Public License |
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* version 2. This program is licensed "as is" without any warranty of any |
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* kind, whether express or implied. |
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*/ |
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|
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/* |
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* This driver was based on au1100fb.c by MontaVista rewritten for 2.6 |
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* by Embedded Alley Solutions <[email protected]>, which in turn |
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* was based on skeletonfb.c, Skeleton for a frame buffer device by |
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* Geert Uytterhoeven. |
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*/ |
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|
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#include <linux/device.h> |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/errno.h> |
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#include <linux/string.h> |
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#include <linux/mm.h> |
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#include <linux/fb.h> |
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#include <linux/init.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/of_device.h> |
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#include <linux/of_platform.h> |
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#include <linux/of_address.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#ifdef CONFIG_PPC_DCR |
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#include <asm/dcr.h> |
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#endif |
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|
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#define DRIVER_NAME "xilinxfb" |
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|
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/* |
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* Xilinx calls it "TFT LCD Controller" though it can also be used for |
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* the VGA port on the Xilinx ML40x board. This is a hardware display |
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* controller for a 640x480 resolution TFT or VGA screen. |
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* |
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* The interface to the framebuffer is nice and simple. There are two |
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* control registers. The first tells the LCD interface where in memory |
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* the frame buffer is (only the 11 most significant bits are used, so |
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* don't start thinking about scrolling). The second allows the LCD to |
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* be turned on or off as well as rotated 180 degrees. |
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* |
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* In case of direct BUS access the second control register will be at |
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* an offset of 4 as compared to the DCR access where the offset is 1 |
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* i.e. REG_CTRL. So this is taken care in the function |
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* xilinx_fb_out32 where it left shifts the offset 2 times in case of |
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* direct BUS access. |
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*/ |
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#define NUM_REGS 2 |
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#define REG_FB_ADDR 0 |
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#define REG_CTRL 1 |
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#define REG_CTRL_ENABLE 0x0001 |
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#define REG_CTRL_ROTATE 0x0002 |
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/* |
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* The hardware only handles a single mode: 640x480 24 bit true |
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* color. Each pixel gets a word (32 bits) of memory. Within each word, |
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* the 8 most significant bits are ignored, the next 8 bits are the red |
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* level, the next 8 bits are the green level and the 8 least |
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* significant bits are the blue level. Each row of the LCD uses 1024 |
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* words, but only the first 640 pixels are displayed with the other 384 |
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* words being ignored. There are 480 rows. |
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*/ |
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#define BYTES_PER_PIXEL 4 |
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#define BITS_PER_PIXEL (BYTES_PER_PIXEL * 8) |
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#define RED_SHIFT 16 |
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#define GREEN_SHIFT 8 |
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#define BLUE_SHIFT 0 |
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#define PALETTE_ENTRIES_NO 16 /* passed to fb_alloc_cmap() */ |
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/* ML300/403 reference design framebuffer driver platform data struct */ |
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struct xilinxfb_platform_data { |
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u32 rotate_screen; /* Flag to rotate display 180 degrees */ |
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u32 screen_height_mm; /* Physical dimensions of screen in mm */ |
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u32 screen_width_mm; |
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u32 xres, yres; /* resolution of screen in pixels */ |
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u32 xvirt, yvirt; /* resolution of memory buffer */ |
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|
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/* Physical address of framebuffer memory; If non-zero, driver |
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* will use provided memory address instead of allocating one from |
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* the consistent pool. |
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*/ |
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u32 fb_phys; |
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}; |
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/* |
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* Default xilinxfb configuration |
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*/ |
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static const struct xilinxfb_platform_data xilinx_fb_default_pdata = { |
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.xres = 640, |
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.yres = 480, |
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.xvirt = 1024, |
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.yvirt = 480, |
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}; |
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/* |
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* Here are the default fb_fix_screeninfo and fb_var_screeninfo structures |
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*/ |
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static const struct fb_fix_screeninfo xilinx_fb_fix = { |
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.id = "Xilinx", |
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.type = FB_TYPE_PACKED_PIXELS, |
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.visual = FB_VISUAL_TRUECOLOR, |
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.accel = FB_ACCEL_NONE |
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}; |
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static const struct fb_var_screeninfo xilinx_fb_var = { |
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.bits_per_pixel = BITS_PER_PIXEL, |
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.red = { RED_SHIFT, 8, 0 }, |
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.green = { GREEN_SHIFT, 8, 0 }, |
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.blue = { BLUE_SHIFT, 8, 0 }, |
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.transp = { 0, 0, 0 }, |
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.activate = FB_ACTIVATE_NOW |
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}; |
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#define BUS_ACCESS_FLAG 0x1 /* 1 = BUS, 0 = DCR */ |
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#define LITTLE_ENDIAN_ACCESS 0x2 /* LITTLE ENDIAN IO functions */ |
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struct xilinxfb_drvdata { |
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struct fb_info info; /* FB driver info record */ |
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phys_addr_t regs_phys; /* phys. address of the control |
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* registers |
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*/ |
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void __iomem *regs; /* virt. address of the control |
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* registers |
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*/ |
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#ifdef CONFIG_PPC_DCR |
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dcr_host_t dcr_host; |
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unsigned int dcr_len; |
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#endif |
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void *fb_virt; /* virt. address of the frame buffer */ |
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dma_addr_t fb_phys; /* phys. address of the frame buffer */ |
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int fb_alloced; /* Flag, was the fb memory alloced? */ |
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u8 flags; /* features of the driver */ |
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u32 reg_ctrl_default; |
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u32 pseudo_palette[PALETTE_ENTRIES_NO]; |
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/* Fake palette of 16 colors */ |
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}; |
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#define to_xilinxfb_drvdata(_info) \ |
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container_of(_info, struct xilinxfb_drvdata, info) |
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/* |
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* The XPS TFT Controller can be accessed through BUS or DCR interface. |
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* To perform the read/write on the registers we need to check on |
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* which bus its connected and call the appropriate write API. |
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*/ |
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static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset, |
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u32 val) |
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{ |
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if (drvdata->flags & BUS_ACCESS_FLAG) { |
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if (drvdata->flags & LITTLE_ENDIAN_ACCESS) |
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iowrite32(val, drvdata->regs + (offset << 2)); |
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else |
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iowrite32be(val, drvdata->regs + (offset << 2)); |
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} |
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#ifdef CONFIG_PPC_DCR |
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else |
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dcr_write(drvdata->dcr_host, offset, val); |
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#endif |
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} |
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static u32 xilinx_fb_in32(struct xilinxfb_drvdata *drvdata, u32 offset) |
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{ |
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if (drvdata->flags & BUS_ACCESS_FLAG) { |
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if (drvdata->flags & LITTLE_ENDIAN_ACCESS) |
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return ioread32(drvdata->regs + (offset << 2)); |
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else |
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return ioread32be(drvdata->regs + (offset << 2)); |
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} |
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#ifdef CONFIG_PPC_DCR |
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else |
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return dcr_read(drvdata->dcr_host, offset); |
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#endif |
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return 0; |
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} |
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static int |
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xilinx_fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, |
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unsigned int blue, unsigned int transp, struct fb_info *fbi) |
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{ |
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u32 *palette = fbi->pseudo_palette; |
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if (regno >= PALETTE_ENTRIES_NO) |
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return -EINVAL; |
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if (fbi->var.grayscale) { |
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/* Convert color to grayscale. |
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* grayscale = 0.30*R + 0.59*G + 0.11*B |
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*/ |
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blue = (red * 77 + green * 151 + blue * 28 + 127) >> 8; |
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green = blue; |
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red = green; |
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} |
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/* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */ |
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/* We only handle 8 bits of each color. */ |
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red >>= 8; |
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green >>= 8; |
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blue >>= 8; |
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palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) | |
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(blue << BLUE_SHIFT); |
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return 0; |
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} |
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static int |
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xilinx_fb_blank(int blank_mode, struct fb_info *fbi) |
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{ |
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struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi); |
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switch (blank_mode) { |
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case FB_BLANK_UNBLANK: |
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/* turn on panel */ |
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xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default); |
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break; |
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case FB_BLANK_NORMAL: |
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case FB_BLANK_VSYNC_SUSPEND: |
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case FB_BLANK_HSYNC_SUSPEND: |
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case FB_BLANK_POWERDOWN: |
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/* turn off panel */ |
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xilinx_fb_out32(drvdata, REG_CTRL, 0); |
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default: |
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break; |
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} |
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return 0; /* success */ |
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} |
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static const struct fb_ops xilinxfb_ops = { |
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.owner = THIS_MODULE, |
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.fb_setcolreg = xilinx_fb_setcolreg, |
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.fb_blank = xilinx_fb_blank, |
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.fb_fillrect = cfb_fillrect, |
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.fb_copyarea = cfb_copyarea, |
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.fb_imageblit = cfb_imageblit, |
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}; |
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/* --------------------------------------------------------------------- |
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* Bus independent setup/teardown |
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*/ |
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static int xilinxfb_assign(struct platform_device *pdev, |
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struct xilinxfb_drvdata *drvdata, |
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struct xilinxfb_platform_data *pdata) |
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{ |
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int rc; |
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struct device *dev = &pdev->dev; |
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int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL; |
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if (drvdata->flags & BUS_ACCESS_FLAG) { |
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struct resource *res; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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drvdata->regs = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(drvdata->regs)) |
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return PTR_ERR(drvdata->regs); |
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drvdata->regs_phys = res->start; |
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} |
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/* Allocate the framebuffer memory */ |
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if (pdata->fb_phys) { |
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drvdata->fb_phys = pdata->fb_phys; |
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drvdata->fb_virt = ioremap(pdata->fb_phys, fbsize); |
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} else { |
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drvdata->fb_alloced = 1; |
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drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize), |
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&drvdata->fb_phys, |
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GFP_KERNEL); |
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} |
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if (!drvdata->fb_virt) { |
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dev_err(dev, "Could not allocate frame buffer memory\n"); |
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return -ENOMEM; |
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} |
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/* Clear (turn to black) the framebuffer */ |
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memset_io((void __iomem *)drvdata->fb_virt, 0, fbsize); |
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/* Tell the hardware where the frame buffer is */ |
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xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys); |
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rc = xilinx_fb_in32(drvdata, REG_FB_ADDR); |
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/* Endianness detection */ |
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if (rc != drvdata->fb_phys) { |
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drvdata->flags |= LITTLE_ENDIAN_ACCESS; |
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xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys); |
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} |
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/* Turn on the display */ |
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drvdata->reg_ctrl_default = REG_CTRL_ENABLE; |
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if (pdata->rotate_screen) |
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drvdata->reg_ctrl_default |= REG_CTRL_ROTATE; |
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xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default); |
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/* Fill struct fb_info */ |
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drvdata->info.device = dev; |
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drvdata->info.screen_base = (void __iomem *)drvdata->fb_virt; |
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drvdata->info.fbops = &xilinxfb_ops; |
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drvdata->info.fix = xilinx_fb_fix; |
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drvdata->info.fix.smem_start = drvdata->fb_phys; |
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drvdata->info.fix.smem_len = fbsize; |
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drvdata->info.fix.line_length = pdata->xvirt * BYTES_PER_PIXEL; |
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drvdata->info.pseudo_palette = drvdata->pseudo_palette; |
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drvdata->info.flags = FBINFO_DEFAULT; |
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drvdata->info.var = xilinx_fb_var; |
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drvdata->info.var.height = pdata->screen_height_mm; |
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drvdata->info.var.width = pdata->screen_width_mm; |
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drvdata->info.var.xres = pdata->xres; |
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drvdata->info.var.yres = pdata->yres; |
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drvdata->info.var.xres_virtual = pdata->xvirt; |
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drvdata->info.var.yres_virtual = pdata->yvirt; |
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/* Allocate a colour map */ |
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rc = fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0); |
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if (rc) { |
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dev_err(dev, "Fail to allocate colormap (%d entries)\n", |
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PALETTE_ENTRIES_NO); |
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goto err_cmap; |
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} |
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/* Register new frame buffer */ |
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rc = register_framebuffer(&drvdata->info); |
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if (rc) { |
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dev_err(dev, "Could not register frame buffer\n"); |
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goto err_regfb; |
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} |
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if (drvdata->flags & BUS_ACCESS_FLAG) { |
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/* Put a banner in the log (for DEBUG) */ |
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dev_dbg(dev, "regs: phys=%pa, virt=%p\n", |
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&drvdata->regs_phys, drvdata->regs); |
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} |
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/* Put a banner in the log (for DEBUG) */ |
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dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n", |
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(unsigned long long)drvdata->fb_phys, drvdata->fb_virt, fbsize); |
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return 0; /* success */ |
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err_regfb: |
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fb_dealloc_cmap(&drvdata->info.cmap); |
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err_cmap: |
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if (drvdata->fb_alloced) |
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dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata->fb_virt, |
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drvdata->fb_phys); |
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else |
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iounmap(drvdata->fb_virt); |
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/* Turn off the display */ |
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xilinx_fb_out32(drvdata, REG_CTRL, 0); |
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return rc; |
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} |
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static int xilinxfb_release(struct device *dev) |
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{ |
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struct xilinxfb_drvdata *drvdata = dev_get_drvdata(dev); |
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#if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO) |
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xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info); |
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#endif |
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unregister_framebuffer(&drvdata->info); |
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fb_dealloc_cmap(&drvdata->info.cmap); |
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if (drvdata->fb_alloced) |
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dma_free_coherent(dev, PAGE_ALIGN(drvdata->info.fix.smem_len), |
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drvdata->fb_virt, drvdata->fb_phys); |
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else |
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iounmap(drvdata->fb_virt); |
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/* Turn off the display */ |
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xilinx_fb_out32(drvdata, REG_CTRL, 0); |
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#ifdef CONFIG_PPC_DCR |
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/* Release the resources, as allocated based on interface */ |
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if (!(drvdata->flags & BUS_ACCESS_FLAG)) |
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dcr_unmap(drvdata->dcr_host, drvdata->dcr_len); |
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#endif |
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return 0; |
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} |
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/* --------------------------------------------------------------------- |
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* OF bus binding |
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*/ |
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static int xilinxfb_of_probe(struct platform_device *pdev) |
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{ |
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const u32 *prop; |
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u32 tft_access = 0; |
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struct xilinxfb_platform_data pdata; |
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int size; |
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struct xilinxfb_drvdata *drvdata; |
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/* Copy with the default pdata (not a ptr reference!) */ |
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pdata = xilinx_fb_default_pdata; |
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/* Allocate the driver data region */ |
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drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); |
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if (!drvdata) |
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return -ENOMEM; |
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/* |
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* To check whether the core is connected directly to DCR or BUS |
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* interface and initialize the tft_access accordingly. |
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*/ |
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of_property_read_u32(pdev->dev.of_node, "xlnx,dcr-splb-slave-if", |
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&tft_access); |
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|
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/* |
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* Fill the resource structure if its direct BUS interface |
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* otherwise fill the dcr_host structure. |
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*/ |
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if (tft_access) |
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drvdata->flags |= BUS_ACCESS_FLAG; |
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#ifdef CONFIG_PPC_DCR |
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else { |
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int start; |
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|
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start = dcr_resource_start(pdev->dev.of_node, 0); |
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drvdata->dcr_len = dcr_resource_len(pdev->dev.of_node, 0); |
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drvdata->dcr_host = dcr_map(pdev->dev.of_node, start, drvdata->dcr_len); |
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if (!DCR_MAP_OK(drvdata->dcr_host)) { |
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dev_err(&pdev->dev, "invalid DCR address\n"); |
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return -ENODEV; |
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} |
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} |
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#endif |
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prop = of_get_property(pdev->dev.of_node, "phys-size", &size); |
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if ((prop) && (size >= sizeof(u32) * 2)) { |
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pdata.screen_width_mm = prop[0]; |
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pdata.screen_height_mm = prop[1]; |
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} |
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prop = of_get_property(pdev->dev.of_node, "resolution", &size); |
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if ((prop) && (size >= sizeof(u32) * 2)) { |
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pdata.xres = prop[0]; |
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pdata.yres = prop[1]; |
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} |
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prop = of_get_property(pdev->dev.of_node, "virtual-resolution", &size); |
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if ((prop) && (size >= sizeof(u32) * 2)) { |
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pdata.xvirt = prop[0]; |
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pdata.yvirt = prop[1]; |
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} |
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if (of_find_property(pdev->dev.of_node, "rotate-display", NULL)) |
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pdata.rotate_screen = 1; |
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platform_set_drvdata(pdev, drvdata); |
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return xilinxfb_assign(pdev, drvdata, &pdata); |
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} |
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static int xilinxfb_of_remove(struct platform_device *op) |
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{ |
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return xilinxfb_release(&op->dev); |
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} |
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/* Match table for of_platform binding */ |
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static const struct of_device_id xilinxfb_of_match[] = { |
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{ .compatible = "xlnx,xps-tft-1.00.a", }, |
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{ .compatible = "xlnx,xps-tft-2.00.a", }, |
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{ .compatible = "xlnx,xps-tft-2.01.a", }, |
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{ .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", }, |
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{ .compatible = "xlnx,plb-dvi-cntlr-ref-1.00.c", }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, xilinxfb_of_match); |
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|
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static struct platform_driver xilinxfb_of_driver = { |
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.probe = xilinxfb_of_probe, |
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.remove = xilinxfb_of_remove, |
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.driver = { |
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.name = DRIVER_NAME, |
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.of_match_table = xilinxfb_of_match, |
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}, |
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}; |
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module_platform_driver(xilinxfb_of_driver); |
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|
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MODULE_AUTHOR("MontaVista Software, Inc. <[email protected]>"); |
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MODULE_DESCRIPTION("Xilinx TFT frame buffer driver"); |
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MODULE_LICENSE("GPL");
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