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1813 lines
46 KiB
1813 lines
46 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* linux/drivers/video/s3c-fb.c |
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* |
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* Copyright 2008 Openmoko Inc. |
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* Copyright 2008-2010 Simtec Electronics |
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* Ben Dooks <[email protected]> |
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* http://armlinux.simtec.co.uk/ |
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* |
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* Samsung SoC Framebuffer driver |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/slab.h> |
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#include <linux/init.h> |
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#include <linux/clk.h> |
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#include <linux/fb.h> |
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#include <linux/io.h> |
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#include <linux/uaccess.h> |
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#include <linux/interrupt.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/platform_data/video_s3c.h> |
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#include <video/samsung_fimd.h> |
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|
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/* This driver will export a number of framebuffer interfaces depending |
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* on the configuration passed in via the platform data. Each fb instance |
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* maps to a hardware window. Currently there is no support for runtime |
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* setting of the alpha-blending functions that each window has, so only |
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* window 0 is actually useful. |
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* |
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* Window 0 is treated specially, it is used for the basis of the LCD |
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* output timings and as the control for the output power-down state. |
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*/ |
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|
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/* note, the previous use of <mach/regs-fb.h> to get platform specific data |
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* has been replaced by using the platform device name to pick the correct |
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* configuration data for the system. |
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*/ |
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|
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#ifdef CONFIG_FB_S3C_DEBUG_REGWRITE |
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#undef writel |
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#define writel(v, r) do { \ |
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pr_debug("%s: %08x => %p\n", __func__, (unsigned int)v, r); \ |
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__raw_writel(v, r); \ |
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} while (0) |
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#endif /* FB_S3C_DEBUG_REGWRITE */ |
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|
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/* irq_flags bits */ |
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#define S3C_FB_VSYNC_IRQ_EN 0 |
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#define VSYNC_TIMEOUT_MSEC 50 |
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struct s3c_fb; |
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#define VALID_BPP(x) (1 << ((x) - 1)) |
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#define OSD_BASE(win, variant) ((variant).osd + ((win) * (variant).osd_stride)) |
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#define VIDOSD_A(win, variant) (OSD_BASE(win, variant) + 0x00) |
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#define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04) |
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#define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08) |
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#define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C) |
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|
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/** |
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* struct s3c_fb_variant - fb variant information |
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* @is_2443: Set if S3C2443/S3C2416 style hardware. |
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* @nr_windows: The number of windows. |
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* @vidtcon: The base for the VIDTCONx registers |
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* @wincon: The base for the WINxCON registers. |
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* @winmap: The base for the WINxMAP registers. |
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* @keycon: The abse for the WxKEYCON registers. |
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* @buf_start: Offset of buffer start registers. |
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* @buf_size: Offset of buffer size registers. |
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* @buf_end: Offset of buffer end registers. |
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* @osd: The base for the OSD registers. |
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* @osd_stride: stride of osd |
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* @palette: Address of palette memory, or 0 if none. |
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* @has_prtcon: Set if has PRTCON register. |
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* @has_shadowcon: Set if has SHADOWCON register. |
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* @has_blendcon: Set if has BLENDCON register. |
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* @has_clksel: Set if VIDCON0 register has CLKSEL bit. |
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* @has_fixvclk: Set if VIDCON1 register has FIXVCLK bits. |
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*/ |
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struct s3c_fb_variant { |
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unsigned int is_2443:1; |
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unsigned short nr_windows; |
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unsigned int vidtcon; |
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unsigned short wincon; |
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unsigned short winmap; |
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unsigned short keycon; |
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unsigned short buf_start; |
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unsigned short buf_end; |
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unsigned short buf_size; |
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unsigned short osd; |
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unsigned short osd_stride; |
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unsigned short palette[S3C_FB_MAX_WIN]; |
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|
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unsigned int has_prtcon:1; |
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unsigned int has_shadowcon:1; |
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unsigned int has_blendcon:1; |
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unsigned int has_clksel:1; |
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unsigned int has_fixvclk:1; |
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}; |
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/** |
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* struct s3c_fb_win_variant |
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* @has_osd_c: Set if has OSD C register. |
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* @has_osd_d: Set if has OSD D register. |
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* @has_osd_alpha: Set if can change alpha transparency for a window. |
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* @palette_sz: Size of palette in entries. |
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* @palette_16bpp: Set if palette is 16bits wide. |
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* @osd_size_off: If != 0, supports setting up OSD for a window; the appropriate |
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* register is located at the given offset from OSD_BASE. |
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* @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel. |
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* |
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* valid_bpp bit x is set if (x+1)BPP is supported. |
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*/ |
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struct s3c_fb_win_variant { |
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unsigned int has_osd_c:1; |
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unsigned int has_osd_d:1; |
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unsigned int has_osd_alpha:1; |
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unsigned int palette_16bpp:1; |
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unsigned short osd_size_off; |
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unsigned short palette_sz; |
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u32 valid_bpp; |
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}; |
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|
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/** |
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* struct s3c_fb_driverdata - per-device type driver data for init time. |
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* @variant: The variant information for this driver. |
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* @win: The window information for each window. |
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*/ |
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struct s3c_fb_driverdata { |
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struct s3c_fb_variant variant; |
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struct s3c_fb_win_variant *win[S3C_FB_MAX_WIN]; |
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}; |
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/** |
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* struct s3c_fb_palette - palette information |
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* @r: Red bitfield. |
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* @g: Green bitfield. |
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* @b: Blue bitfield. |
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* @a: Alpha bitfield. |
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*/ |
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struct s3c_fb_palette { |
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struct fb_bitfield r; |
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struct fb_bitfield g; |
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struct fb_bitfield b; |
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struct fb_bitfield a; |
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}; |
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/** |
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* struct s3c_fb_win - per window private data for each framebuffer. |
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* @windata: The platform data supplied for the window configuration. |
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* @parent: The hardware that this window is part of. |
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* @fbinfo: Pointer pack to the framebuffer info for this window. |
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* @variant: The variant information for this window. |
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* @palette_buffer: Buffer/cache to hold palette entries. |
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* @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/ |
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* @index: The window number of this window. |
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* @palette: The bitfields for changing r/g/b into a hardware palette entry. |
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*/ |
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struct s3c_fb_win { |
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struct s3c_fb_pd_win *windata; |
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struct s3c_fb *parent; |
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struct fb_info *fbinfo; |
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struct s3c_fb_palette palette; |
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struct s3c_fb_win_variant variant; |
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u32 *palette_buffer; |
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u32 pseudo_palette[16]; |
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unsigned int index; |
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}; |
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/** |
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* struct s3c_fb_vsync - vsync information |
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* @wait: a queue for processes waiting for vsync |
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* @count: vsync interrupt count |
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*/ |
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struct s3c_fb_vsync { |
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wait_queue_head_t wait; |
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unsigned int count; |
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}; |
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|
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/** |
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* struct s3c_fb - overall hardware state of the hardware |
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* @slock: The spinlock protection for this data structure. |
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* @dev: The device that we bound to, for printing, etc. |
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* @bus_clk: The clk (hclk) feeding our interface and possibly pixclk. |
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* @lcd_clk: The clk (sclk) feeding pixclk. |
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* @regs: The mapped hardware registers. |
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* @variant: Variant information for this hardware. |
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* @enabled: A bitmask of enabled hardware windows. |
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* @output_on: Flag if the physical output is enabled. |
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* @pdata: The platform configuration data passed with the device. |
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* @windows: The hardware windows that have been claimed. |
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* @irq_no: IRQ line number |
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* @irq_flags: irq flags |
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* @vsync_info: VSYNC-related information (count, queues...) |
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*/ |
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struct s3c_fb { |
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spinlock_t slock; |
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struct device *dev; |
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struct clk *bus_clk; |
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struct clk *lcd_clk; |
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void __iomem *regs; |
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struct s3c_fb_variant variant; |
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unsigned char enabled; |
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bool output_on; |
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struct s3c_fb_platdata *pdata; |
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struct s3c_fb_win *windows[S3C_FB_MAX_WIN]; |
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int irq_no; |
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unsigned long irq_flags; |
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struct s3c_fb_vsync vsync_info; |
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}; |
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/** |
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* s3c_fb_validate_win_bpp - validate the bits-per-pixel for this mode. |
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* @win: The device window. |
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* @bpp: The bit depth. |
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*/ |
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static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp) |
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{ |
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return win->variant.valid_bpp & VALID_BPP(bpp); |
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} |
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/** |
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* s3c_fb_check_var() - framebuffer layer request to verify a given mode. |
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* @var: The screen information to verify. |
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* @info: The framebuffer device. |
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* |
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* Framebuffer layer call to verify the given information and allow us to |
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* update various information depending on the hardware capabilities. |
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*/ |
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static int s3c_fb_check_var(struct fb_var_screeninfo *var, |
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struct fb_info *info) |
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{ |
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struct s3c_fb_win *win = info->par; |
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struct s3c_fb *sfb = win->parent; |
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dev_dbg(sfb->dev, "checking parameters\n"); |
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var->xres_virtual = max(var->xres_virtual, var->xres); |
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var->yres_virtual = max(var->yres_virtual, var->yres); |
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if (!s3c_fb_validate_win_bpp(win, var->bits_per_pixel)) { |
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dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n", |
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win->index, var->bits_per_pixel); |
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return -EINVAL; |
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} |
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/* always ensure these are zero, for drop through cases below */ |
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var->transp.offset = 0; |
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var->transp.length = 0; |
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switch (var->bits_per_pixel) { |
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case 1: |
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case 2: |
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case 4: |
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case 8: |
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if (sfb->variant.palette[win->index] != 0) { |
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/* non palletised, A:1,R:2,G:3,B:2 mode */ |
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var->red.offset = 5; |
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var->green.offset = 2; |
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var->blue.offset = 0; |
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var->red.length = 2; |
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var->green.length = 3; |
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var->blue.length = 2; |
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var->transp.offset = 7; |
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var->transp.length = 1; |
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} else { |
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var->red.offset = 0; |
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var->red.length = var->bits_per_pixel; |
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var->green = var->red; |
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var->blue = var->red; |
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} |
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break; |
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case 19: |
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/* 666 with one bit alpha/transparency */ |
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var->transp.offset = 18; |
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var->transp.length = 1; |
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fallthrough; |
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case 18: |
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var->bits_per_pixel = 32; |
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/* 666 format */ |
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var->red.offset = 12; |
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var->green.offset = 6; |
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var->blue.offset = 0; |
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var->red.length = 6; |
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var->green.length = 6; |
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var->blue.length = 6; |
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break; |
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case 16: |
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/* 16 bpp, 565 format */ |
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var->red.offset = 11; |
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var->green.offset = 5; |
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var->blue.offset = 0; |
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var->red.length = 5; |
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var->green.length = 6; |
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var->blue.length = 5; |
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break; |
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case 32: |
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case 28: |
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case 25: |
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var->transp.length = var->bits_per_pixel - 24; |
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var->transp.offset = 24; |
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fallthrough; |
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case 24: |
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/* our 24bpp is unpacked, so 32bpp */ |
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var->bits_per_pixel = 32; |
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var->red.offset = 16; |
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var->red.length = 8; |
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var->green.offset = 8; |
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var->green.length = 8; |
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var->blue.offset = 0; |
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var->blue.length = 8; |
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break; |
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default: |
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dev_err(sfb->dev, "invalid bpp\n"); |
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return -EINVAL; |
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} |
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dev_dbg(sfb->dev, "%s: verified parameters\n", __func__); |
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return 0; |
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} |
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/** |
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* s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock. |
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* @sfb: The hardware state. |
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* @pixclk: The pixel clock wanted, in picoseconds. |
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* |
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* Given the specified pixel clock, work out the necessary divider to get |
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* close to the output frequency. |
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*/ |
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static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk) |
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{ |
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unsigned long clk; |
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unsigned long long tmp; |
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unsigned int result; |
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if (sfb->variant.has_clksel) |
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clk = clk_get_rate(sfb->bus_clk); |
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else |
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clk = clk_get_rate(sfb->lcd_clk); |
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tmp = (unsigned long long)clk; |
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tmp *= pixclk; |
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do_div(tmp, 1000000000UL); |
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result = (unsigned int)tmp / 1000; |
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dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n", |
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pixclk, clk, result, result ? clk / result : clk); |
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return result; |
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} |
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/** |
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* s3c_fb_align_word() - align pixel count to word boundary |
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* @bpp: The number of bits per pixel |
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* @pix: The value to be aligned. |
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* |
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* Align the given pixel count so that it will start on an 32bit word |
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* boundary. |
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*/ |
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static int s3c_fb_align_word(unsigned int bpp, unsigned int pix) |
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{ |
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int pix_per_word; |
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if (bpp > 16) |
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return pix; |
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pix_per_word = (8 * 32) / bpp; |
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return ALIGN(pix, pix_per_word); |
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} |
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/** |
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* vidosd_set_size() - set OSD size for a window |
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* |
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* @win: the window to set OSD size for |
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* @size: OSD size register value |
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*/ |
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static void vidosd_set_size(struct s3c_fb_win *win, u32 size) |
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{ |
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struct s3c_fb *sfb = win->parent; |
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/* OSD can be set up if osd_size_off != 0 for this window */ |
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if (win->variant.osd_size_off) |
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writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant) |
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+ win->variant.osd_size_off); |
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} |
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/** |
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* vidosd_set_alpha() - set alpha transparency for a window |
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* |
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* @win: the window to set OSD size for |
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* @alpha: alpha register value |
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*/ |
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static void vidosd_set_alpha(struct s3c_fb_win *win, u32 alpha) |
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{ |
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struct s3c_fb *sfb = win->parent; |
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if (win->variant.has_osd_alpha) |
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writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant)); |
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} |
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|
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/** |
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* shadow_protect_win() - disable updating values from shadow registers at vsync |
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* |
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* @win: window to protect registers for |
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* @protect: 1 to protect (disable updates) |
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*/ |
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static void shadow_protect_win(struct s3c_fb_win *win, bool protect) |
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{ |
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struct s3c_fb *sfb = win->parent; |
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u32 reg; |
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if (protect) { |
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if (sfb->variant.has_prtcon) { |
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writel(PRTCON_PROTECT, sfb->regs + PRTCON); |
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} else if (sfb->variant.has_shadowcon) { |
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reg = readl(sfb->regs + SHADOWCON); |
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writel(reg | SHADOWCON_WINx_PROTECT(win->index), |
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sfb->regs + SHADOWCON); |
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} |
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} else { |
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if (sfb->variant.has_prtcon) { |
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writel(0, sfb->regs + PRTCON); |
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} else if (sfb->variant.has_shadowcon) { |
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reg = readl(sfb->regs + SHADOWCON); |
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writel(reg & ~SHADOWCON_WINx_PROTECT(win->index), |
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sfb->regs + SHADOWCON); |
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} |
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} |
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} |
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|
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/** |
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* s3c_fb_enable() - Set the state of the main LCD output |
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* @sfb: The main framebuffer state. |
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* @enable: The state to set. |
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*/ |
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static void s3c_fb_enable(struct s3c_fb *sfb, int enable) |
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{ |
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u32 vidcon0 = readl(sfb->regs + VIDCON0); |
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|
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if (enable && !sfb->output_on) |
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pm_runtime_get_sync(sfb->dev); |
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|
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if (enable) { |
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vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F; |
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} else { |
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/* see the note in the framebuffer datasheet about |
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* why you cannot take both of these bits down at the |
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* same time. */ |
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|
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if (vidcon0 & VIDCON0_ENVID) { |
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vidcon0 |= VIDCON0_ENVID; |
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vidcon0 &= ~VIDCON0_ENVID_F; |
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} |
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} |
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writel(vidcon0, sfb->regs + VIDCON0); |
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|
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if (!enable && sfb->output_on) |
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pm_runtime_put_sync(sfb->dev); |
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|
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sfb->output_on = enable; |
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} |
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|
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/** |
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* s3c_fb_set_par() - framebuffer request to set new framebuffer state. |
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* @info: The framebuffer to change. |
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* |
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* Framebuffer layer request to set a new mode for the specified framebuffer |
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*/ |
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static int s3c_fb_set_par(struct fb_info *info) |
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{ |
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struct fb_var_screeninfo *var = &info->var; |
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struct s3c_fb_win *win = info->par; |
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struct s3c_fb *sfb = win->parent; |
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void __iomem *regs = sfb->regs; |
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void __iomem *buf = regs; |
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int win_no = win->index; |
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u32 alpha = 0; |
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u32 data; |
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u32 pagewidth; |
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|
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dev_dbg(sfb->dev, "setting framebuffer parameters\n"); |
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|
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pm_runtime_get_sync(sfb->dev); |
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|
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shadow_protect_win(win, 1); |
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|
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switch (var->bits_per_pixel) { |
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case 32: |
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case 24: |
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case 16: |
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case 12: |
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info->fix.visual = FB_VISUAL_TRUECOLOR; |
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break; |
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case 8: |
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if (win->variant.palette_sz >= 256) |
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info->fix.visual = FB_VISUAL_PSEUDOCOLOR; |
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else |
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info->fix.visual = FB_VISUAL_TRUECOLOR; |
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break; |
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case 1: |
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info->fix.visual = FB_VISUAL_MONO01; |
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break; |
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default: |
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info->fix.visual = FB_VISUAL_PSEUDOCOLOR; |
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break; |
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} |
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|
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info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8; |
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|
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info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0; |
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info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0; |
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|
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/* disable the window whilst we update it */ |
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writel(0, regs + WINCON(win_no)); |
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|
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if (!sfb->output_on) |
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s3c_fb_enable(sfb, 1); |
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|
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/* write the buffer address */ |
|
|
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/* start and end registers stride is 8 */ |
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buf = regs + win_no * 8; |
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|
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writel(info->fix.smem_start, buf + sfb->variant.buf_start); |
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|
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data = info->fix.smem_start + info->fix.line_length * var->yres; |
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writel(data, buf + sfb->variant.buf_end); |
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|
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pagewidth = (var->xres * var->bits_per_pixel) >> 3; |
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data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) | |
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VIDW_BUF_SIZE_PAGEWIDTH(pagewidth) | |
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VIDW_BUF_SIZE_OFFSET_E(info->fix.line_length - pagewidth) | |
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VIDW_BUF_SIZE_PAGEWIDTH_E(pagewidth); |
|
writel(data, regs + sfb->variant.buf_size + (win_no * 4)); |
|
|
|
/* write 'OSD' registers to control position of framebuffer */ |
|
|
|
data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0) | |
|
VIDOSDxA_TOPLEFT_X_E(0) | VIDOSDxA_TOPLEFT_Y_E(0); |
|
writel(data, regs + VIDOSD_A(win_no, sfb->variant)); |
|
|
|
data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel, |
|
var->xres - 1)) | |
|
VIDOSDxB_BOTRIGHT_Y(var->yres - 1) | |
|
VIDOSDxB_BOTRIGHT_X_E(s3c_fb_align_word(var->bits_per_pixel, |
|
var->xres - 1)) | |
|
VIDOSDxB_BOTRIGHT_Y_E(var->yres - 1); |
|
|
|
writel(data, regs + VIDOSD_B(win_no, sfb->variant)); |
|
|
|
data = var->xres * var->yres; |
|
|
|
alpha = VIDISD14C_ALPHA1_R(0xf) | |
|
VIDISD14C_ALPHA1_G(0xf) | |
|
VIDISD14C_ALPHA1_B(0xf); |
|
|
|
vidosd_set_alpha(win, alpha); |
|
vidosd_set_size(win, data); |
|
|
|
/* Enable DMA channel for this window */ |
|
if (sfb->variant.has_shadowcon) { |
|
data = readl(sfb->regs + SHADOWCON); |
|
data |= SHADOWCON_CHx_ENABLE(win_no); |
|
writel(data, sfb->regs + SHADOWCON); |
|
} |
|
|
|
data = WINCONx_ENWIN; |
|
sfb->enabled |= (1 << win->index); |
|
|
|
/* note, since we have to round up the bits-per-pixel, we end up |
|
* relying on the bitfield information for r/g/b/a to work out |
|
* exactly which mode of operation is intended. */ |
|
|
|
switch (var->bits_per_pixel) { |
|
case 1: |
|
data |= WINCON0_BPPMODE_1BPP; |
|
data |= WINCONx_BITSWP; |
|
data |= WINCONx_BURSTLEN_4WORD; |
|
break; |
|
case 2: |
|
data |= WINCON0_BPPMODE_2BPP; |
|
data |= WINCONx_BITSWP; |
|
data |= WINCONx_BURSTLEN_8WORD; |
|
break; |
|
case 4: |
|
data |= WINCON0_BPPMODE_4BPP; |
|
data |= WINCONx_BITSWP; |
|
data |= WINCONx_BURSTLEN_8WORD; |
|
break; |
|
case 8: |
|
if (var->transp.length != 0) |
|
data |= WINCON1_BPPMODE_8BPP_1232; |
|
else |
|
data |= WINCON0_BPPMODE_8BPP_PALETTE; |
|
data |= WINCONx_BURSTLEN_8WORD; |
|
data |= WINCONx_BYTSWP; |
|
break; |
|
case 16: |
|
if (var->transp.length != 0) |
|
data |= WINCON1_BPPMODE_16BPP_A1555; |
|
else |
|
data |= WINCON0_BPPMODE_16BPP_565; |
|
data |= WINCONx_HAWSWP; |
|
data |= WINCONx_BURSTLEN_16WORD; |
|
break; |
|
case 24: |
|
case 32: |
|
if (var->red.length == 6) { |
|
if (var->transp.length != 0) |
|
data |= WINCON1_BPPMODE_19BPP_A1666; |
|
else |
|
data |= WINCON1_BPPMODE_18BPP_666; |
|
} else if (var->transp.length == 1) |
|
data |= WINCON1_BPPMODE_25BPP_A1888 |
|
| WINCON1_BLD_PIX; |
|
else if ((var->transp.length == 4) || |
|
(var->transp.length == 8)) |
|
data |= WINCON1_BPPMODE_28BPP_A4888 |
|
| WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; |
|
else |
|
data |= WINCON0_BPPMODE_24BPP_888; |
|
|
|
data |= WINCONx_WSWP; |
|
data |= WINCONx_BURSTLEN_16WORD; |
|
break; |
|
} |
|
|
|
/* Enable the colour keying for the window below this one */ |
|
if (win_no > 0) { |
|
u32 keycon0_data = 0, keycon1_data = 0; |
|
void __iomem *keycon = regs + sfb->variant.keycon; |
|
|
|
keycon0_data = ~(WxKEYCON0_KEYBL_EN | |
|
WxKEYCON0_KEYEN_F | |
|
WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); |
|
|
|
keycon1_data = WxKEYCON1_COLVAL(0xffffff); |
|
|
|
keycon += (win_no - 1) * 8; |
|
|
|
writel(keycon0_data, keycon + WKEYCON0); |
|
writel(keycon1_data, keycon + WKEYCON1); |
|
} |
|
|
|
writel(data, regs + sfb->variant.wincon + (win_no * 4)); |
|
writel(0x0, regs + sfb->variant.winmap + (win_no * 4)); |
|
|
|
/* Set alpha value width */ |
|
if (sfb->variant.has_blendcon) { |
|
data = readl(sfb->regs + BLENDCON); |
|
data &= ~BLENDCON_NEW_MASK; |
|
if (var->transp.length > 4) |
|
data |= BLENDCON_NEW_8BIT_ALPHA_VALUE; |
|
else |
|
data |= BLENDCON_NEW_4BIT_ALPHA_VALUE; |
|
writel(data, sfb->regs + BLENDCON); |
|
} |
|
|
|
shadow_protect_win(win, 0); |
|
|
|
pm_runtime_put_sync(sfb->dev); |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* s3c_fb_update_palette() - set or schedule a palette update. |
|
* @sfb: The hardware information. |
|
* @win: The window being updated. |
|
* @reg: The palette index being changed. |
|
* @value: The computed palette value. |
|
* |
|
* Change the value of a palette register, either by directly writing to |
|
* the palette (this requires the palette RAM to be disconnected from the |
|
* hardware whilst this is in progress) or schedule the update for later. |
|
* |
|
* At the moment, since we have no VSYNC interrupt support, we simply set |
|
* the palette entry directly. |
|
*/ |
|
static void s3c_fb_update_palette(struct s3c_fb *sfb, |
|
struct s3c_fb_win *win, |
|
unsigned int reg, |
|
u32 value) |
|
{ |
|
void __iomem *palreg; |
|
u32 palcon; |
|
|
|
palreg = sfb->regs + sfb->variant.palette[win->index]; |
|
|
|
dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n", |
|
__func__, win->index, reg, palreg, value); |
|
|
|
win->palette_buffer[reg] = value; |
|
|
|
palcon = readl(sfb->regs + WPALCON); |
|
writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON); |
|
|
|
if (win->variant.palette_16bpp) |
|
writew(value, palreg + (reg * 2)); |
|
else |
|
writel(value, palreg + (reg * 4)); |
|
|
|
writel(palcon, sfb->regs + WPALCON); |
|
} |
|
|
|
static inline unsigned int chan_to_field(unsigned int chan, |
|
struct fb_bitfield *bf) |
|
{ |
|
chan &= 0xffff; |
|
chan >>= 16 - bf->length; |
|
return chan << bf->offset; |
|
} |
|
|
|
/** |
|
* s3c_fb_setcolreg() - framebuffer layer request to change palette. |
|
* @regno: The palette index to change. |
|
* @red: The red field for the palette data. |
|
* @green: The green field for the palette data. |
|
* @blue: The blue field for the palette data. |
|
* @transp: The transparency (alpha) field for the palette data. |
|
* @info: The framebuffer being changed. |
|
*/ |
|
static int s3c_fb_setcolreg(unsigned regno, |
|
unsigned red, unsigned green, unsigned blue, |
|
unsigned transp, struct fb_info *info) |
|
{ |
|
struct s3c_fb_win *win = info->par; |
|
struct s3c_fb *sfb = win->parent; |
|
unsigned int val; |
|
|
|
dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n", |
|
__func__, win->index, regno, red, green, blue); |
|
|
|
pm_runtime_get_sync(sfb->dev); |
|
|
|
switch (info->fix.visual) { |
|
case FB_VISUAL_TRUECOLOR: |
|
/* true-colour, use pseudo-palette */ |
|
|
|
if (regno < 16) { |
|
u32 *pal = info->pseudo_palette; |
|
|
|
val = chan_to_field(red, &info->var.red); |
|
val |= chan_to_field(green, &info->var.green); |
|
val |= chan_to_field(blue, &info->var.blue); |
|
|
|
pal[regno] = val; |
|
} |
|
break; |
|
|
|
case FB_VISUAL_PSEUDOCOLOR: |
|
if (regno < win->variant.palette_sz) { |
|
val = chan_to_field(red, &win->palette.r); |
|
val |= chan_to_field(green, &win->palette.g); |
|
val |= chan_to_field(blue, &win->palette.b); |
|
|
|
s3c_fb_update_palette(sfb, win, regno, val); |
|
} |
|
|
|
break; |
|
|
|
default: |
|
pm_runtime_put_sync(sfb->dev); |
|
return 1; /* unknown type */ |
|
} |
|
|
|
pm_runtime_put_sync(sfb->dev); |
|
return 0; |
|
} |
|
|
|
/** |
|
* s3c_fb_blank() - blank or unblank the given window |
|
* @blank_mode: The blank state from FB_BLANK_* |
|
* @info: The framebuffer to blank. |
|
* |
|
* Framebuffer layer request to change the power state. |
|
*/ |
|
static int s3c_fb_blank(int blank_mode, struct fb_info *info) |
|
{ |
|
struct s3c_fb_win *win = info->par; |
|
struct s3c_fb *sfb = win->parent; |
|
unsigned int index = win->index; |
|
u32 wincon; |
|
u32 output_on = sfb->output_on; |
|
|
|
dev_dbg(sfb->dev, "blank mode %d\n", blank_mode); |
|
|
|
pm_runtime_get_sync(sfb->dev); |
|
|
|
wincon = readl(sfb->regs + sfb->variant.wincon + (index * 4)); |
|
|
|
switch (blank_mode) { |
|
case FB_BLANK_POWERDOWN: |
|
wincon &= ~WINCONx_ENWIN; |
|
sfb->enabled &= ~(1 << index); |
|
fallthrough; /* to FB_BLANK_NORMAL */ |
|
|
|
case FB_BLANK_NORMAL: |
|
/* disable the DMA and display 0x0 (black) */ |
|
shadow_protect_win(win, 1); |
|
writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0), |
|
sfb->regs + sfb->variant.winmap + (index * 4)); |
|
shadow_protect_win(win, 0); |
|
break; |
|
|
|
case FB_BLANK_UNBLANK: |
|
shadow_protect_win(win, 1); |
|
writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4)); |
|
shadow_protect_win(win, 0); |
|
wincon |= WINCONx_ENWIN; |
|
sfb->enabled |= (1 << index); |
|
break; |
|
|
|
case FB_BLANK_VSYNC_SUSPEND: |
|
case FB_BLANK_HSYNC_SUSPEND: |
|
default: |
|
pm_runtime_put_sync(sfb->dev); |
|
return 1; |
|
} |
|
|
|
shadow_protect_win(win, 1); |
|
writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4)); |
|
|
|
/* Check the enabled state to see if we need to be running the |
|
* main LCD interface, as if there are no active windows then |
|
* it is highly likely that we also do not need to output |
|
* anything. |
|
*/ |
|
s3c_fb_enable(sfb, sfb->enabled ? 1 : 0); |
|
shadow_protect_win(win, 0); |
|
|
|
pm_runtime_put_sync(sfb->dev); |
|
|
|
return output_on == sfb->output_on; |
|
} |
|
|
|
/** |
|
* s3c_fb_pan_display() - Pan the display. |
|
* |
|
* Note that the offsets can be written to the device at any time, as their |
|
* values are latched at each vsync automatically. This also means that only |
|
* the last call to this function will have any effect on next vsync, but |
|
* there is no need to sleep waiting for it to prevent tearing. |
|
* |
|
* @var: The screen information to verify. |
|
* @info: The framebuffer device. |
|
*/ |
|
static int s3c_fb_pan_display(struct fb_var_screeninfo *var, |
|
struct fb_info *info) |
|
{ |
|
struct s3c_fb_win *win = info->par; |
|
struct s3c_fb *sfb = win->parent; |
|
void __iomem *buf = sfb->regs + win->index * 8; |
|
unsigned int start_boff, end_boff; |
|
|
|
pm_runtime_get_sync(sfb->dev); |
|
|
|
/* Offset in bytes to the start of the displayed area */ |
|
start_boff = var->yoffset * info->fix.line_length; |
|
/* X offset depends on the current bpp */ |
|
if (info->var.bits_per_pixel >= 8) { |
|
start_boff += var->xoffset * (info->var.bits_per_pixel >> 3); |
|
} else { |
|
switch (info->var.bits_per_pixel) { |
|
case 4: |
|
start_boff += var->xoffset >> 1; |
|
break; |
|
case 2: |
|
start_boff += var->xoffset >> 2; |
|
break; |
|
case 1: |
|
start_boff += var->xoffset >> 3; |
|
break; |
|
default: |
|
dev_err(sfb->dev, "invalid bpp\n"); |
|
pm_runtime_put_sync(sfb->dev); |
|
return -EINVAL; |
|
} |
|
} |
|
/* Offset in bytes to the end of the displayed area */ |
|
end_boff = start_boff + info->var.yres * info->fix.line_length; |
|
|
|
/* Temporarily turn off per-vsync update from shadow registers until |
|
* both start and end addresses are updated to prevent corruption */ |
|
shadow_protect_win(win, 1); |
|
|
|
writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start); |
|
writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end); |
|
|
|
shadow_protect_win(win, 0); |
|
|
|
pm_runtime_put_sync(sfb->dev); |
|
return 0; |
|
} |
|
|
|
/** |
|
* s3c_fb_enable_irq() - enable framebuffer interrupts |
|
* @sfb: main hardware state |
|
*/ |
|
static void s3c_fb_enable_irq(struct s3c_fb *sfb) |
|
{ |
|
void __iomem *regs = sfb->regs; |
|
u32 irq_ctrl_reg; |
|
|
|
if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) { |
|
/* IRQ disabled, enable it */ |
|
irq_ctrl_reg = readl(regs + VIDINTCON0); |
|
|
|
irq_ctrl_reg |= VIDINTCON0_INT_ENABLE; |
|
irq_ctrl_reg |= VIDINTCON0_INT_FRAME; |
|
|
|
irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK; |
|
irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC; |
|
irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK; |
|
irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE; |
|
|
|
writel(irq_ctrl_reg, regs + VIDINTCON0); |
|
} |
|
} |
|
|
|
/** |
|
* s3c_fb_disable_irq() - disable framebuffer interrupts |
|
* @sfb: main hardware state |
|
*/ |
|
static void s3c_fb_disable_irq(struct s3c_fb *sfb) |
|
{ |
|
void __iomem *regs = sfb->regs; |
|
u32 irq_ctrl_reg; |
|
|
|
if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) { |
|
/* IRQ enabled, disable it */ |
|
irq_ctrl_reg = readl(regs + VIDINTCON0); |
|
|
|
irq_ctrl_reg &= ~VIDINTCON0_INT_FRAME; |
|
irq_ctrl_reg &= ~VIDINTCON0_INT_ENABLE; |
|
|
|
writel(irq_ctrl_reg, regs + VIDINTCON0); |
|
} |
|
} |
|
|
|
static irqreturn_t s3c_fb_irq(int irq, void *dev_id) |
|
{ |
|
struct s3c_fb *sfb = dev_id; |
|
void __iomem *regs = sfb->regs; |
|
u32 irq_sts_reg; |
|
|
|
spin_lock(&sfb->slock); |
|
|
|
irq_sts_reg = readl(regs + VIDINTCON1); |
|
|
|
if (irq_sts_reg & VIDINTCON1_INT_FRAME) { |
|
|
|
/* VSYNC interrupt, accept it */ |
|
writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1); |
|
|
|
sfb->vsync_info.count++; |
|
wake_up_interruptible(&sfb->vsync_info.wait); |
|
} |
|
|
|
/* We only support waiting for VSYNC for now, so it's safe |
|
* to always disable irqs here. |
|
*/ |
|
s3c_fb_disable_irq(sfb); |
|
|
|
spin_unlock(&sfb->slock); |
|
return IRQ_HANDLED; |
|
} |
|
|
|
/** |
|
* s3c_fb_wait_for_vsync() - sleep until next VSYNC interrupt or timeout |
|
* @sfb: main hardware state |
|
* @crtc: head index. |
|
*/ |
|
static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc) |
|
{ |
|
unsigned long count; |
|
int ret; |
|
|
|
if (crtc != 0) |
|
return -ENODEV; |
|
|
|
pm_runtime_get_sync(sfb->dev); |
|
|
|
count = sfb->vsync_info.count; |
|
s3c_fb_enable_irq(sfb); |
|
ret = wait_event_interruptible_timeout(sfb->vsync_info.wait, |
|
count != sfb->vsync_info.count, |
|
msecs_to_jiffies(VSYNC_TIMEOUT_MSEC)); |
|
|
|
pm_runtime_put_sync(sfb->dev); |
|
|
|
if (ret == 0) |
|
return -ETIMEDOUT; |
|
|
|
return 0; |
|
} |
|
|
|
static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd, |
|
unsigned long arg) |
|
{ |
|
struct s3c_fb_win *win = info->par; |
|
struct s3c_fb *sfb = win->parent; |
|
int ret; |
|
u32 crtc; |
|
|
|
switch (cmd) { |
|
case FBIO_WAITFORVSYNC: |
|
if (get_user(crtc, (u32 __user *)arg)) { |
|
ret = -EFAULT; |
|
break; |
|
} |
|
|
|
ret = s3c_fb_wait_for_vsync(sfb, crtc); |
|
break; |
|
default: |
|
ret = -ENOTTY; |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static const struct fb_ops s3c_fb_ops = { |
|
.owner = THIS_MODULE, |
|
.fb_check_var = s3c_fb_check_var, |
|
.fb_set_par = s3c_fb_set_par, |
|
.fb_blank = s3c_fb_blank, |
|
.fb_setcolreg = s3c_fb_setcolreg, |
|
.fb_fillrect = cfb_fillrect, |
|
.fb_copyarea = cfb_copyarea, |
|
.fb_imageblit = cfb_imageblit, |
|
.fb_pan_display = s3c_fb_pan_display, |
|
.fb_ioctl = s3c_fb_ioctl, |
|
}; |
|
|
|
/** |
|
* s3c_fb_missing_pixclock() - calculates pixel clock |
|
* @mode: The video mode to change. |
|
* |
|
* Calculate the pixel clock when none has been given through platform data. |
|
*/ |
|
static void s3c_fb_missing_pixclock(struct fb_videomode *mode) |
|
{ |
|
u64 pixclk = 1000000000000ULL; |
|
u32 div; |
|
|
|
div = mode->left_margin + mode->hsync_len + mode->right_margin + |
|
mode->xres; |
|
div *= mode->upper_margin + mode->vsync_len + mode->lower_margin + |
|
mode->yres; |
|
div *= mode->refresh ? : 60; |
|
|
|
do_div(pixclk, div); |
|
|
|
mode->pixclock = pixclk; |
|
} |
|
|
|
/** |
|
* s3c_fb_alloc_memory() - allocate display memory for framebuffer window |
|
* @sfb: The base resources for the hardware. |
|
* @win: The window to initialise memory for. |
|
* |
|
* Allocate memory for the given framebuffer. |
|
*/ |
|
static int s3c_fb_alloc_memory(struct s3c_fb *sfb, struct s3c_fb_win *win) |
|
{ |
|
struct s3c_fb_pd_win *windata = win->windata; |
|
unsigned int real_size, virt_size, size; |
|
struct fb_info *fbi = win->fbinfo; |
|
dma_addr_t map_dma; |
|
|
|
dev_dbg(sfb->dev, "allocating memory for display\n"); |
|
|
|
real_size = windata->xres * windata->yres; |
|
virt_size = windata->virtual_x * windata->virtual_y; |
|
|
|
dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n", |
|
real_size, windata->xres, windata->yres, |
|
virt_size, windata->virtual_x, windata->virtual_y); |
|
|
|
size = (real_size > virt_size) ? real_size : virt_size; |
|
size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp; |
|
size /= 8; |
|
|
|
fbi->fix.smem_len = size; |
|
size = PAGE_ALIGN(size); |
|
|
|
dev_dbg(sfb->dev, "want %u bytes for window\n", size); |
|
|
|
fbi->screen_buffer = dma_alloc_wc(sfb->dev, size, &map_dma, GFP_KERNEL); |
|
if (!fbi->screen_buffer) |
|
return -ENOMEM; |
|
|
|
dev_dbg(sfb->dev, "mapped %x to %p\n", |
|
(unsigned int)map_dma, fbi->screen_buffer); |
|
|
|
memset(fbi->screen_buffer, 0x0, size); |
|
fbi->fix.smem_start = map_dma; |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* s3c_fb_free_memory() - free the display memory for the given window |
|
* @sfb: The base resources for the hardware. |
|
* @win: The window to free the display memory for. |
|
* |
|
* Free the display memory allocated by s3c_fb_alloc_memory(). |
|
*/ |
|
static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win) |
|
{ |
|
struct fb_info *fbi = win->fbinfo; |
|
|
|
if (fbi->screen_buffer) |
|
dma_free_wc(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len), |
|
fbi->screen_buffer, fbi->fix.smem_start); |
|
} |
|
|
|
/** |
|
* s3c_fb_release_win() - release resources for a framebuffer window. |
|
* @sfb: The base resources for the hardware. |
|
* @win: The window to cleanup the resources for. |
|
* |
|
* Release the resources that where claimed for the hardware window, |
|
* such as the framebuffer instance and any memory claimed for it. |
|
*/ |
|
static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win) |
|
{ |
|
u32 data; |
|
|
|
if (win->fbinfo) { |
|
if (sfb->variant.has_shadowcon) { |
|
data = readl(sfb->regs + SHADOWCON); |
|
data &= ~SHADOWCON_CHx_ENABLE(win->index); |
|
data &= ~SHADOWCON_CHx_LOCAL_ENABLE(win->index); |
|
writel(data, sfb->regs + SHADOWCON); |
|
} |
|
unregister_framebuffer(win->fbinfo); |
|
if (win->fbinfo->cmap.len) |
|
fb_dealloc_cmap(&win->fbinfo->cmap); |
|
s3c_fb_free_memory(sfb, win); |
|
framebuffer_release(win->fbinfo); |
|
} |
|
} |
|
|
|
/** |
|
* s3c_fb_probe_win() - register an hardware window |
|
* @sfb: The base resources for the hardware |
|
* @win_no: The window number |
|
* @variant: The variant information for this window. |
|
* @res: Pointer to where to place the resultant window. |
|
* |
|
* Allocate and do the basic initialisation for one of the hardware's graphics |
|
* windows. |
|
*/ |
|
static int s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no, |
|
struct s3c_fb_win_variant *variant, |
|
struct s3c_fb_win **res) |
|
{ |
|
struct fb_videomode initmode; |
|
struct s3c_fb_pd_win *windata; |
|
struct s3c_fb_win *win; |
|
struct fb_info *fbinfo; |
|
int palette_size; |
|
int ret; |
|
|
|
dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant); |
|
|
|
init_waitqueue_head(&sfb->vsync_info.wait); |
|
|
|
palette_size = variant->palette_sz * 4; |
|
|
|
fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) + |
|
palette_size * sizeof(u32), sfb->dev); |
|
if (!fbinfo) |
|
return -ENOMEM; |
|
|
|
windata = sfb->pdata->win[win_no]; |
|
initmode = *sfb->pdata->vtiming; |
|
|
|
WARN_ON(windata->max_bpp == 0); |
|
WARN_ON(windata->xres == 0); |
|
WARN_ON(windata->yres == 0); |
|
|
|
win = fbinfo->par; |
|
*res = win; |
|
win->variant = *variant; |
|
win->fbinfo = fbinfo; |
|
win->parent = sfb; |
|
win->windata = windata; |
|
win->index = win_no; |
|
win->palette_buffer = (u32 *)(win + 1); |
|
|
|
ret = s3c_fb_alloc_memory(sfb, win); |
|
if (ret) { |
|
dev_err(sfb->dev, "failed to allocate display memory\n"); |
|
return ret; |
|
} |
|
|
|
/* setup the r/b/g positions for the window's palette */ |
|
if (win->variant.palette_16bpp) { |
|
/* Set RGB 5:6:5 as default */ |
|
win->palette.r.offset = 11; |
|
win->palette.r.length = 5; |
|
win->palette.g.offset = 5; |
|
win->palette.g.length = 6; |
|
win->palette.b.offset = 0; |
|
win->palette.b.length = 5; |
|
|
|
} else { |
|
/* Set 8bpp or 8bpp and 1bit alpha */ |
|
win->palette.r.offset = 16; |
|
win->palette.r.length = 8; |
|
win->palette.g.offset = 8; |
|
win->palette.g.length = 8; |
|
win->palette.b.offset = 0; |
|
win->palette.b.length = 8; |
|
} |
|
|
|
/* setup the initial video mode from the window */ |
|
initmode.xres = windata->xres; |
|
initmode.yres = windata->yres; |
|
fb_videomode_to_var(&fbinfo->var, &initmode); |
|
|
|
fbinfo->fix.type = FB_TYPE_PACKED_PIXELS; |
|
fbinfo->fix.accel = FB_ACCEL_NONE; |
|
fbinfo->var.activate = FB_ACTIVATE_NOW; |
|
fbinfo->var.vmode = FB_VMODE_NONINTERLACED; |
|
fbinfo->var.bits_per_pixel = windata->default_bpp; |
|
fbinfo->fbops = &s3c_fb_ops; |
|
fbinfo->flags = FBINFO_FLAG_DEFAULT; |
|
fbinfo->pseudo_palette = &win->pseudo_palette; |
|
|
|
/* prepare to actually start the framebuffer */ |
|
|
|
ret = s3c_fb_check_var(&fbinfo->var, fbinfo); |
|
if (ret < 0) { |
|
dev_err(sfb->dev, "check_var failed on initial video params\n"); |
|
return ret; |
|
} |
|
|
|
/* create initial colour map */ |
|
|
|
ret = fb_alloc_cmap(&fbinfo->cmap, win->variant.palette_sz, 1); |
|
if (ret == 0) |
|
fb_set_cmap(&fbinfo->cmap, fbinfo); |
|
else |
|
dev_err(sfb->dev, "failed to allocate fb cmap\n"); |
|
|
|
s3c_fb_set_par(fbinfo); |
|
|
|
dev_dbg(sfb->dev, "about to register framebuffer\n"); |
|
|
|
/* run the check_var and set_par on our configuration. */ |
|
|
|
ret = register_framebuffer(fbinfo); |
|
if (ret < 0) { |
|
dev_err(sfb->dev, "failed to register framebuffer\n"); |
|
return ret; |
|
} |
|
|
|
dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id); |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* s3c_fb_set_rgb_timing() - set video timing for rgb interface. |
|
* @sfb: The base resources for the hardware. |
|
* |
|
* Set horizontal and vertical lcd rgb interface timing. |
|
*/ |
|
static void s3c_fb_set_rgb_timing(struct s3c_fb *sfb) |
|
{ |
|
struct fb_videomode *vmode = sfb->pdata->vtiming; |
|
void __iomem *regs = sfb->regs; |
|
int clkdiv; |
|
u32 data; |
|
|
|
if (!vmode->pixclock) |
|
s3c_fb_missing_pixclock(vmode); |
|
|
|
clkdiv = s3c_fb_calc_pixclk(sfb, vmode->pixclock); |
|
|
|
data = sfb->pdata->vidcon0; |
|
data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR); |
|
|
|
if (clkdiv > 1) |
|
data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR; |
|
else |
|
data &= ~VIDCON0_CLKDIR; /* 1:1 clock */ |
|
|
|
if (sfb->variant.is_2443) |
|
data |= (1 << 5); |
|
writel(data, regs + VIDCON0); |
|
|
|
data = VIDTCON0_VBPD(vmode->upper_margin - 1) | |
|
VIDTCON0_VFPD(vmode->lower_margin - 1) | |
|
VIDTCON0_VSPW(vmode->vsync_len - 1); |
|
writel(data, regs + sfb->variant.vidtcon); |
|
|
|
data = VIDTCON1_HBPD(vmode->left_margin - 1) | |
|
VIDTCON1_HFPD(vmode->right_margin - 1) | |
|
VIDTCON1_HSPW(vmode->hsync_len - 1); |
|
writel(data, regs + sfb->variant.vidtcon + 4); |
|
|
|
data = VIDTCON2_LINEVAL(vmode->yres - 1) | |
|
VIDTCON2_HOZVAL(vmode->xres - 1) | |
|
VIDTCON2_LINEVAL_E(vmode->yres - 1) | |
|
VIDTCON2_HOZVAL_E(vmode->xres - 1); |
|
writel(data, regs + sfb->variant.vidtcon + 8); |
|
} |
|
|
|
/** |
|
* s3c_fb_clear_win() - clear hardware window registers. |
|
* @sfb: The base resources for the hardware. |
|
* @win: The window to process. |
|
* |
|
* Reset the specific window registers to a known state. |
|
*/ |
|
static void s3c_fb_clear_win(struct s3c_fb *sfb, int win) |
|
{ |
|
void __iomem *regs = sfb->regs; |
|
u32 reg; |
|
|
|
writel(0, regs + sfb->variant.wincon + (win * 4)); |
|
writel(0, regs + VIDOSD_A(win, sfb->variant)); |
|
writel(0, regs + VIDOSD_B(win, sfb->variant)); |
|
writel(0, regs + VIDOSD_C(win, sfb->variant)); |
|
|
|
if (sfb->variant.has_shadowcon) { |
|
reg = readl(sfb->regs + SHADOWCON); |
|
reg &= ~(SHADOWCON_WINx_PROTECT(win) | |
|
SHADOWCON_CHx_ENABLE(win) | |
|
SHADOWCON_CHx_LOCAL_ENABLE(win)); |
|
writel(reg, sfb->regs + SHADOWCON); |
|
} |
|
} |
|
|
|
static int s3c_fb_probe(struct platform_device *pdev) |
|
{ |
|
const struct platform_device_id *platid; |
|
struct s3c_fb_driverdata *fbdrv; |
|
struct device *dev = &pdev->dev; |
|
struct s3c_fb_platdata *pd; |
|
struct s3c_fb *sfb; |
|
struct resource *res; |
|
int win; |
|
int ret = 0; |
|
u32 reg; |
|
|
|
platid = platform_get_device_id(pdev); |
|
fbdrv = (struct s3c_fb_driverdata *)platid->driver_data; |
|
|
|
if (fbdrv->variant.nr_windows > S3C_FB_MAX_WIN) { |
|
dev_err(dev, "too many windows, cannot attach\n"); |
|
return -EINVAL; |
|
} |
|
|
|
pd = dev_get_platdata(&pdev->dev); |
|
if (!pd) { |
|
dev_err(dev, "no platform data specified\n"); |
|
return -EINVAL; |
|
} |
|
|
|
sfb = devm_kzalloc(dev, sizeof(*sfb), GFP_KERNEL); |
|
if (!sfb) |
|
return -ENOMEM; |
|
|
|
dev_dbg(dev, "allocate new framebuffer %p\n", sfb); |
|
|
|
sfb->dev = dev; |
|
sfb->pdata = pd; |
|
sfb->variant = fbdrv->variant; |
|
|
|
spin_lock_init(&sfb->slock); |
|
|
|
sfb->bus_clk = devm_clk_get(dev, "lcd"); |
|
if (IS_ERR(sfb->bus_clk)) { |
|
dev_err(dev, "failed to get bus clock\n"); |
|
return PTR_ERR(sfb->bus_clk); |
|
} |
|
|
|
clk_prepare_enable(sfb->bus_clk); |
|
|
|
if (!sfb->variant.has_clksel) { |
|
sfb->lcd_clk = devm_clk_get(dev, "sclk_fimd"); |
|
if (IS_ERR(sfb->lcd_clk)) { |
|
dev_err(dev, "failed to get lcd clock\n"); |
|
ret = PTR_ERR(sfb->lcd_clk); |
|
goto err_bus_clk; |
|
} |
|
|
|
clk_prepare_enable(sfb->lcd_clk); |
|
} |
|
|
|
pm_runtime_enable(sfb->dev); |
|
|
|
sfb->regs = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(sfb->regs)) { |
|
ret = PTR_ERR(sfb->regs); |
|
goto err_lcd_clk; |
|
} |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
|
if (!res) { |
|
dev_err(dev, "failed to acquire irq resource\n"); |
|
ret = -ENOENT; |
|
goto err_lcd_clk; |
|
} |
|
sfb->irq_no = res->start; |
|
ret = devm_request_irq(dev, sfb->irq_no, s3c_fb_irq, |
|
0, "s3c_fb", sfb); |
|
if (ret) { |
|
dev_err(dev, "irq request failed\n"); |
|
goto err_lcd_clk; |
|
} |
|
|
|
dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs); |
|
|
|
platform_set_drvdata(pdev, sfb); |
|
pm_runtime_get_sync(sfb->dev); |
|
|
|
/* setup gpio and output polarity controls */ |
|
|
|
pd->setup_gpio(); |
|
|
|
writel(pd->vidcon1, sfb->regs + VIDCON1); |
|
|
|
/* set video clock running at under-run */ |
|
if (sfb->variant.has_fixvclk) { |
|
reg = readl(sfb->regs + VIDCON1); |
|
reg &= ~VIDCON1_VCLK_MASK; |
|
reg |= VIDCON1_VCLK_RUN; |
|
writel(reg, sfb->regs + VIDCON1); |
|
} |
|
|
|
/* zero all windows before we do anything */ |
|
|
|
for (win = 0; win < fbdrv->variant.nr_windows; win++) |
|
s3c_fb_clear_win(sfb, win); |
|
|
|
/* initialise colour key controls */ |
|
for (win = 0; win < (fbdrv->variant.nr_windows - 1); win++) { |
|
void __iomem *regs = sfb->regs + sfb->variant.keycon; |
|
|
|
regs += (win * 8); |
|
writel(0xffffff, regs + WKEYCON0); |
|
writel(0xffffff, regs + WKEYCON1); |
|
} |
|
|
|
s3c_fb_set_rgb_timing(sfb); |
|
|
|
/* we have the register setup, start allocating framebuffers */ |
|
|
|
for (win = 0; win < fbdrv->variant.nr_windows; win++) { |
|
if (!pd->win[win]) |
|
continue; |
|
|
|
ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win], |
|
&sfb->windows[win]); |
|
if (ret < 0) { |
|
dev_err(dev, "failed to create window %d\n", win); |
|
for (; win >= 0; win--) |
|
s3c_fb_release_win(sfb, sfb->windows[win]); |
|
goto err_pm_runtime; |
|
} |
|
} |
|
|
|
platform_set_drvdata(pdev, sfb); |
|
pm_runtime_put_sync(sfb->dev); |
|
|
|
return 0; |
|
|
|
err_pm_runtime: |
|
pm_runtime_put_sync(sfb->dev); |
|
|
|
err_lcd_clk: |
|
pm_runtime_disable(sfb->dev); |
|
|
|
if (!sfb->variant.has_clksel) |
|
clk_disable_unprepare(sfb->lcd_clk); |
|
|
|
err_bus_clk: |
|
clk_disable_unprepare(sfb->bus_clk); |
|
|
|
return ret; |
|
} |
|
|
|
/** |
|
* s3c_fb_remove() - Cleanup on module finalisation |
|
* @pdev: The platform device we are bound to. |
|
* |
|
* Shutdown and then release all the resources that the driver allocated |
|
* on initialisation. |
|
*/ |
|
static int s3c_fb_remove(struct platform_device *pdev) |
|
{ |
|
struct s3c_fb *sfb = platform_get_drvdata(pdev); |
|
int win; |
|
|
|
pm_runtime_get_sync(sfb->dev); |
|
|
|
for (win = 0; win < S3C_FB_MAX_WIN; win++) |
|
if (sfb->windows[win]) |
|
s3c_fb_release_win(sfb, sfb->windows[win]); |
|
|
|
if (!sfb->variant.has_clksel) |
|
clk_disable_unprepare(sfb->lcd_clk); |
|
|
|
clk_disable_unprepare(sfb->bus_clk); |
|
|
|
pm_runtime_put_sync(sfb->dev); |
|
pm_runtime_disable(sfb->dev); |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int s3c_fb_suspend(struct device *dev) |
|
{ |
|
struct s3c_fb *sfb = dev_get_drvdata(dev); |
|
struct s3c_fb_win *win; |
|
int win_no; |
|
|
|
pm_runtime_get_sync(sfb->dev); |
|
|
|
for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) { |
|
win = sfb->windows[win_no]; |
|
if (!win) |
|
continue; |
|
|
|
/* use the blank function to push into power-down */ |
|
s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo); |
|
} |
|
|
|
if (!sfb->variant.has_clksel) |
|
clk_disable_unprepare(sfb->lcd_clk); |
|
|
|
clk_disable_unprepare(sfb->bus_clk); |
|
|
|
pm_runtime_put_sync(sfb->dev); |
|
|
|
return 0; |
|
} |
|
|
|
static int s3c_fb_resume(struct device *dev) |
|
{ |
|
struct s3c_fb *sfb = dev_get_drvdata(dev); |
|
struct s3c_fb_platdata *pd = sfb->pdata; |
|
struct s3c_fb_win *win; |
|
int win_no; |
|
u32 reg; |
|
|
|
pm_runtime_get_sync(sfb->dev); |
|
|
|
clk_prepare_enable(sfb->bus_clk); |
|
|
|
if (!sfb->variant.has_clksel) |
|
clk_prepare_enable(sfb->lcd_clk); |
|
|
|
/* setup gpio and output polarity controls */ |
|
pd->setup_gpio(); |
|
writel(pd->vidcon1, sfb->regs + VIDCON1); |
|
|
|
/* set video clock running at under-run */ |
|
if (sfb->variant.has_fixvclk) { |
|
reg = readl(sfb->regs + VIDCON1); |
|
reg &= ~VIDCON1_VCLK_MASK; |
|
reg |= VIDCON1_VCLK_RUN; |
|
writel(reg, sfb->regs + VIDCON1); |
|
} |
|
|
|
/* zero all windows before we do anything */ |
|
for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++) |
|
s3c_fb_clear_win(sfb, win_no); |
|
|
|
for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) { |
|
void __iomem *regs = sfb->regs + sfb->variant.keycon; |
|
win = sfb->windows[win_no]; |
|
if (!win) |
|
continue; |
|
|
|
shadow_protect_win(win, 1); |
|
regs += (win_no * 8); |
|
writel(0xffffff, regs + WKEYCON0); |
|
writel(0xffffff, regs + WKEYCON1); |
|
shadow_protect_win(win, 0); |
|
} |
|
|
|
s3c_fb_set_rgb_timing(sfb); |
|
|
|
/* restore framebuffers */ |
|
for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) { |
|
win = sfb->windows[win_no]; |
|
if (!win) |
|
continue; |
|
|
|
dev_dbg(dev, "resuming window %d\n", win_no); |
|
s3c_fb_set_par(win->fbinfo); |
|
} |
|
|
|
pm_runtime_put_sync(sfb->dev); |
|
|
|
return 0; |
|
} |
|
#endif |
|
|
|
#ifdef CONFIG_PM |
|
static int s3c_fb_runtime_suspend(struct device *dev) |
|
{ |
|
struct s3c_fb *sfb = dev_get_drvdata(dev); |
|
|
|
if (!sfb->variant.has_clksel) |
|
clk_disable_unprepare(sfb->lcd_clk); |
|
|
|
clk_disable_unprepare(sfb->bus_clk); |
|
|
|
return 0; |
|
} |
|
|
|
static int s3c_fb_runtime_resume(struct device *dev) |
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{ |
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struct s3c_fb *sfb = dev_get_drvdata(dev); |
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struct s3c_fb_platdata *pd = sfb->pdata; |
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|
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clk_prepare_enable(sfb->bus_clk); |
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|
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if (!sfb->variant.has_clksel) |
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clk_prepare_enable(sfb->lcd_clk); |
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|
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/* setup gpio and output polarity controls */ |
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pd->setup_gpio(); |
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writel(pd->vidcon1, sfb->regs + VIDCON1); |
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|
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return 0; |
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} |
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#endif |
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|
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#define VALID_BPP124 (VALID_BPP(1) | VALID_BPP(2) | VALID_BPP(4)) |
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#define VALID_BPP1248 (VALID_BPP124 | VALID_BPP(8)) |
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|
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static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] = { |
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[0] = { |
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.has_osd_c = 1, |
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.osd_size_off = 0x8, |
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.palette_sz = 256, |
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.valid_bpp = (VALID_BPP1248 | VALID_BPP(16) | |
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VALID_BPP(18) | VALID_BPP(24)), |
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}, |
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[1] = { |
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.has_osd_c = 1, |
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.has_osd_d = 1, |
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.osd_size_off = 0xc, |
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.has_osd_alpha = 1, |
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.palette_sz = 256, |
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.valid_bpp = (VALID_BPP1248 | VALID_BPP(16) | |
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VALID_BPP(18) | VALID_BPP(19) | |
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VALID_BPP(24) | VALID_BPP(25) | |
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VALID_BPP(28)), |
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}, |
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[2] = { |
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.has_osd_c = 1, |
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.has_osd_d = 1, |
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.osd_size_off = 0xc, |
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.has_osd_alpha = 1, |
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.palette_sz = 16, |
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.palette_16bpp = 1, |
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.valid_bpp = (VALID_BPP1248 | VALID_BPP(16) | |
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VALID_BPP(18) | VALID_BPP(19) | |
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VALID_BPP(24) | VALID_BPP(25) | |
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VALID_BPP(28)), |
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}, |
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[3] = { |
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.has_osd_c = 1, |
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.has_osd_alpha = 1, |
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.palette_sz = 16, |
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.palette_16bpp = 1, |
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.valid_bpp = (VALID_BPP124 | VALID_BPP(16) | |
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VALID_BPP(18) | VALID_BPP(19) | |
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VALID_BPP(24) | VALID_BPP(25) | |
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VALID_BPP(28)), |
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}, |
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[4] = { |
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.has_osd_c = 1, |
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.has_osd_alpha = 1, |
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.palette_sz = 4, |
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.palette_16bpp = 1, |
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.valid_bpp = (VALID_BPP(1) | VALID_BPP(2) | |
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VALID_BPP(16) | VALID_BPP(18) | |
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VALID_BPP(19) | VALID_BPP(24) | |
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VALID_BPP(25) | VALID_BPP(28)), |
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}, |
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}; |
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|
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static struct s3c_fb_driverdata s3c_fb_data_64xx = { |
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.variant = { |
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.nr_windows = 5, |
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.vidtcon = VIDTCON0, |
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.wincon = WINCON(0), |
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.winmap = WINxMAP(0), |
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.keycon = WKEYCON, |
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.osd = VIDOSD_BASE, |
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.osd_stride = 16, |
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.buf_start = VIDW_BUF_START(0), |
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.buf_size = VIDW_BUF_SIZE(0), |
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.buf_end = VIDW_BUF_END(0), |
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|
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.palette = { |
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[0] = 0x400, |
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[1] = 0x800, |
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[2] = 0x300, |
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[3] = 0x320, |
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[4] = 0x340, |
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}, |
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|
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.has_prtcon = 1, |
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.has_clksel = 1, |
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}, |
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.win[0] = &s3c_fb_data_64xx_wins[0], |
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.win[1] = &s3c_fb_data_64xx_wins[1], |
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.win[2] = &s3c_fb_data_64xx_wins[2], |
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.win[3] = &s3c_fb_data_64xx_wins[3], |
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.win[4] = &s3c_fb_data_64xx_wins[4], |
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}; |
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|
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/* S3C2443/S3C2416 style hardware */ |
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static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = { |
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.variant = { |
|
.nr_windows = 2, |
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.is_2443 = 1, |
|
|
|
.vidtcon = 0x08, |
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.wincon = 0x14, |
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.winmap = 0xd0, |
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.keycon = 0xb0, |
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.osd = 0x28, |
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.osd_stride = 12, |
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.buf_start = 0x64, |
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.buf_size = 0x94, |
|
.buf_end = 0x7c, |
|
|
|
.palette = { |
|
[0] = 0x400, |
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[1] = 0x800, |
|
}, |
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.has_clksel = 1, |
|
}, |
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.win[0] = &(struct s3c_fb_win_variant) { |
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.palette_sz = 256, |
|
.valid_bpp = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24), |
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}, |
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.win[1] = &(struct s3c_fb_win_variant) { |
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.has_osd_c = 1, |
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.has_osd_alpha = 1, |
|
.palette_sz = 256, |
|
.valid_bpp = (VALID_BPP1248 | VALID_BPP(16) | |
|
VALID_BPP(18) | VALID_BPP(19) | |
|
VALID_BPP(24) | VALID_BPP(25) | |
|
VALID_BPP(28)), |
|
}, |
|
}; |
|
|
|
static const struct platform_device_id s3c_fb_driver_ids[] = { |
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{ |
|
.name = "s3c-fb", |
|
.driver_data = (unsigned long)&s3c_fb_data_64xx, |
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}, { |
|
.name = "s3c2443-fb", |
|
.driver_data = (unsigned long)&s3c_fb_data_s3c2443, |
|
}, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids); |
|
|
|
static const struct dev_pm_ops s3cfb_pm_ops = { |
|
SET_SYSTEM_SLEEP_PM_OPS(s3c_fb_suspend, s3c_fb_resume) |
|
SET_RUNTIME_PM_OPS(s3c_fb_runtime_suspend, s3c_fb_runtime_resume, |
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NULL) |
|
}; |
|
|
|
static struct platform_driver s3c_fb_driver = { |
|
.probe = s3c_fb_probe, |
|
.remove = s3c_fb_remove, |
|
.id_table = s3c_fb_driver_ids, |
|
.driver = { |
|
.name = "s3c-fb", |
|
.pm = &s3cfb_pm_ops, |
|
}, |
|
}; |
|
|
|
module_platform_driver(s3c_fb_driver); |
|
|
|
MODULE_AUTHOR("Ben Dooks <[email protected]>"); |
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MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver"); |
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MODULE_LICENSE("GPL"); |
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MODULE_ALIAS("platform:s3c-fb");
|
|
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