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710 lines
17 KiB
710 lines
17 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* |
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* Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450 |
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* |
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* (c) 1998-2002 Petr Vandrovec <[email protected]> |
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* |
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*/ |
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#ifndef __MATROXFB_H__ |
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#define __MATROXFB_H__ |
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/* general, but fairly heavy, debugging */ |
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#undef MATROXFB_DEBUG |
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/* heavy debugging: */ |
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/* -- logs putc[s], so every time a char is displayed, it's logged */ |
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#undef MATROXFB_DEBUG_HEAVY |
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/* This one _could_ cause infinite loops */ |
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/* It _does_ cause lots and lots of messages during idle loops */ |
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#undef MATROXFB_DEBUG_LOOP |
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/* Debug register calls, too? */ |
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#undef MATROXFB_DEBUG_REG |
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/* Guard accelerator accesses with spin_lock_irqsave... */ |
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#undef MATROXFB_USE_SPINLOCKS |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/errno.h> |
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#include <linux/string.h> |
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#include <linux/mm.h> |
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#include <linux/slab.h> |
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#include <linux/delay.h> |
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#include <linux/fb.h> |
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#include <linux/console.h> |
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#include <linux/selection.h> |
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#include <linux/ioport.h> |
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#include <linux/init.h> |
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#include <linux/timer.h> |
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#include <linux/pci.h> |
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#include <linux/spinlock.h> |
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#include <linux/kd.h> |
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#include <asm/io.h> |
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#include <asm/unaligned.h> |
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#if defined(CONFIG_PPC_PMAC) |
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#include <asm/prom.h> |
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#include "../macmodes.h" |
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#endif |
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#ifdef MATROXFB_DEBUG |
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#define DEBUG |
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#define DBG(x) printk(KERN_DEBUG "matroxfb: %s\n", (x)); |
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#ifdef MATROXFB_DEBUG_HEAVY |
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#define DBG_HEAVY(x) DBG(x) |
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#else /* MATROXFB_DEBUG_HEAVY */ |
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#define DBG_HEAVY(x) /* DBG_HEAVY */ |
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#endif /* MATROXFB_DEBUG_HEAVY */ |
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#ifdef MATROXFB_DEBUG_LOOP |
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#define DBG_LOOP(x) DBG(x) |
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#else /* MATROXFB_DEBUG_LOOP */ |
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#define DBG_LOOP(x) /* DBG_LOOP */ |
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#endif /* MATROXFB_DEBUG_LOOP */ |
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#ifdef MATROXFB_DEBUG_REG |
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#define DBG_REG(x) DBG(x) |
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#else /* MATROXFB_DEBUG_REG */ |
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#define DBG_REG(x) /* DBG_REG */ |
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#endif /* MATROXFB_DEBUG_REG */ |
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#else /* MATROXFB_DEBUG */ |
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#define DBG(x) /* DBG */ |
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#define DBG_HEAVY(x) /* DBG_HEAVY */ |
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#define DBG_REG(x) /* DBG_REG */ |
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#define DBG_LOOP(x) /* DBG_LOOP */ |
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#endif /* MATROXFB_DEBUG */ |
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#ifdef DEBUG |
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#define dprintk(X...) printk(X) |
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#else |
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#define dprintk(X...) no_printk(X) |
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#endif |
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#ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF |
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#define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 0x110A |
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#endif |
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#ifndef PCI_SS_VENDOR_ID_MATROX |
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#define PCI_SS_VENDOR_ID_MATROX PCI_VENDOR_ID_MATROX |
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#endif |
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#ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP |
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#define PCI_SS_ID_MATROX_GENERIC 0xFF00 |
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#define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 0xFF01 |
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#define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 0xFF02 |
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#define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03 |
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#define PCI_SS_ID_MATROX_MARVEL_G200_AGP 0xFF04 |
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#define PCI_SS_ID_MATROX_MGA_G100_PCI 0xFF05 |
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#define PCI_SS_ID_MATROX_MGA_G100_AGP 0x1001 |
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#define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP 0x2179 |
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#define PCI_SS_ID_SIEMENS_MGA_G100_AGP 0x001E /* 30 */ |
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#define PCI_SS_ID_SIEMENS_MGA_G200_AGP 0x0032 /* 50 */ |
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#endif |
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#define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRECTCOLOR |
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#define MX_VISUAL_DIRECTCOLOR FB_VISUAL_TRUECOLOR |
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#define MX_VISUAL_PSEUDOCOLOR FB_VISUAL_PSEUDOCOLOR |
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#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) |
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/* G-series and Mystique have (almost) same DAC */ |
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#undef NEED_DAC1064 |
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#if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G) |
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#define NEED_DAC1064 1 |
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#endif |
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typedef struct { |
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void __iomem* vaddr; |
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} vaddr_t; |
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static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) { |
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return readb(va.vaddr + offs); |
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} |
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static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) { |
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writeb(value, va.vaddr + offs); |
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} |
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static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) { |
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writew(value, va.vaddr + offs); |
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} |
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static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) { |
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return readl(va.vaddr + offs); |
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} |
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static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) { |
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writel(value, va.vaddr + offs); |
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} |
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static inline void mga_memcpy_toio(vaddr_t va, const void* src, int len) { |
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#if defined(__alpha__) || defined(__i386__) || defined(__x86_64__) |
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/* |
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* iowrite32_rep works for us if: |
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* (1) Copies data as 32bit quantities, not byte after byte, |
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* (2) Performs LE ordered stores, and |
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* (3) It copes with unaligned source (destination is guaranteed to be page |
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* aligned and length is guaranteed to be multiple of 4). |
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*/ |
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iowrite32_rep(va.vaddr, src, len >> 2); |
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#else |
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u_int32_t __iomem* addr = va.vaddr; |
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if ((unsigned long)src & 3) { |
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while (len >= 4) { |
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fb_writel(get_unaligned((u32 *)src), addr); |
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addr++; |
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len -= 4; |
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src += 4; |
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} |
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} else { |
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while (len >= 4) { |
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fb_writel(*(u32 *)src, addr); |
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addr++; |
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len -= 4; |
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src += 4; |
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} |
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} |
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#endif |
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} |
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static inline void vaddr_add(vaddr_t* va, unsigned long offs) { |
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va->vaddr += offs; |
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} |
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static inline void __iomem* vaddr_va(vaddr_t va) { |
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return va.vaddr; |
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} |
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struct my_timming { |
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unsigned int pixclock; |
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int mnp; |
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unsigned int crtc; |
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unsigned int HDisplay; |
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unsigned int HSyncStart; |
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unsigned int HSyncEnd; |
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unsigned int HTotal; |
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unsigned int VDisplay; |
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unsigned int VSyncStart; |
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unsigned int VSyncEnd; |
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unsigned int VTotal; |
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unsigned int sync; |
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int dblscan; |
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int interlaced; |
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unsigned int delay; /* CRTC delay */ |
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}; |
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enum { M_SYSTEM_PLL, M_PIXEL_PLL_A, M_PIXEL_PLL_B, M_PIXEL_PLL_C, M_VIDEO_PLL }; |
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struct matrox_pll_cache { |
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unsigned int valid; |
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struct { |
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unsigned int mnp_key; |
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unsigned int mnp_value; |
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} data[4]; |
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}; |
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struct matrox_pll_limits { |
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unsigned int vcomin; |
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unsigned int vcomax; |
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}; |
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struct matrox_pll_features { |
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unsigned int vco_freq_min; |
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unsigned int ref_freq; |
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unsigned int feed_div_min; |
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unsigned int feed_div_max; |
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unsigned int in_div_min; |
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unsigned int in_div_max; |
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unsigned int post_shift_max; |
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}; |
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struct matroxfb_par |
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{ |
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unsigned int final_bppShift; |
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unsigned int cmap_len; |
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struct { |
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unsigned int bytes; |
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unsigned int pixels; |
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unsigned int chunks; |
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} ydstorg; |
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}; |
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struct matrox_fb_info; |
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struct matrox_DAC1064_features { |
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u_int8_t xvrefctrl; |
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u_int8_t xmiscctrl; |
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}; |
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/* current hardware status */ |
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struct mavenregs { |
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u_int8_t regs[256]; |
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int mode; |
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int vlines; |
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int xtal; |
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int fv; |
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u_int16_t htotal; |
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u_int16_t hcorr; |
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}; |
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struct matrox_crtc2 { |
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u_int32_t ctl; |
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}; |
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struct matrox_hw_state { |
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u_int32_t MXoptionReg; |
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unsigned char DACclk[6]; |
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unsigned char DACreg[80]; |
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unsigned char MiscOutReg; |
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unsigned char DACpal[768]; |
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unsigned char CRTC[25]; |
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unsigned char CRTCEXT[9]; |
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unsigned char SEQ[5]; |
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/* unused for MGA mode, but who knows... */ |
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unsigned char GCTL[9]; |
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/* unused for MGA mode, but who knows... */ |
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unsigned char ATTR[21]; |
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/* TVOut only */ |
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struct mavenregs maven; |
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struct matrox_crtc2 crtc2; |
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}; |
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struct matrox_accel_data { |
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#ifdef CONFIG_FB_MATROX_MILLENIUM |
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unsigned char ramdac_rev; |
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#endif |
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u_int32_t m_dwg_rect; |
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u_int32_t m_opmode; |
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u_int32_t m_access; |
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u_int32_t m_pitch; |
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}; |
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struct v4l2_queryctrl; |
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struct v4l2_control; |
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struct matrox_altout { |
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const char *name; |
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int (*compute)(void* altout_dev, struct my_timming* input); |
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int (*program)(void* altout_dev); |
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int (*start)(void* altout_dev); |
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int (*verifymode)(void* altout_dev, u_int32_t mode); |
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int (*getqueryctrl)(void* altout_dev, |
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struct v4l2_queryctrl* ctrl); |
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int (*getctrl)(void* altout_dev, |
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struct v4l2_control* ctrl); |
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int (*setctrl)(void* altout_dev, |
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struct v4l2_control* ctrl); |
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}; |
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#define MATROXFB_SRC_NONE 0 |
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#define MATROXFB_SRC_CRTC1 1 |
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#define MATROXFB_SRC_CRTC2 2 |
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enum mga_chip { MGA_2064, MGA_2164, MGA_1064, MGA_1164, MGA_G100, MGA_G200, MGA_G400, MGA_G450, MGA_G550 }; |
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struct matrox_bios { |
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unsigned int bios_valid : 1; |
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unsigned int pins_len; |
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unsigned char pins[128]; |
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struct { |
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unsigned char vMaj, vMin, vRev; |
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} version; |
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struct { |
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unsigned char state, tvout; |
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} output; |
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}; |
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struct matrox_switch; |
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struct matroxfb_driver; |
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struct matroxfb_dh_fb_info; |
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struct matrox_vsync { |
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wait_queue_head_t wait; |
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unsigned int cnt; |
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}; |
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struct matrox_fb_info { |
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struct fb_info fbcon; |
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struct list_head next_fb; |
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int dead; |
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int initialized; |
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unsigned int usecount; |
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unsigned int userusecount; |
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unsigned long irq_flags; |
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struct matroxfb_par curr; |
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struct matrox_hw_state hw; |
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struct matrox_accel_data accel; |
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struct pci_dev* pcidev; |
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struct { |
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struct matrox_vsync vsync; |
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unsigned int pixclock; |
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int mnp; |
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int panpos; |
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} crtc1; |
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struct { |
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struct matrox_vsync vsync; |
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unsigned int pixclock; |
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int mnp; |
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struct matroxfb_dh_fb_info* info; |
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struct rw_semaphore lock; |
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} crtc2; |
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struct { |
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struct rw_semaphore lock; |
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struct { |
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int brightness, contrast, saturation, hue, gamma; |
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int testout, deflicker; |
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} tvo_params; |
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} altout; |
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#define MATROXFB_MAX_OUTPUTS 3 |
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struct { |
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unsigned int src; |
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struct matrox_altout* output; |
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void* data; |
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unsigned int mode; |
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unsigned int default_src; |
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} outputs[MATROXFB_MAX_OUTPUTS]; |
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#define MATROXFB_MAX_FB_DRIVERS 5 |
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struct matroxfb_driver* (drivers[MATROXFB_MAX_FB_DRIVERS]); |
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void* (drivers_data[MATROXFB_MAX_FB_DRIVERS]); |
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unsigned int drivers_count; |
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struct { |
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unsigned long base; /* physical */ |
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vaddr_t vbase; /* CPU view */ |
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unsigned int len; |
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unsigned int len_usable; |
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unsigned int len_maximum; |
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} video; |
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struct { |
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unsigned long base; /* physical */ |
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vaddr_t vbase; /* CPU view */ |
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unsigned int len; |
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} mmio; |
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unsigned int max_pixel_clock; |
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unsigned int max_pixel_clock_panellink; |
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struct matrox_switch* hw_switch; |
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struct { |
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struct matrox_pll_features pll; |
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struct matrox_DAC1064_features DAC1064; |
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} features; |
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struct { |
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spinlock_t DAC; |
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spinlock_t accel; |
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} lock; |
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enum mga_chip chip; |
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int interleave; |
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int millenium; |
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int milleniumII; |
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struct { |
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int cfb4; |
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const int* vxres; |
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int cross4MB; |
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int text; |
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int plnwt; |
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int srcorg; |
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} capable; |
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int wc_cookie; |
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struct { |
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int precise_width; |
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int mga_24bpp_fix; |
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int novga; |
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int nobios; |
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int nopciretry; |
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int noinit; |
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int sgram; |
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int support32MB; |
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int accelerator; |
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int text_type_aux; |
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int video64bits; |
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int crtc2; |
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int maven_capable; |
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unsigned int vgastep; |
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unsigned int textmode; |
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unsigned int textstep; |
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unsigned int textvram; /* character cells */ |
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unsigned int ydstorg; /* offset in bytes from video start to usable memory */ |
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/* 0 except for 6MB Millenium */ |
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int memtype; |
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int g450dac; |
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int dfp_type; |
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int panellink; /* G400 DFP possible (not G450/G550) */ |
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int dualhead; |
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unsigned int fbResource; |
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} devflags; |
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struct fb_ops fbops; |
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struct matrox_bios bios; |
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struct { |
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struct matrox_pll_limits pixel; |
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struct matrox_pll_limits system; |
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struct matrox_pll_limits video; |
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} limits; |
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struct { |
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struct matrox_pll_cache pixel; |
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struct matrox_pll_cache system; |
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struct matrox_pll_cache video; |
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} cache; |
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struct { |
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struct { |
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unsigned int video; |
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unsigned int system; |
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} pll; |
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struct { |
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u_int32_t opt; |
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u_int32_t opt2; |
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u_int32_t opt3; |
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u_int32_t mctlwtst; |
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u_int32_t mctlwtst_core; |
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u_int32_t memmisc; |
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u_int32_t memrdbk; |
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u_int32_t maccess; |
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} reg; |
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struct { |
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unsigned int ddr:1, |
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emrswen:1, |
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dll:1; |
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} memory; |
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} values; |
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u_int32_t cmap[16]; |
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}; |
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#define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon) |
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struct matrox_switch { |
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int (*preinit)(struct matrox_fb_info *minfo); |
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void (*reset)(struct matrox_fb_info *minfo); |
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int (*init)(struct matrox_fb_info *minfo, struct my_timming*); |
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void (*restore)(struct matrox_fb_info *minfo); |
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}; |
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struct matroxfb_driver { |
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struct list_head node; |
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char* name; |
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void* (*probe)(struct matrox_fb_info* info); |
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void (*remove)(struct matrox_fb_info* info, void* data); |
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}; |
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int matroxfb_register_driver(struct matroxfb_driver* drv); |
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void matroxfb_unregister_driver(struct matroxfb_driver* drv); |
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#define PCI_OPTION_REG 0x40 |
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#define PCI_OPTION_ENABLE_ROM 0x40000000 |
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#define PCI_MGA_INDEX 0x44 |
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#define PCI_MGA_DATA 0x48 |
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#define PCI_OPTION2_REG 0x50 |
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#define PCI_OPTION3_REG 0x54 |
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#define PCI_MEMMISC_REG 0x58 |
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#define M_DWGCTL 0x1C00 |
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#define M_MACCESS 0x1C04 |
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#define M_CTLWTST 0x1C08 |
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#define M_PLNWT 0x1C1C |
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#define M_BCOL 0x1C20 |
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#define M_FCOL 0x1C24 |
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#define M_SGN 0x1C58 |
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#define M_LEN 0x1C5C |
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#define M_AR0 0x1C60 |
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#define M_AR1 0x1C64 |
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#define M_AR2 0x1C68 |
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#define M_AR3 0x1C6C |
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#define M_AR4 0x1C70 |
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#define M_AR5 0x1C74 |
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#define M_AR6 0x1C78 |
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#define M_CXBNDRY 0x1C80 |
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#define M_FXBNDRY 0x1C84 |
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#define M_YDSTLEN 0x1C88 |
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#define M_PITCH 0x1C8C |
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#define M_YDST 0x1C90 |
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#define M_YDSTORG 0x1C94 |
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#define M_YTOP 0x1C98 |
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#define M_YBOT 0x1C9C |
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/* mystique only */ |
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#define M_CACHEFLUSH 0x1FFF |
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#define M_EXEC 0x0100 |
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#define M_DWG_TRAP 0x04 |
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#define M_DWG_BITBLT 0x08 |
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#define M_DWG_ILOAD 0x09 |
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#define M_DWG_LINEAR 0x0080 |
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#define M_DWG_SOLID 0x0800 |
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#define M_DWG_ARZERO 0x1000 |
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#define M_DWG_SGNZERO 0x2000 |
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#define M_DWG_SHIFTZERO 0x4000 |
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#define M_DWG_REPLACE 0x000C0000 |
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#define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40) |
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#define M_DWG_XOR 0x00060010 |
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#define M_DWG_BFCOL 0x04000000 |
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#define M_DWG_BMONOWF 0x08000000 |
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#define M_DWG_TRANSC 0x40000000 |
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#define M_FIFOSTATUS 0x1E10 |
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#define M_STATUS 0x1E14 |
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#define M_ICLEAR 0x1E18 |
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#define M_IEN 0x1E1C |
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#define M_VCOUNT 0x1E20 |
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#define M_RESET 0x1E40 |
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#define M_MEMRDBK 0x1E44 |
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#define M_AGP2PLL 0x1E4C |
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#define M_OPMODE 0x1E54 |
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#define M_OPMODE_DMA_GEN_WRITE 0x00 |
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#define M_OPMODE_DMA_BLIT 0x04 |
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#define M_OPMODE_DMA_VECTOR_WRITE 0x08 |
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#define M_OPMODE_DMA_LE 0x0000 /* little endian - no transformation */ |
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#define M_OPMODE_DMA_BE_8BPP 0x0000 |
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#define M_OPMODE_DMA_BE_16BPP 0x0100 |
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#define M_OPMODE_DMA_BE_32BPP 0x0200 |
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#define M_OPMODE_DIR_LE 0x000000 /* little endian - no transformation */ |
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#define M_OPMODE_DIR_BE_8BPP 0x000000 |
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#define M_OPMODE_DIR_BE_16BPP 0x010000 |
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#define M_OPMODE_DIR_BE_32BPP 0x020000 |
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#define M_ATTR_INDEX 0x1FC0 |
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#define M_ATTR_DATA 0x1FC1 |
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#define M_MISC_REG 0x1FC2 |
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#define M_3C2_RD 0x1FC2 |
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#define M_SEQ_INDEX 0x1FC4 |
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#define M_SEQ_DATA 0x1FC5 |
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#define M_SEQ1 0x01 |
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#define M_SEQ1_SCROFF 0x20 |
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#define M_MISC_REG_READ 0x1FCC |
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#define M_GRAPHICS_INDEX 0x1FCE |
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#define M_GRAPHICS_DATA 0x1FCF |
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#define M_CRTC_INDEX 0x1FD4 |
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#define M_ATTR_RESET 0x1FDA |
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#define M_3DA_WR 0x1FDA |
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#define M_INSTS1 0x1FDA |
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#define M_EXTVGA_INDEX 0x1FDE |
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#define M_EXTVGA_DATA 0x1FDF |
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/* G200 only */ |
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#define M_SRCORG 0x2CB4 |
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#define M_DSTORG 0x2CB8 |
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#define M_RAMDAC_BASE 0x3C00 |
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/* fortunately, same on TVP3026 and MGA1064 */ |
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#define M_DAC_REG (M_RAMDAC_BASE+0) |
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#define M_DAC_VAL (M_RAMDAC_BASE+1) |
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#define M_PALETTE_MASK (M_RAMDAC_BASE+2) |
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#define M_X_INDEX 0x00 |
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#define M_X_DATAREG 0x0A |
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#define DAC_XGENIOCTRL 0x2A |
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#define DAC_XGENIODATA 0x2B |
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#define M_C2CTL 0x3C10 |
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#define MX_OPTION_BSWAP 0x00000000 |
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#ifdef __LITTLE_ENDIAN |
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#define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) |
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#define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) |
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#define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) |
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#define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) |
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#define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) |
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#else |
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#ifdef __BIG_ENDIAN |
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#define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) /* TODO */ |
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#define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) |
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#define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT) |
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#define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) /* TODO, ?32 */ |
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#define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT) |
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#else |
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#error "Byte ordering have to be defined. Cannot continue." |
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#endif |
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#endif |
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#define mga_inb(addr) mga_readb(minfo->mmio.vbase, (addr)) |
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#define mga_inl(addr) mga_readl(minfo->mmio.vbase, (addr)) |
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#define mga_outb(addr,val) mga_writeb(minfo->mmio.vbase, (addr), (val)) |
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#define mga_outw(addr,val) mga_writew(minfo->mmio.vbase, (addr), (val)) |
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#define mga_outl(addr,val) mga_writel(minfo->mmio.vbase, (addr), (val)) |
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#define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1)) |
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#define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port)) |
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#define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n)) |
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#define WaitTillIdle() do { mga_inl(M_STATUS); do {} while (mga_inl(M_STATUS) & 0x10000); } while (0) |
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/* code speedup */ |
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#ifdef CONFIG_FB_MATROX_MILLENIUM |
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#define isInterleave(x) (x->interleave) |
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#define isMillenium(x) (x->millenium) |
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#define isMilleniumII(x) (x->milleniumII) |
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#else |
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#define isInterleave(x) (0) |
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#define isMillenium(x) (0) |
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#define isMilleniumII(x) (0) |
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#endif |
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#define matroxfb_DAC_lock() spin_lock(&minfo->lock.DAC) |
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#define matroxfb_DAC_unlock() spin_unlock(&minfo->lock.DAC) |
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#define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&minfo->lock.DAC, flags) |
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#define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&minfo->lock.DAC, flags) |
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extern void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg, |
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int val); |
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extern int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg); |
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extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt); |
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extern int matroxfb_wait_for_sync(struct matrox_fb_info *minfo, u_int32_t crtc); |
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extern int matroxfb_enable_irq(struct matrox_fb_info *minfo, int reenable); |
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#ifdef MATROXFB_USE_SPINLOCKS |
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#define CRITBEGIN spin_lock_irqsave(&minfo->lock.accel, critflags); |
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#define CRITEND spin_unlock_irqrestore(&minfo->lock.accel, critflags); |
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#define CRITFLAGS unsigned long critflags; |
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#else |
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#define CRITBEGIN |
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#define CRITEND |
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#define CRITFLAGS |
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#endif |
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#endif /* __MATROXFB_H__ */
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