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170 lines
4.5 KiB
170 lines
4.5 KiB
/* |
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* linux/drivers/video/kyro/STG4000VTG.c |
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* |
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* Copyright (C) 2002 STMicroelectronics |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file COPYING in the main directory of this archive |
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* for more details. |
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*/ |
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#include <linux/types.h> |
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#include <video/kyro.h> |
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#include "STG4000Reg.h" |
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#include "STG4000Interface.h" |
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void DisableVGA(volatile STG4000REG __iomem *pSTGReg) |
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{ |
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u32 tmp; |
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volatile u32 count = 0, i; |
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/* Reset the VGA registers */ |
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tmp = STG_READ_REG(SoftwareReset); |
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CLEAR_BIT(8); |
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STG_WRITE_REG(SoftwareReset, tmp); |
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/* Just for Delay */ |
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for (i = 0; i < 1000; i++) { |
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count++; |
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} |
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/* Pull-out the VGA registers from reset */ |
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tmp = STG_READ_REG(SoftwareReset); |
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tmp |= SET_BIT(8); |
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STG_WRITE_REG(SoftwareReset, tmp); |
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} |
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void StopVTG(volatile STG4000REG __iomem *pSTGReg) |
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{ |
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u32 tmp = 0; |
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/* Stop Ver and Hor Sync Generator */ |
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tmp = (STG_READ_REG(DACSyncCtrl)) | SET_BIT(0) | SET_BIT(2); |
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CLEAR_BIT(31); |
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STG_WRITE_REG(DACSyncCtrl, tmp); |
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} |
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void StartVTG(volatile STG4000REG __iomem *pSTGReg) |
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{ |
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u32 tmp = 0; |
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/* Start Ver and Hor Sync Generator */ |
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tmp = ((STG_READ_REG(DACSyncCtrl)) | SET_BIT(31)); |
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CLEAR_BIT(0); |
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CLEAR_BIT(2); |
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STG_WRITE_REG(DACSyncCtrl, tmp); |
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} |
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void SetupVTG(volatile STG4000REG __iomem *pSTGReg, |
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const struct kyrofb_info * pTiming) |
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{ |
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u32 tmp = 0; |
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u32 margins = 0; |
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u32 ulBorder; |
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u32 xRes = pTiming->XRES; |
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u32 yRes = pTiming->YRES; |
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/* Horizontal */ |
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u32 HAddrTime, HRightBorder, HLeftBorder; |
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u32 HBackPorcStrt, HFrontPorchStrt, HTotal, |
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HLeftBorderStrt, HRightBorderStrt, HDisplayStrt; |
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/* Vertical */ |
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u32 VDisplayStrt, VBottomBorder, VTopBorder; |
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u32 VBackPorchStrt, VTotal, VTopBorderStrt, |
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VFrontPorchStrt, VBottomBorderStrt, VAddrTime; |
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/* Need to calculate the right border */ |
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if ((xRes == 640) && (yRes == 480)) { |
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if ((pTiming->VFREQ == 60) || (pTiming->VFREQ == 72)) { |
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margins = 8; |
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} |
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} |
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/* Work out the Border */ |
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ulBorder = |
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(pTiming->HTot - |
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(pTiming->HST + (pTiming->HBP - margins) + xRes + |
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(pTiming->HFP - margins))) >> 1; |
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/* Border the same for Vertical and Horizontal */ |
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VBottomBorder = HLeftBorder = VTopBorder = HRightBorder = ulBorder; |
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/************ Get Timing values for Horizontal ******************/ |
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HAddrTime = xRes; |
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HBackPorcStrt = pTiming->HST; |
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HTotal = pTiming->HTot; |
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HDisplayStrt = |
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pTiming->HST + (pTiming->HBP - margins) + HLeftBorder; |
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HLeftBorderStrt = HDisplayStrt - HLeftBorder; |
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HFrontPorchStrt = |
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pTiming->HST + (pTiming->HBP - margins) + HLeftBorder + |
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HAddrTime + HRightBorder; |
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HRightBorderStrt = HFrontPorchStrt - HRightBorder; |
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/************ Get Timing values for Vertical ******************/ |
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VAddrTime = yRes; |
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VBackPorchStrt = pTiming->VST; |
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VTotal = pTiming->VTot; |
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VDisplayStrt = |
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pTiming->VST + (pTiming->VBP - margins) + VTopBorder; |
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VTopBorderStrt = VDisplayStrt - VTopBorder; |
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VFrontPorchStrt = |
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pTiming->VST + (pTiming->VBP - margins) + VTopBorder + |
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VAddrTime + VBottomBorder; |
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VBottomBorderStrt = VFrontPorchStrt - VBottomBorder; |
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/* Set Hor Timing 1, 2, 3 */ |
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tmp = STG_READ_REG(DACHorTim1); |
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CLEAR_BITS_FRM_TO(0, 11); |
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CLEAR_BITS_FRM_TO(16, 27); |
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tmp |= (HTotal) | (HBackPorcStrt << 16); |
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STG_WRITE_REG(DACHorTim1, tmp); |
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tmp = STG_READ_REG(DACHorTim2); |
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CLEAR_BITS_FRM_TO(0, 11); |
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CLEAR_BITS_FRM_TO(16, 27); |
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tmp |= (HDisplayStrt << 16) | HLeftBorderStrt; |
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STG_WRITE_REG(DACHorTim2, tmp); |
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tmp = STG_READ_REG(DACHorTim3); |
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CLEAR_BITS_FRM_TO(0, 11); |
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CLEAR_BITS_FRM_TO(16, 27); |
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tmp |= (HFrontPorchStrt << 16) | HRightBorderStrt; |
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STG_WRITE_REG(DACHorTim3, tmp); |
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/* Set Ver Timing 1, 2, 3 */ |
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tmp = STG_READ_REG(DACVerTim1); |
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CLEAR_BITS_FRM_TO(0, 11); |
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CLEAR_BITS_FRM_TO(16, 27); |
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tmp |= (VBackPorchStrt << 16) | (VTotal); |
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STG_WRITE_REG(DACVerTim1, tmp); |
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tmp = STG_READ_REG(DACVerTim2); |
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CLEAR_BITS_FRM_TO(0, 11); |
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CLEAR_BITS_FRM_TO(16, 27); |
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tmp |= (VDisplayStrt << 16) | VTopBorderStrt; |
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STG_WRITE_REG(DACVerTim2, tmp); |
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tmp = STG_READ_REG(DACVerTim3); |
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CLEAR_BITS_FRM_TO(0, 11); |
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CLEAR_BITS_FRM_TO(16, 27); |
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tmp |= (VFrontPorchStrt << 16) | VBottomBorderStrt; |
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STG_WRITE_REG(DACVerTim3, tmp); |
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/* Set Verical and Horizontal Polarity */ |
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tmp = STG_READ_REG(DACSyncCtrl) | SET_BIT(3) | SET_BIT(1); |
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if ((pTiming->HSP > 0) && (pTiming->VSP < 0)) { /* +hsync -vsync */ |
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tmp &= ~0x8; |
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} else if ((pTiming->HSP < 0) && (pTiming->VSP > 0)) { /* -hsync +vsync */ |
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tmp &= ~0x2; |
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} else if ((pTiming->HSP < 0) && (pTiming->VSP < 0)) { /* -hsync -vsync */ |
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tmp &= ~0xA; |
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} else if ((pTiming->HSP > 0) && (pTiming->VSP > 0)) { /* +hsync -vsync */ |
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tmp &= ~0x0; |
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} |
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STG_WRITE_REG(DACSyncCtrl, tmp); |
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}
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