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219 lines
5.2 KiB
219 lines
5.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Common CPM code |
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* |
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* Author: Scott Wood <[email protected]> |
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* |
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* Copyright 2007-2008,2010 Freescale Semiconductor, Inc. |
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* |
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* Some parts derived from commproc.c/cpm2_common.c, which is: |
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* Copyright (c) 1997 Dan error_act ([email protected]) |
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* Copyright (c) 1999-2001 Dan Malek <[email protected]> |
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* Copyright (c) 2000 MontaVista Software, Inc ([email protected]) |
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* 2006 (c) MontaVista Software, Inc. |
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* Vitaly Bordug <[email protected]> |
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*/ |
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#include <linux/init.h> |
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#include <linux/of_device.h> |
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#include <linux/spinlock.h> |
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#include <linux/export.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/slab.h> |
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#include <asm/udbg.h> |
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#include <asm/io.h> |
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#include <asm/cpm.h> |
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#include <asm/fixmap.h> |
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#include <soc/fsl/qe/qe.h> |
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#include <mm/mmu_decl.h> |
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#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO) |
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#include <linux/of_gpio.h> |
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#endif |
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static int __init cpm_init(void) |
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{ |
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struct device_node *np; |
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np = of_find_compatible_node(NULL, NULL, "fsl,cpm1"); |
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if (!np) |
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np = of_find_compatible_node(NULL, NULL, "fsl,cpm2"); |
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if (!np) |
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return -ENODEV; |
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cpm_muram_init(); |
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of_node_put(np); |
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return 0; |
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} |
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subsys_initcall(cpm_init); |
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#ifdef CONFIG_PPC_EARLY_DEBUG_CPM |
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static u32 __iomem *cpm_udbg_txdesc; |
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static u8 __iomem *cpm_udbg_txbuf; |
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static void udbg_putc_cpm(char c) |
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{ |
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if (c == '\n') |
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udbg_putc_cpm('\r'); |
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while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000) |
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; |
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out_8(cpm_udbg_txbuf, c); |
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out_be32(&cpm_udbg_txdesc[0], 0xa0000001); |
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} |
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void __init udbg_init_cpm(void) |
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{ |
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#ifdef CONFIG_PPC_8xx |
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mmu_mapin_immr(); |
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cpm_udbg_txdesc = (u32 __iomem __force *) |
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(CONFIG_PPC_EARLY_DEBUG_CPM_ADDR - PHYS_IMMR_BASE + |
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VIRT_IMMR_BASE); |
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cpm_udbg_txbuf = (u8 __iomem __force *) |
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(in_be32(&cpm_udbg_txdesc[1]) - PHYS_IMMR_BASE + |
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VIRT_IMMR_BASE); |
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#else |
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cpm_udbg_txdesc = (u32 __iomem __force *) |
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CONFIG_PPC_EARLY_DEBUG_CPM_ADDR; |
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cpm_udbg_txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]); |
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#endif |
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if (cpm_udbg_txdesc) { |
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#ifdef CONFIG_CPM2 |
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setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG); |
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#endif |
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udbg_putc = udbg_putc_cpm; |
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} |
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} |
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#endif |
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#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO) |
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struct cpm2_ioports { |
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u32 dir, par, sor, odr, dat; |
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u32 res[3]; |
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}; |
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struct cpm2_gpio32_chip { |
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struct of_mm_gpio_chip mm_gc; |
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spinlock_t lock; |
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/* shadowed data register to clear/set bits safely */ |
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u32 cpdata; |
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}; |
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static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc) |
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{ |
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struct cpm2_gpio32_chip *cpm2_gc = |
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container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc); |
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struct cpm2_ioports __iomem *iop = mm_gc->regs; |
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cpm2_gc->cpdata = in_be32(&iop->dat); |
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} |
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static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio) |
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{ |
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); |
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struct cpm2_ioports __iomem *iop = mm_gc->regs; |
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u32 pin_mask; |
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pin_mask = 1 << (31 - gpio); |
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return !!(in_be32(&iop->dat) & pin_mask); |
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} |
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static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, |
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int value) |
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{ |
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struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc); |
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struct cpm2_ioports __iomem *iop = mm_gc->regs; |
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if (value) |
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cpm2_gc->cpdata |= pin_mask; |
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else |
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cpm2_gc->cpdata &= ~pin_mask; |
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out_be32(&iop->dat, cpm2_gc->cpdata); |
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} |
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static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value) |
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{ |
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); |
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struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc); |
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unsigned long flags; |
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u32 pin_mask = 1 << (31 - gpio); |
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spin_lock_irqsave(&cpm2_gc->lock, flags); |
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__cpm2_gpio32_set(mm_gc, pin_mask, value); |
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spin_unlock_irqrestore(&cpm2_gc->lock, flags); |
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} |
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static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
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{ |
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); |
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struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc); |
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struct cpm2_ioports __iomem *iop = mm_gc->regs; |
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unsigned long flags; |
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u32 pin_mask = 1 << (31 - gpio); |
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spin_lock_irqsave(&cpm2_gc->lock, flags); |
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setbits32(&iop->dir, pin_mask); |
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__cpm2_gpio32_set(mm_gc, pin_mask, val); |
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spin_unlock_irqrestore(&cpm2_gc->lock, flags); |
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return 0; |
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} |
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static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) |
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{ |
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); |
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struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc); |
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struct cpm2_ioports __iomem *iop = mm_gc->regs; |
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unsigned long flags; |
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u32 pin_mask = 1 << (31 - gpio); |
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spin_lock_irqsave(&cpm2_gc->lock, flags); |
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clrbits32(&iop->dir, pin_mask); |
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spin_unlock_irqrestore(&cpm2_gc->lock, flags); |
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return 0; |
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} |
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int cpm2_gpiochip_add32(struct device *dev) |
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{ |
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struct device_node *np = dev->of_node; |
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struct cpm2_gpio32_chip *cpm2_gc; |
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struct of_mm_gpio_chip *mm_gc; |
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struct gpio_chip *gc; |
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cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL); |
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if (!cpm2_gc) |
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return -ENOMEM; |
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spin_lock_init(&cpm2_gc->lock); |
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mm_gc = &cpm2_gc->mm_gc; |
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gc = &mm_gc->gc; |
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mm_gc->save_regs = cpm2_gpio32_save_regs; |
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gc->ngpio = 32; |
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gc->direction_input = cpm2_gpio32_dir_in; |
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gc->direction_output = cpm2_gpio32_dir_out; |
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gc->get = cpm2_gpio32_get; |
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gc->set = cpm2_gpio32_set; |
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gc->parent = dev; |
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gc->owner = THIS_MODULE; |
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return of_mm_gpiochip_add_data(np, mm_gc, cpm2_gc); |
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} |
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#endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */
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