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417 lines
9.9 KiB
417 lines
9.9 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* PowerNV LPC bus handling. |
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* |
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* Copyright 2013 IBM Corp. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/of.h> |
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#include <linux/bug.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include <asm/machdep.h> |
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#include <asm/firmware.h> |
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#include <asm/opal.h> |
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#include <asm/prom.h> |
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#include <linux/uaccess.h> |
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#include <asm/debugfs.h> |
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#include <asm/isa-bridge.h> |
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static int opal_lpc_chip_id = -1; |
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static u8 opal_lpc_inb(unsigned long port) |
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{ |
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int64_t rc; |
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__be32 data; |
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if (opal_lpc_chip_id < 0 || port > 0xffff) |
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return 0xff; |
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rc = opal_lpc_read(opal_lpc_chip_id, OPAL_LPC_IO, port, &data, 1); |
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return rc ? 0xff : be32_to_cpu(data); |
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} |
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static __le16 __opal_lpc_inw(unsigned long port) |
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{ |
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int64_t rc; |
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__be32 data; |
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if (opal_lpc_chip_id < 0 || port > 0xfffe) |
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return 0xffff; |
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if (port & 1) |
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return (__le16)opal_lpc_inb(port) << 8 | opal_lpc_inb(port + 1); |
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rc = opal_lpc_read(opal_lpc_chip_id, OPAL_LPC_IO, port, &data, 2); |
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return rc ? 0xffff : be32_to_cpu(data); |
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} |
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static u16 opal_lpc_inw(unsigned long port) |
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{ |
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return le16_to_cpu(__opal_lpc_inw(port)); |
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} |
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static __le32 __opal_lpc_inl(unsigned long port) |
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{ |
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int64_t rc; |
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__be32 data; |
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if (opal_lpc_chip_id < 0 || port > 0xfffc) |
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return 0xffffffff; |
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if (port & 3) |
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return (__le32)opal_lpc_inb(port ) << 24 | |
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(__le32)opal_lpc_inb(port + 1) << 16 | |
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(__le32)opal_lpc_inb(port + 2) << 8 | |
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opal_lpc_inb(port + 3); |
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rc = opal_lpc_read(opal_lpc_chip_id, OPAL_LPC_IO, port, &data, 4); |
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return rc ? 0xffffffff : be32_to_cpu(data); |
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} |
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static u32 opal_lpc_inl(unsigned long port) |
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{ |
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return le32_to_cpu(__opal_lpc_inl(port)); |
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} |
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static void opal_lpc_outb(u8 val, unsigned long port) |
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{ |
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if (opal_lpc_chip_id < 0 || port > 0xffff) |
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return; |
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opal_lpc_write(opal_lpc_chip_id, OPAL_LPC_IO, port, val, 1); |
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} |
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static void __opal_lpc_outw(__le16 val, unsigned long port) |
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{ |
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if (opal_lpc_chip_id < 0 || port > 0xfffe) |
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return; |
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if (port & 1) { |
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opal_lpc_outb(val >> 8, port); |
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opal_lpc_outb(val , port + 1); |
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return; |
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} |
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opal_lpc_write(opal_lpc_chip_id, OPAL_LPC_IO, port, val, 2); |
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} |
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static void opal_lpc_outw(u16 val, unsigned long port) |
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{ |
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__opal_lpc_outw(cpu_to_le16(val), port); |
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} |
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static void __opal_lpc_outl(__le32 val, unsigned long port) |
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{ |
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if (opal_lpc_chip_id < 0 || port > 0xfffc) |
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return; |
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if (port & 3) { |
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opal_lpc_outb(val >> 24, port); |
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opal_lpc_outb(val >> 16, port + 1); |
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opal_lpc_outb(val >> 8, port + 2); |
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opal_lpc_outb(val , port + 3); |
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return; |
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} |
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opal_lpc_write(opal_lpc_chip_id, OPAL_LPC_IO, port, val, 4); |
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} |
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static void opal_lpc_outl(u32 val, unsigned long port) |
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{ |
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__opal_lpc_outl(cpu_to_le32(val), port); |
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} |
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static void opal_lpc_insb(unsigned long p, void *b, unsigned long c) |
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{ |
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u8 *ptr = b; |
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while(c--) |
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*(ptr++) = opal_lpc_inb(p); |
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} |
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static void opal_lpc_insw(unsigned long p, void *b, unsigned long c) |
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{ |
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__le16 *ptr = b; |
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while(c--) |
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*(ptr++) = __opal_lpc_inw(p); |
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} |
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static void opal_lpc_insl(unsigned long p, void *b, unsigned long c) |
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{ |
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__le32 *ptr = b; |
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while(c--) |
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*(ptr++) = __opal_lpc_inl(p); |
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} |
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static void opal_lpc_outsb(unsigned long p, const void *b, unsigned long c) |
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{ |
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const u8 *ptr = b; |
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while(c--) |
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opal_lpc_outb(*(ptr++), p); |
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} |
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static void opal_lpc_outsw(unsigned long p, const void *b, unsigned long c) |
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{ |
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const __le16 *ptr = b; |
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while(c--) |
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__opal_lpc_outw(*(ptr++), p); |
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} |
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static void opal_lpc_outsl(unsigned long p, const void *b, unsigned long c) |
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{ |
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const __le32 *ptr = b; |
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while(c--) |
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__opal_lpc_outl(*(ptr++), p); |
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} |
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static const struct ppc_pci_io opal_lpc_io = { |
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.inb = opal_lpc_inb, |
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.inw = opal_lpc_inw, |
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.inl = opal_lpc_inl, |
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.outb = opal_lpc_outb, |
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.outw = opal_lpc_outw, |
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.outl = opal_lpc_outl, |
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.insb = opal_lpc_insb, |
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.insw = opal_lpc_insw, |
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.insl = opal_lpc_insl, |
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.outsb = opal_lpc_outsb, |
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.outsw = opal_lpc_outsw, |
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.outsl = opal_lpc_outsl, |
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}; |
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#ifdef CONFIG_DEBUG_FS |
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struct lpc_debugfs_entry { |
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enum OpalLPCAddressType lpc_type; |
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}; |
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static ssize_t lpc_debug_read(struct file *filp, char __user *ubuf, |
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size_t count, loff_t *ppos) |
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{ |
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struct lpc_debugfs_entry *lpc = filp->private_data; |
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u32 data, pos, len, todo; |
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int rc; |
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if (!access_ok(ubuf, count)) |
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return -EFAULT; |
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todo = count; |
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while (todo) { |
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pos = *ppos; |
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/* |
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* Select access size based on count and alignment and |
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* access type. IO and MEM only support byte acceses, |
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* FW supports all 3. |
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*/ |
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len = 1; |
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if (lpc->lpc_type == OPAL_LPC_FW) { |
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if (todo > 3 && (pos & 3) == 0) |
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len = 4; |
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else if (todo > 1 && (pos & 1) == 0) |
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len = 2; |
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} |
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rc = opal_lpc_read(opal_lpc_chip_id, lpc->lpc_type, pos, |
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&data, len); |
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if (rc) |
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return -ENXIO; |
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/* |
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* Now there is some trickery with the data returned by OPAL |
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* as it's the desired data right justified in a 32-bit BE |
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* word. |
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* |
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* This is a very bad interface and I'm to blame for it :-( |
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* |
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* So we can't just apply a 32-bit swap to what comes from OPAL, |
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* because user space expects the *bytes* to be in their proper |
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* respective positions (ie, LPC position). |
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* |
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* So what we really want to do here is to shift data right |
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* appropriately on a LE kernel. |
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* |
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* IE. If the LPC transaction has bytes B0, B1, B2 and B3 in that |
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* order, we have in memory written to by OPAL at the "data" |
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* pointer: |
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* |
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* Bytes: OPAL "data" LE "data" |
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* 32-bit: B0 B1 B2 B3 B0B1B2B3 B3B2B1B0 |
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* 16-bit: B0 B1 0000B0B1 B1B00000 |
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* 8-bit: B0 000000B0 B0000000 |
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* |
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* So a BE kernel will have the leftmost of the above in the MSB |
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* and rightmost in the LSB and can just then "cast" the u32 "data" |
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* down to the appropriate quantity and write it. |
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* |
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* However, an LE kernel can't. It doesn't need to swap because a |
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* load from data followed by a store to user are going to preserve |
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* the byte ordering which is the wire byte order which is what the |
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* user wants, but in order to "crop" to the right size, we need to |
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* shift right first. |
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*/ |
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switch(len) { |
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case 4: |
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rc = __put_user((u32)data, (u32 __user *)ubuf); |
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break; |
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case 2: |
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#ifdef __LITTLE_ENDIAN__ |
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data >>= 16; |
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#endif |
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rc = __put_user((u16)data, (u16 __user *)ubuf); |
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break; |
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default: |
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#ifdef __LITTLE_ENDIAN__ |
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data >>= 24; |
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#endif |
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rc = __put_user((u8)data, (u8 __user *)ubuf); |
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break; |
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} |
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if (rc) |
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return -EFAULT; |
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*ppos += len; |
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ubuf += len; |
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todo -= len; |
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} |
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return count; |
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} |
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static ssize_t lpc_debug_write(struct file *filp, const char __user *ubuf, |
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size_t count, loff_t *ppos) |
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{ |
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struct lpc_debugfs_entry *lpc = filp->private_data; |
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u32 data, pos, len, todo; |
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int rc; |
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if (!access_ok(ubuf, count)) |
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return -EFAULT; |
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todo = count; |
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while (todo) { |
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pos = *ppos; |
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/* |
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* Select access size based on count and alignment and |
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* access type. IO and MEM only support byte acceses, |
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* FW supports all 3. |
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*/ |
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len = 1; |
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if (lpc->lpc_type == OPAL_LPC_FW) { |
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if (todo > 3 && (pos & 3) == 0) |
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len = 4; |
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else if (todo > 1 && (pos & 1) == 0) |
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len = 2; |
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} |
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/* |
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* Similarly to the read case, we have some trickery here but |
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* it's different to handle. We need to pass the value to OPAL in |
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* a register whose layout depends on the access size. We want |
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* to reproduce the memory layout of the user, however we aren't |
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* doing a load from user and a store to another memory location |
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* which would achieve that. Here we pass the value to OPAL via |
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* a register which is expected to contain the "BE" interpretation |
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* of the byte sequence. IE: for a 32-bit access, byte 0 should be |
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* in the MSB. So here we *do* need to byteswap on LE. |
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* |
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* User bytes: LE "data" OPAL "data" |
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* 32-bit: B0 B1 B2 B3 B3B2B1B0 B0B1B2B3 |
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* 16-bit: B0 B1 0000B1B0 0000B0B1 |
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* 8-bit: B0 000000B0 000000B0 |
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*/ |
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switch(len) { |
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case 4: |
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rc = __get_user(data, (u32 __user *)ubuf); |
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data = cpu_to_be32(data); |
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break; |
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case 2: |
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rc = __get_user(data, (u16 __user *)ubuf); |
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data = cpu_to_be16(data); |
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break; |
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default: |
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rc = __get_user(data, (u8 __user *)ubuf); |
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break; |
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} |
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if (rc) |
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return -EFAULT; |
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rc = opal_lpc_write(opal_lpc_chip_id, lpc->lpc_type, pos, |
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data, len); |
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if (rc) |
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return -ENXIO; |
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*ppos += len; |
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ubuf += len; |
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todo -= len; |
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} |
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return count; |
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} |
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static const struct file_operations lpc_fops = { |
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.read = lpc_debug_read, |
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.write = lpc_debug_write, |
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.open = simple_open, |
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.llseek = default_llseek, |
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}; |
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static int opal_lpc_debugfs_create_type(struct dentry *folder, |
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const char *fname, |
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enum OpalLPCAddressType type) |
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{ |
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struct lpc_debugfs_entry *entry; |
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entry = kzalloc(sizeof(*entry), GFP_KERNEL); |
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if (!entry) |
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return -ENOMEM; |
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entry->lpc_type = type; |
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debugfs_create_file(fname, 0600, folder, entry, &lpc_fops); |
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return 0; |
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} |
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static int opal_lpc_init_debugfs(void) |
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{ |
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struct dentry *root; |
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int rc = 0; |
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if (opal_lpc_chip_id < 0) |
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return -ENODEV; |
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root = debugfs_create_dir("lpc", powerpc_debugfs_root); |
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rc |= opal_lpc_debugfs_create_type(root, "io", OPAL_LPC_IO); |
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rc |= opal_lpc_debugfs_create_type(root, "mem", OPAL_LPC_MEM); |
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rc |= opal_lpc_debugfs_create_type(root, "fw", OPAL_LPC_FW); |
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return rc; |
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} |
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machine_device_initcall(powernv, opal_lpc_init_debugfs); |
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#endif /* CONFIG_DEBUG_FS */ |
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void __init opal_lpc_init(void) |
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{ |
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struct device_node *np; |
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/* |
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* Look for a Power8 LPC bus tagged as "primary", |
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* we currently support only one though the OPAL APIs |
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* support any number. |
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*/ |
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for_each_compatible_node(np, NULL, "ibm,power8-lpc") { |
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if (!of_device_is_available(np)) |
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continue; |
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if (!of_get_property(np, "primary", NULL)) |
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continue; |
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opal_lpc_chip_id = of_get_ibm_chip_id(np); |
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break; |
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} |
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if (opal_lpc_chip_id < 0) |
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return; |
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/* Does it support direct mapping ? */ |
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if (of_get_property(np, "ranges", NULL)) { |
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pr_info("OPAL: Found memory mapped LPC bus on chip %d\n", |
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opal_lpc_chip_id); |
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isa_bridge_init_non_pci(np); |
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} else { |
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pr_info("OPAL: Found non-mapped LPC bus on chip %d\n", |
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opal_lpc_chip_id); |
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/* Setup special IO ops */ |
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ppc_pci_io = opal_lpc_io; |
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isa_io_special = true; |
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} |
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}
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