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705 lines
18 KiB
705 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* This file implements the DMA operations for NVLink devices. The NPU |
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* devices all point to the same iommu table as the parent PCI device. |
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* |
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* Copyright Alistair Popple, IBM Corporation 2015. |
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*/ |
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|
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#include <linux/mmu_notifier.h> |
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#include <linux/mmu_context.h> |
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#include <linux/of.h> |
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#include <linux/pci.h> |
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#include <linux/memblock.h> |
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#include <linux/sizes.h> |
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|
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#include <asm/debugfs.h> |
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#include <asm/powernv.h> |
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#include <asm/ppc-pci.h> |
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#include <asm/opal.h> |
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#include "pci.h" |
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static struct pci_dev *get_pci_dev(struct device_node *dn) |
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{ |
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struct pci_dn *pdn = PCI_DN(dn); |
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struct pci_dev *pdev; |
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pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdn->phb->bus), |
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pdn->busno, pdn->devfn); |
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|
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/* |
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* pci_get_domain_bus_and_slot() increased the reference count of |
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* the PCI device, but callers don't need that actually as the PE |
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* already holds a reference to the device. Since callers aren't |
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* aware of the reference count change, call pci_dev_put() now to |
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* avoid leaks. |
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*/ |
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if (pdev) |
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pci_dev_put(pdev); |
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return pdev; |
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} |
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|
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/* Given a NPU device get the associated PCI device. */ |
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struct pci_dev *pnv_pci_get_gpu_dev(struct pci_dev *npdev) |
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{ |
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struct device_node *dn; |
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struct pci_dev *gpdev; |
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if (WARN_ON(!npdev)) |
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return NULL; |
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if (WARN_ON(!npdev->dev.of_node)) |
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return NULL; |
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/* Get assoicated PCI device */ |
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dn = of_parse_phandle(npdev->dev.of_node, "ibm,gpu", 0); |
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if (!dn) |
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return NULL; |
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gpdev = get_pci_dev(dn); |
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of_node_put(dn); |
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return gpdev; |
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} |
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EXPORT_SYMBOL(pnv_pci_get_gpu_dev); |
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|
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/* Given the real PCI device get a linked NPU device. */ |
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struct pci_dev *pnv_pci_get_npu_dev(struct pci_dev *gpdev, int index) |
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{ |
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struct device_node *dn; |
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struct pci_dev *npdev; |
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if (WARN_ON(!gpdev)) |
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return NULL; |
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/* Not all PCI devices have device-tree nodes */ |
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if (!gpdev->dev.of_node) |
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return NULL; |
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/* Get assoicated PCI device */ |
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dn = of_parse_phandle(gpdev->dev.of_node, "ibm,npu", index); |
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if (!dn) |
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return NULL; |
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npdev = get_pci_dev(dn); |
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of_node_put(dn); |
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return npdev; |
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} |
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EXPORT_SYMBOL(pnv_pci_get_npu_dev); |
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#ifdef CONFIG_IOMMU_API |
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/* |
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* Returns the PE assoicated with the PCI device of the given |
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* NPU. Returns the linked pci device if pci_dev != NULL. |
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*/ |
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static struct pnv_ioda_pe *get_gpu_pci_dev_and_pe(struct pnv_ioda_pe *npe, |
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struct pci_dev **gpdev) |
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{ |
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struct pnv_phb *phb; |
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struct pci_controller *hose; |
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struct pci_dev *pdev; |
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struct pnv_ioda_pe *pe; |
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struct pci_dn *pdn; |
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pdev = pnv_pci_get_gpu_dev(npe->pdev); |
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if (!pdev) |
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return NULL; |
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pdn = pci_get_pdn(pdev); |
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if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) |
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return NULL; |
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hose = pci_bus_to_host(pdev->bus); |
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phb = hose->private_data; |
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pe = &phb->ioda.pe_array[pdn->pe_number]; |
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if (gpdev) |
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*gpdev = pdev; |
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return pe; |
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} |
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static long pnv_npu_unset_window(struct iommu_table_group *table_group, |
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int num); |
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static long pnv_npu_set_window(struct iommu_table_group *table_group, int num, |
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struct iommu_table *tbl) |
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{ |
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struct pnv_ioda_pe *npe = container_of(table_group, struct pnv_ioda_pe, |
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table_group); |
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struct pnv_phb *phb = npe->phb; |
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int64_t rc; |
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const unsigned long size = tbl->it_indirect_levels ? |
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tbl->it_level_size : tbl->it_size; |
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const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; |
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const __u64 win_size = tbl->it_size << tbl->it_page_shift; |
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int num2 = (num == 0) ? 1 : 0; |
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|
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/* NPU has just one TVE so if there is another table, remove it first */ |
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if (npe->table_group.tables[num2]) |
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pnv_npu_unset_window(&npe->table_group, num2); |
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pe_info(npe, "Setting up window %llx..%llx pg=%lx\n", |
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start_addr, start_addr + win_size - 1, |
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IOMMU_PAGE_SIZE(tbl)); |
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rc = opal_pci_map_pe_dma_window(phb->opal_id, |
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npe->pe_number, |
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npe->pe_number, |
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tbl->it_indirect_levels + 1, |
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__pa(tbl->it_base), |
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size << 3, |
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IOMMU_PAGE_SIZE(tbl)); |
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if (rc) { |
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pe_err(npe, "Failed to configure TCE table, err %lld\n", rc); |
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return rc; |
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} |
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pnv_pci_ioda2_tce_invalidate_entire(phb, false); |
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/* Add the table to the list so its TCE cache will get invalidated */ |
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pnv_pci_link_table_and_group(phb->hose->node, num, |
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tbl, &npe->table_group); |
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return 0; |
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} |
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static long pnv_npu_unset_window(struct iommu_table_group *table_group, int num) |
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{ |
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struct pnv_ioda_pe *npe = container_of(table_group, struct pnv_ioda_pe, |
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table_group); |
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struct pnv_phb *phb = npe->phb; |
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int64_t rc; |
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if (!npe->table_group.tables[num]) |
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return 0; |
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pe_info(npe, "Removing DMA window\n"); |
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rc = opal_pci_map_pe_dma_window(phb->opal_id, npe->pe_number, |
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npe->pe_number, |
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0/* levels */, 0/* table address */, |
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0/* table size */, 0/* page size */); |
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if (rc) { |
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pe_err(npe, "Unmapping failed, ret = %lld\n", rc); |
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return rc; |
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} |
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pnv_pci_ioda2_tce_invalidate_entire(phb, false); |
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pnv_pci_unlink_table_and_group(npe->table_group.tables[num], |
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&npe->table_group); |
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return 0; |
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} |
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/* Switch ownership from platform code to external user (e.g. VFIO) */ |
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static void pnv_npu_take_ownership(struct iommu_table_group *table_group) |
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{ |
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struct pnv_ioda_pe *npe = container_of(table_group, struct pnv_ioda_pe, |
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table_group); |
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struct pnv_phb *phb = npe->phb; |
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int64_t rc; |
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struct pci_dev *gpdev = NULL; |
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/* |
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* Note: NPU has just a single TVE in the hardware which means that |
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* while used by the kernel, it can have either 32bit window or |
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* DMA bypass but never both. So we deconfigure 32bit window only |
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* if it was enabled at the moment of ownership change. |
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*/ |
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if (npe->table_group.tables[0]) { |
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pnv_npu_unset_window(&npe->table_group, 0); |
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return; |
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} |
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/* Disable bypass */ |
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rc = opal_pci_map_pe_dma_window_real(phb->opal_id, |
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npe->pe_number, npe->pe_number, |
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0 /* bypass base */, 0); |
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if (rc) { |
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pe_err(npe, "Failed to disable bypass, err %lld\n", rc); |
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return; |
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} |
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pnv_pci_ioda2_tce_invalidate_entire(npe->phb, false); |
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get_gpu_pci_dev_and_pe(npe, &gpdev); |
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if (gpdev) |
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pnv_npu2_unmap_lpar_dev(gpdev); |
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} |
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static void pnv_npu_release_ownership(struct iommu_table_group *table_group) |
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{ |
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struct pnv_ioda_pe *npe = container_of(table_group, struct pnv_ioda_pe, |
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table_group); |
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struct pci_dev *gpdev = NULL; |
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get_gpu_pci_dev_and_pe(npe, &gpdev); |
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if (gpdev) |
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pnv_npu2_map_lpar_dev(gpdev, 0, MSR_DR | MSR_PR | MSR_HV); |
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} |
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static struct iommu_table_group_ops pnv_pci_npu_ops = { |
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.set_window = pnv_npu_set_window, |
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.unset_window = pnv_npu_unset_window, |
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.take_ownership = pnv_npu_take_ownership, |
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.release_ownership = pnv_npu_release_ownership, |
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}; |
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#endif /* !CONFIG_IOMMU_API */ |
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|
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/* |
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* NPU2 ATS |
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*/ |
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/* Maximum possible number of ATSD MMIO registers per NPU */ |
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#define NV_NMMU_ATSD_REGS 8 |
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#define NV_NPU_MAX_PE_NUM 16 |
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|
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/* |
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* A compound NPU IOMMU group which might consist of 1 GPU + 2xNPUs (POWER8) or |
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* up to 3 x (GPU + 2xNPUs) (POWER9). |
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*/ |
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struct npu_comp { |
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struct iommu_table_group table_group; |
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int pe_num; |
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struct pnv_ioda_pe *pe[NV_NPU_MAX_PE_NUM]; |
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}; |
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/* An NPU descriptor, valid for POWER9 only */ |
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struct npu { |
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int index; |
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struct npu_comp npucomp; |
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}; |
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#ifdef CONFIG_IOMMU_API |
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static long pnv_npu_peers_create_table_userspace( |
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struct iommu_table_group *table_group, |
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int num, __u32 page_shift, __u64 window_size, __u32 levels, |
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struct iommu_table **ptbl) |
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{ |
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struct npu_comp *npucomp = container_of(table_group, struct npu_comp, |
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table_group); |
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if (!npucomp->pe_num || !npucomp->pe[0] || |
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!npucomp->pe[0]->table_group.ops || |
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!npucomp->pe[0]->table_group.ops->create_table) |
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return -EFAULT; |
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return npucomp->pe[0]->table_group.ops->create_table( |
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&npucomp->pe[0]->table_group, num, page_shift, |
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window_size, levels, ptbl); |
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} |
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static long pnv_npu_peers_set_window(struct iommu_table_group *table_group, |
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int num, struct iommu_table *tbl) |
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{ |
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int i, j; |
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long ret = 0; |
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struct npu_comp *npucomp = container_of(table_group, struct npu_comp, |
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table_group); |
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for (i = 0; i < npucomp->pe_num; ++i) { |
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struct pnv_ioda_pe *pe = npucomp->pe[i]; |
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if (!pe->table_group.ops->set_window) |
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continue; |
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ret = pe->table_group.ops->set_window(&pe->table_group, |
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num, tbl); |
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if (ret) |
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break; |
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} |
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if (ret) { |
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for (j = 0; j < i; ++j) { |
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struct pnv_ioda_pe *pe = npucomp->pe[j]; |
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if (!pe->table_group.ops->unset_window) |
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continue; |
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ret = pe->table_group.ops->unset_window( |
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&pe->table_group, num); |
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if (ret) |
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break; |
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} |
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} else { |
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table_group->tables[num] = iommu_tce_table_get(tbl); |
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} |
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return ret; |
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} |
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static long pnv_npu_peers_unset_window(struct iommu_table_group *table_group, |
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int num) |
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{ |
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int i, j; |
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long ret = 0; |
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struct npu_comp *npucomp = container_of(table_group, struct npu_comp, |
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table_group); |
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for (i = 0; i < npucomp->pe_num; ++i) { |
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struct pnv_ioda_pe *pe = npucomp->pe[i]; |
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WARN_ON(npucomp->table_group.tables[num] != |
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table_group->tables[num]); |
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if (!npucomp->table_group.tables[num]) |
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continue; |
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if (!pe->table_group.ops->unset_window) |
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continue; |
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ret = pe->table_group.ops->unset_window(&pe->table_group, num); |
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if (ret) |
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break; |
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} |
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if (ret) { |
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for (j = 0; j < i; ++j) { |
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struct pnv_ioda_pe *pe = npucomp->pe[j]; |
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if (!npucomp->table_group.tables[num]) |
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continue; |
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if (!pe->table_group.ops->set_window) |
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continue; |
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ret = pe->table_group.ops->set_window(&pe->table_group, |
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num, table_group->tables[num]); |
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if (ret) |
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break; |
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} |
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} else if (table_group->tables[num]) { |
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iommu_tce_table_put(table_group->tables[num]); |
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table_group->tables[num] = NULL; |
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} |
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return ret; |
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} |
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static void pnv_npu_peers_take_ownership(struct iommu_table_group *table_group) |
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{ |
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int i; |
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struct npu_comp *npucomp = container_of(table_group, struct npu_comp, |
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table_group); |
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for (i = 0; i < npucomp->pe_num; ++i) { |
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struct pnv_ioda_pe *pe = npucomp->pe[i]; |
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if (!pe->table_group.ops || |
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!pe->table_group.ops->take_ownership) |
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continue; |
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pe->table_group.ops->take_ownership(&pe->table_group); |
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} |
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} |
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static void pnv_npu_peers_release_ownership( |
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struct iommu_table_group *table_group) |
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{ |
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int i; |
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struct npu_comp *npucomp = container_of(table_group, struct npu_comp, |
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table_group); |
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for (i = 0; i < npucomp->pe_num; ++i) { |
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struct pnv_ioda_pe *pe = npucomp->pe[i]; |
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if (!pe->table_group.ops || |
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!pe->table_group.ops->release_ownership) |
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continue; |
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pe->table_group.ops->release_ownership(&pe->table_group); |
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} |
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} |
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static struct iommu_table_group_ops pnv_npu_peers_ops = { |
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.get_table_size = pnv_pci_ioda2_get_table_size, |
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.create_table = pnv_npu_peers_create_table_userspace, |
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.set_window = pnv_npu_peers_set_window, |
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.unset_window = pnv_npu_peers_unset_window, |
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.take_ownership = pnv_npu_peers_take_ownership, |
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.release_ownership = pnv_npu_peers_release_ownership, |
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}; |
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static void pnv_comp_attach_table_group(struct npu_comp *npucomp, |
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struct pnv_ioda_pe *pe) |
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{ |
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if (WARN_ON(npucomp->pe_num == NV_NPU_MAX_PE_NUM)) |
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return; |
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npucomp->pe[npucomp->pe_num] = pe; |
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++npucomp->pe_num; |
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} |
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static struct iommu_table_group * |
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pnv_try_setup_npu_table_group(struct pnv_ioda_pe *pe) |
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{ |
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struct iommu_table_group *compound_group; |
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struct npu_comp *npucomp; |
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struct pci_dev *gpdev = NULL; |
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struct pci_controller *hose; |
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struct pci_dev *npdev = NULL; |
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|
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list_for_each_entry(gpdev, &pe->pbus->devices, bus_list) { |
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npdev = pnv_pci_get_npu_dev(gpdev, 0); |
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if (npdev) |
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break; |
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} |
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|
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if (!npdev) |
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/* It is not an NPU attached device, skip */ |
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return NULL; |
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hose = pci_bus_to_host(npdev->bus); |
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|
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if (hose->npu) { |
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/* P9 case: compound group is per-NPU (all gpus, all links) */ |
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npucomp = &hose->npu->npucomp; |
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} else { |
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/* P8 case: Compound group is per-GPU (1 gpu, 2 links) */ |
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npucomp = pe->npucomp = kzalloc(sizeof(*npucomp), GFP_KERNEL); |
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} |
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compound_group = &npucomp->table_group; |
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if (!compound_group->group) { |
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compound_group->ops = &pnv_npu_peers_ops; |
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iommu_register_group(compound_group, hose->global_number, |
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pe->pe_number); |
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|
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/* Steal capabilities from a GPU PE */ |
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compound_group->max_dynamic_windows_supported = |
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pe->table_group.max_dynamic_windows_supported; |
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compound_group->tce32_start = pe->table_group.tce32_start; |
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compound_group->tce32_size = pe->table_group.tce32_size; |
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compound_group->max_levels = pe->table_group.max_levels; |
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if (!compound_group->pgsizes) |
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compound_group->pgsizes = pe->table_group.pgsizes; |
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} |
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|
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/* |
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* The gpu would have been added to the iommu group that's created |
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* for the PE. Pull it out now. |
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*/ |
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iommu_del_device(&gpdev->dev); |
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|
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/* |
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* I'm not sure this is strictly required, but it's probably a good idea |
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* since the table_group for the PE is going to be attached to the |
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* compound table group. If we leave the PE's iommu group active then |
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* we might have the same table_group being modifiable via two sepeate |
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* iommu groups. |
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*/ |
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iommu_group_put(pe->table_group.group); |
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|
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/* now put the GPU into the compound group */ |
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pnv_comp_attach_table_group(npucomp, pe); |
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iommu_add_device(compound_group, &gpdev->dev); |
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|
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return compound_group; |
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} |
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|
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static struct iommu_table_group *pnv_npu_compound_attach(struct pnv_ioda_pe *pe) |
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{ |
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struct iommu_table_group *table_group; |
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struct npu_comp *npucomp; |
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struct pci_dev *gpdev = NULL; |
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struct pci_dev *npdev; |
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struct pnv_ioda_pe *gpe = get_gpu_pci_dev_and_pe(pe, &gpdev); |
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|
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WARN_ON(!(pe->flags & PNV_IODA_PE_DEV)); |
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if (!gpe) |
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return NULL; |
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|
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/* |
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* IODA2 bridges get this set up from pci_controller_ops::setup_bridge |
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* but NPU bridges do not have this hook defined so we do it here. |
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* We do not setup other table group parameters as they won't be used |
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* anyway - NVLink bridges are subordinate PEs. |
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*/ |
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pe->table_group.ops = &pnv_pci_npu_ops; |
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|
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table_group = iommu_group_get_iommudata( |
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iommu_group_get(&gpdev->dev)); |
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|
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/* |
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* On P9 NPU PHB and PCI PHB support different page sizes, |
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* keep only matching. We expect here that NVLink bridge PE pgsizes is |
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* initialized by the caller. |
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*/ |
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table_group->pgsizes &= pe->table_group.pgsizes; |
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npucomp = container_of(table_group, struct npu_comp, table_group); |
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pnv_comp_attach_table_group(npucomp, pe); |
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|
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list_for_each_entry(npdev, &pe->phb->hose->bus->devices, bus_list) { |
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struct pci_dev *gpdevtmp = pnv_pci_get_gpu_dev(npdev); |
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|
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if (gpdevtmp != gpdev) |
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continue; |
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|
|
iommu_add_device(table_group, &npdev->dev); |
|
} |
|
|
|
return table_group; |
|
} |
|
|
|
void pnv_pci_npu_setup_iommu_groups(void) |
|
{ |
|
struct pci_controller *hose; |
|
struct pnv_phb *phb; |
|
struct pnv_ioda_pe *pe; |
|
|
|
/* |
|
* For non-nvlink devices the IOMMU group is registered when the PE is |
|
* configured and devices are added to the group when the per-device |
|
* DMA setup is run. That's done in hose->ops.dma_dev_setup() which is |
|
* only initialise for "normal" IODA PHBs. |
|
* |
|
* For NVLink devices we need to ensure the NVLinks and the GPU end up |
|
* in the same IOMMU group, so that's handled here. |
|
*/ |
|
list_for_each_entry(hose, &hose_list, list_node) { |
|
phb = hose->private_data; |
|
|
|
if (phb->type == PNV_PHB_IODA2) |
|
list_for_each_entry(pe, &phb->ioda.pe_list, list) |
|
pnv_try_setup_npu_table_group(pe); |
|
} |
|
|
|
/* |
|
* Now we have all PHBs discovered, time to add NPU devices to |
|
* the corresponding IOMMU groups. |
|
*/ |
|
list_for_each_entry(hose, &hose_list, list_node) { |
|
unsigned long pgsizes; |
|
|
|
phb = hose->private_data; |
|
|
|
if (phb->type != PNV_PHB_NPU_NVLINK) |
|
continue; |
|
|
|
pgsizes = pnv_ioda_parse_tce_sizes(phb); |
|
list_for_each_entry(pe, &phb->ioda.pe_list, list) { |
|
/* |
|
* IODA2 bridges get this set up from |
|
* pci_controller_ops::setup_bridge but NPU bridges |
|
* do not have this hook defined so we do it here. |
|
*/ |
|
pe->table_group.pgsizes = pgsizes; |
|
pnv_npu_compound_attach(pe); |
|
} |
|
} |
|
} |
|
#endif /* CONFIG_IOMMU_API */ |
|
|
|
int pnv_npu2_init(struct pci_controller *hose) |
|
{ |
|
static int npu_index; |
|
struct npu *npu; |
|
int ret; |
|
|
|
npu = kzalloc(sizeof(*npu), GFP_KERNEL); |
|
if (!npu) |
|
return -ENOMEM; |
|
|
|
npu_index++; |
|
if (WARN_ON(npu_index >= NV_MAX_NPUS)) { |
|
ret = -ENOSPC; |
|
goto fail_exit; |
|
} |
|
npu->index = npu_index; |
|
hose->npu = npu; |
|
|
|
return 0; |
|
|
|
fail_exit: |
|
kfree(npu); |
|
return ret; |
|
} |
|
|
|
int pnv_npu2_map_lpar_dev(struct pci_dev *gpdev, unsigned int lparid, |
|
unsigned long msr) |
|
{ |
|
int ret; |
|
struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0); |
|
struct pci_controller *hose; |
|
struct pnv_phb *nphb; |
|
|
|
if (!npdev) |
|
return -ENODEV; |
|
|
|
hose = pci_bus_to_host(npdev->bus); |
|
if (hose->npu == NULL) { |
|
dev_info_once(&npdev->dev, "Nvlink1 does not support contexts"); |
|
return 0; |
|
} |
|
|
|
nphb = hose->private_data; |
|
|
|
dev_dbg(&gpdev->dev, "Map LPAR opalid=%llu lparid=%u\n", |
|
nphb->opal_id, lparid); |
|
/* |
|
* Currently we only support radix and non-zero LPCR only makes sense |
|
* for hash tables so skiboot expects the LPCR parameter to be a zero. |
|
*/ |
|
ret = opal_npu_map_lpar(nphb->opal_id, pci_dev_id(gpdev), lparid, |
|
0 /* LPCR bits */); |
|
if (ret) { |
|
dev_err(&gpdev->dev, "Error %d mapping device to LPAR\n", ret); |
|
return ret; |
|
} |
|
|
|
dev_dbg(&gpdev->dev, "init context opalid=%llu msr=%lx\n", |
|
nphb->opal_id, msr); |
|
ret = opal_npu_init_context(nphb->opal_id, 0/*__unused*/, msr, |
|
pci_dev_id(gpdev)); |
|
if (ret < 0) |
|
dev_err(&gpdev->dev, "Failed to init context: %d\n", ret); |
|
else |
|
ret = 0; |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(pnv_npu2_map_lpar_dev); |
|
|
|
void pnv_npu2_map_lpar(struct pnv_ioda_pe *gpe, unsigned long msr) |
|
{ |
|
struct pci_dev *gpdev; |
|
|
|
list_for_each_entry(gpdev, &gpe->pbus->devices, bus_list) |
|
pnv_npu2_map_lpar_dev(gpdev, 0, msr); |
|
} |
|
|
|
int pnv_npu2_unmap_lpar_dev(struct pci_dev *gpdev) |
|
{ |
|
int ret; |
|
struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0); |
|
struct pci_controller *hose; |
|
struct pnv_phb *nphb; |
|
|
|
if (!npdev) |
|
return -ENODEV; |
|
|
|
hose = pci_bus_to_host(npdev->bus); |
|
if (hose->npu == NULL) { |
|
dev_info_once(&npdev->dev, "Nvlink1 does not support contexts"); |
|
return 0; |
|
} |
|
|
|
nphb = hose->private_data; |
|
|
|
dev_dbg(&gpdev->dev, "destroy context opalid=%llu\n", |
|
nphb->opal_id); |
|
ret = opal_npu_destroy_context(nphb->opal_id, 0/*__unused*/, |
|
pci_dev_id(gpdev)); |
|
if (ret < 0) { |
|
dev_err(&gpdev->dev, "Failed to destroy context: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
/* Set LPID to 0 anyway, just to be safe */ |
|
dev_dbg(&gpdev->dev, "Map LPAR opalid=%llu lparid=0\n", nphb->opal_id); |
|
ret = opal_npu_map_lpar(nphb->opal_id, pci_dev_id(gpdev), 0 /*LPID*/, |
|
0 /* LPCR bits */); |
|
if (ret) |
|
dev_err(&gpdev->dev, "Error %d mapping device to LPAR\n", ret); |
|
|
|
return ret; |
|
} |
|
EXPORT_SYMBOL_GPL(pnv_npu2_unmap_lpar_dev);
|
|
|