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299 lines
6.3 KiB
299 lines
6.3 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2006 PA Semi, Inc |
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* |
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* Authors: Kip Walker, PA Semi |
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* Olof Johansson, PA Semi |
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* |
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* Maintained by: Olof Johansson <[email protected]> |
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* |
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* Based on arch/powerpc/platforms/maple/pci.c |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/pci.h> |
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#include <asm/pci-bridge.h> |
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#include <asm/isa-bridge.h> |
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#include <asm/machdep.h> |
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#include <asm/ppc-pci.h> |
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#include "pasemi.h" |
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#define PA_PXP_CFA(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off)) |
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static inline int pa_pxp_offset_valid(u8 bus, u8 devfn, int offset) |
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{ |
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/* Device 0 Function 0 is special: It's config space spans function 1 as |
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* well, so allow larger offset. It's really a two-function device but the |
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* second function does not probe. |
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*/ |
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if (bus == 0 && devfn == 0) |
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return offset < 8192; |
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else |
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return offset < 4096; |
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} |
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static void volatile __iomem *pa_pxp_cfg_addr(struct pci_controller *hose, |
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u8 bus, u8 devfn, int offset) |
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{ |
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return hose->cfg_data + PA_PXP_CFA(bus, devfn, offset); |
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} |
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static inline int is_root_port(int busno, int devfn) |
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{ |
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return ((busno == 0) && (PCI_FUNC(devfn) < 4) && |
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((PCI_SLOT(devfn) == 16) || (PCI_SLOT(devfn) == 17))); |
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} |
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static inline int is_5945_reg(int reg) |
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{ |
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return (((reg >= 0x18) && (reg < 0x34)) || |
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((reg >= 0x158) && (reg < 0x178))); |
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} |
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static int workaround_5945(struct pci_bus *bus, unsigned int devfn, |
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int offset, int len, u32 *val) |
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{ |
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struct pci_controller *hose; |
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void volatile __iomem *addr, *dummy; |
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int byte; |
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u32 tmp; |
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if (!is_root_port(bus->number, devfn) || !is_5945_reg(offset)) |
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return 0; |
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hose = pci_bus_to_host(bus); |
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addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset & ~0x3); |
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byte = offset & 0x3; |
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/* Workaround bug 5945: write 0 to a dummy register before reading, |
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* and write back what we read. We must read/write the full 32-bit |
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* contents so we need to shift and mask by hand. |
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*/ |
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dummy = pa_pxp_cfg_addr(hose, bus->number, devfn, 0x10); |
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out_le32(dummy, 0); |
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tmp = in_le32(addr); |
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out_le32(addr, tmp); |
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switch (len) { |
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case 1: |
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*val = (tmp >> (8*byte)) & 0xff; |
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break; |
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case 2: |
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if (byte == 0) |
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*val = tmp & 0xffff; |
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else |
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*val = (tmp >> 16) & 0xffff; |
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break; |
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default: |
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*val = tmp; |
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break; |
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} |
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return 1; |
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} |
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#ifdef CONFIG_PPC_PASEMI_NEMO |
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#define PXP_ERR_CFG_REG 0x4 |
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#define PXP_IGNORE_PCIE_ERRORS 0x800 |
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#define SB600_BUS 5 |
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static void sb600_set_flag(int bus) |
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{ |
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static void __iomem *iob_mapbase = NULL; |
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struct resource res; |
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struct device_node *dn; |
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int err; |
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if (iob_mapbase == NULL) { |
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dn = of_find_compatible_node(NULL, "isa", "pasemi,1682m-iob"); |
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if (!dn) { |
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pr_crit("NEMO SB600 missing iob node\n"); |
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return; |
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} |
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err = of_address_to_resource(dn, 0, &res); |
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of_node_put(dn); |
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if (err) { |
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pr_crit("NEMO SB600 missing resource\n"); |
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return; |
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} |
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pr_info("NEMO SB600 IOB base %08llx\n",res.start); |
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iob_mapbase = ioremap(res.start + 0x100, 0x94); |
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} |
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if (iob_mapbase != NULL) { |
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if (bus == SB600_BUS) { |
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/* |
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* This is the SB600's bus, tell the PCI-e root port |
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* to allow non-zero devices to enumerate. |
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*/ |
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out_le32(iob_mapbase + PXP_ERR_CFG_REG, in_le32(iob_mapbase + PXP_ERR_CFG_REG) | PXP_IGNORE_PCIE_ERRORS); |
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} else { |
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/* |
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* Only scan device 0 on other busses |
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*/ |
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out_le32(iob_mapbase + PXP_ERR_CFG_REG, in_le32(iob_mapbase + PXP_ERR_CFG_REG) & ~PXP_IGNORE_PCIE_ERRORS); |
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} |
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} |
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} |
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#else |
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static void sb600_set_flag(int bus) |
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{ |
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} |
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#endif |
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static int pa_pxp_read_config(struct pci_bus *bus, unsigned int devfn, |
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int offset, int len, u32 *val) |
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{ |
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struct pci_controller *hose; |
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void volatile __iomem *addr; |
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hose = pci_bus_to_host(bus); |
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if (!hose) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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if (!pa_pxp_offset_valid(bus->number, devfn, offset)) |
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return PCIBIOS_BAD_REGISTER_NUMBER; |
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if (workaround_5945(bus, devfn, offset, len, val)) |
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return PCIBIOS_SUCCESSFUL; |
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addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset); |
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sb600_set_flag(bus->number); |
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/* |
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* Note: the caller has already checked that offset is |
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* suitably aligned and that len is 1, 2 or 4. |
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*/ |
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switch (len) { |
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case 1: |
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*val = in_8(addr); |
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break; |
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case 2: |
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*val = in_le16(addr); |
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break; |
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default: |
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*val = in_le32(addr); |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int pa_pxp_write_config(struct pci_bus *bus, unsigned int devfn, |
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int offset, int len, u32 val) |
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{ |
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struct pci_controller *hose; |
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void volatile __iomem *addr; |
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hose = pci_bus_to_host(bus); |
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if (!hose) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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if (!pa_pxp_offset_valid(bus->number, devfn, offset)) |
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return PCIBIOS_BAD_REGISTER_NUMBER; |
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addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset); |
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sb600_set_flag(bus->number); |
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/* |
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* Note: the caller has already checked that offset is |
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* suitably aligned and that len is 1, 2 or 4. |
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*/ |
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switch (len) { |
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case 1: |
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out_8(addr, val); |
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break; |
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case 2: |
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out_le16(addr, val); |
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break; |
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default: |
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out_le32(addr, val); |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static struct pci_ops pa_pxp_ops = { |
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.read = pa_pxp_read_config, |
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.write = pa_pxp_write_config, |
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}; |
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static void __init setup_pa_pxp(struct pci_controller *hose) |
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{ |
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hose->ops = &pa_pxp_ops; |
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hose->cfg_data = ioremap(0xe0000000, 0x10000000); |
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} |
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static int __init pas_add_bridge(struct device_node *dev) |
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{ |
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struct pci_controller *hose; |
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pr_debug("Adding PCI host bridge %pOF\n", dev); |
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hose = pcibios_alloc_controller(dev); |
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if (!hose) |
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return -ENOMEM; |
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hose->first_busno = 0; |
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hose->last_busno = 0xff; |
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hose->controller_ops = pasemi_pci_controller_ops; |
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setup_pa_pxp(hose); |
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pr_info("Found PA-PXP PCI host bridge.\n"); |
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/* Interpret the "ranges" property */ |
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pci_process_bridge_OF_ranges(hose, dev, 1); |
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/* |
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* Scan for an isa bridge. This is needed to find the SB600 on the nemo |
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* and does nothing on machines without one. |
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*/ |
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isa_bridge_find_early(hose); |
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return 0; |
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} |
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void __init pas_pci_init(void) |
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{ |
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struct device_node *np, *root; |
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int res; |
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root = of_find_node_by_path("/"); |
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if (!root) { |
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pr_crit("pas_pci_init: can't find root of device tree\n"); |
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return; |
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} |
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pci_set_flags(PCI_SCAN_ALL_PCIE_DEVS); |
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np = of_find_compatible_node(root, NULL, "pasemi,rootbus"); |
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if (np) { |
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res = pas_add_bridge(np); |
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of_node_put(np); |
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} |
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} |
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void __iomem *pasemi_pci_getcfgaddr(struct pci_dev *dev, int offset) |
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{ |
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struct pci_controller *hose; |
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hose = pci_bus_to_host(dev->bus); |
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return (void __iomem *)pa_pxp_cfg_addr(hose, dev->bus->number, dev->devfn, offset); |
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} |
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struct pci_controller_ops pasemi_pci_controller_ops;
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