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619 lines
15 KiB
619 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2006-2007 PA Semi, Inc |
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* |
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* Common functions for DMA access on PA Semi PWRficient |
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*/ |
|
|
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#include <linux/kernel.h> |
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#include <linux/export.h> |
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#include <linux/pci.h> |
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#include <linux/slab.h> |
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#include <linux/of.h> |
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#include <linux/sched.h> |
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|
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#include <asm/pasemi_dma.h> |
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|
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#define MAX_TXCH 64 |
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#define MAX_RXCH 64 |
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#define MAX_FLAGS 64 |
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#define MAX_FUN 8 |
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|
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static struct pasdma_status *dma_status; |
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|
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static void __iomem *iob_regs; |
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static void __iomem *mac_regs[6]; |
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static void __iomem *dma_regs; |
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|
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static int base_hw_irq; |
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static int num_txch, num_rxch; |
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static struct pci_dev *dma_pdev; |
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|
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/* Bitmaps to handle allocation of channels */ |
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|
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static DECLARE_BITMAP(txch_free, MAX_TXCH); |
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static DECLARE_BITMAP(rxch_free, MAX_RXCH); |
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static DECLARE_BITMAP(flags_free, MAX_FLAGS); |
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static DECLARE_BITMAP(fun_free, MAX_FUN); |
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|
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/* pasemi_read_iob_reg - read IOB register |
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* @reg: Register to read (offset into PCI CFG space) |
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*/ |
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unsigned int pasemi_read_iob_reg(unsigned int reg) |
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{ |
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return in_le32(iob_regs+reg); |
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} |
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EXPORT_SYMBOL(pasemi_read_iob_reg); |
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|
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/* pasemi_write_iob_reg - write IOB register |
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* @reg: Register to write to (offset into PCI CFG space) |
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* @val: Value to write |
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*/ |
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void pasemi_write_iob_reg(unsigned int reg, unsigned int val) |
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{ |
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out_le32(iob_regs+reg, val); |
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} |
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EXPORT_SYMBOL(pasemi_write_iob_reg); |
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|
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/* pasemi_read_mac_reg - read MAC register |
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* @intf: MAC interface |
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* @reg: Register to read (offset into PCI CFG space) |
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*/ |
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unsigned int pasemi_read_mac_reg(int intf, unsigned int reg) |
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{ |
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return in_le32(mac_regs[intf]+reg); |
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} |
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EXPORT_SYMBOL(pasemi_read_mac_reg); |
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|
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/* pasemi_write_mac_reg - write MAC register |
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* @intf: MAC interface |
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* @reg: Register to write to (offset into PCI CFG space) |
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* @val: Value to write |
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*/ |
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void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val) |
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{ |
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out_le32(mac_regs[intf]+reg, val); |
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} |
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EXPORT_SYMBOL(pasemi_write_mac_reg); |
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|
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/* pasemi_read_dma_reg - read DMA register |
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* @reg: Register to read (offset into PCI CFG space) |
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*/ |
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unsigned int pasemi_read_dma_reg(unsigned int reg) |
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{ |
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return in_le32(dma_regs+reg); |
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} |
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EXPORT_SYMBOL(pasemi_read_dma_reg); |
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|
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/* pasemi_write_dma_reg - write DMA register |
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* @reg: Register to write to (offset into PCI CFG space) |
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* @val: Value to write |
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*/ |
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void pasemi_write_dma_reg(unsigned int reg, unsigned int val) |
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{ |
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out_le32(dma_regs+reg, val); |
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} |
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EXPORT_SYMBOL(pasemi_write_dma_reg); |
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|
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static int pasemi_alloc_tx_chan(enum pasemi_dmachan_type type) |
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{ |
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int bit; |
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int start, limit; |
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|
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switch (type & (TXCHAN_EVT0|TXCHAN_EVT1)) { |
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case TXCHAN_EVT0: |
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start = 0; |
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limit = 10; |
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break; |
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case TXCHAN_EVT1: |
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start = 10; |
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limit = MAX_TXCH; |
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break; |
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default: |
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start = 0; |
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limit = MAX_TXCH; |
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break; |
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} |
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retry: |
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bit = find_next_bit(txch_free, MAX_TXCH, start); |
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if (bit >= limit) |
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return -ENOSPC; |
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if (!test_and_clear_bit(bit, txch_free)) |
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goto retry; |
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|
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return bit; |
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} |
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|
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static void pasemi_free_tx_chan(int chan) |
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{ |
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BUG_ON(test_bit(chan, txch_free)); |
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set_bit(chan, txch_free); |
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} |
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|
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static int pasemi_alloc_rx_chan(void) |
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{ |
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int bit; |
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retry: |
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bit = find_first_bit(rxch_free, MAX_RXCH); |
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if (bit >= MAX_TXCH) |
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return -ENOSPC; |
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if (!test_and_clear_bit(bit, rxch_free)) |
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goto retry; |
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|
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return bit; |
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} |
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|
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static void pasemi_free_rx_chan(int chan) |
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{ |
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BUG_ON(test_bit(chan, rxch_free)); |
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set_bit(chan, rxch_free); |
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} |
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|
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/* pasemi_dma_alloc_chan - Allocate a DMA channel |
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* @type: Type of channel to allocate |
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* @total_size: Total size of structure to allocate (to allow for more |
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* room behind the structure to be used by the client) |
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* @offset: Offset in bytes from start of the total structure to the beginning |
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* of struct pasemi_dmachan. Needed when struct pasemi_dmachan is |
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* not the first member of the client structure. |
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* |
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* pasemi_dma_alloc_chan allocates a DMA channel for use by a client. The |
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* type argument specifies whether it's a RX or TX channel, and in the case |
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* of TX channels which group it needs to belong to (if any). |
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* |
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* Returns a pointer to the total structure allocated on success, NULL |
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* on failure. |
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*/ |
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void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type, |
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int total_size, int offset) |
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{ |
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void *buf; |
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struct pasemi_dmachan *chan; |
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int chno; |
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|
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BUG_ON(total_size < sizeof(struct pasemi_dmachan)); |
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buf = kzalloc(total_size, GFP_KERNEL); |
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|
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if (!buf) |
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return NULL; |
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chan = buf + offset; |
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|
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chan->priv = buf; |
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|
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switch (type & (TXCHAN|RXCHAN)) { |
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case RXCHAN: |
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chno = pasemi_alloc_rx_chan(); |
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chan->chno = chno; |
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chan->irq = irq_create_mapping(NULL, |
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base_hw_irq + num_txch + chno); |
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chan->status = &dma_status->rx_sta[chno]; |
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break; |
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case TXCHAN: |
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chno = pasemi_alloc_tx_chan(type); |
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chan->chno = chno; |
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chan->irq = irq_create_mapping(NULL, base_hw_irq + chno); |
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chan->status = &dma_status->tx_sta[chno]; |
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break; |
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} |
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|
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chan->chan_type = type; |
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|
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return chan; |
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} |
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EXPORT_SYMBOL(pasemi_dma_alloc_chan); |
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|
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/* pasemi_dma_free_chan - Free a previously allocated channel |
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* @chan: Channel to free |
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* |
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* Frees a previously allocated channel. It will also deallocate any |
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* descriptor ring associated with the channel, if allocated. |
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*/ |
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void pasemi_dma_free_chan(struct pasemi_dmachan *chan) |
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{ |
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if (chan->ring_virt) |
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pasemi_dma_free_ring(chan); |
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|
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switch (chan->chan_type & (RXCHAN|TXCHAN)) { |
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case RXCHAN: |
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pasemi_free_rx_chan(chan->chno); |
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break; |
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case TXCHAN: |
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pasemi_free_tx_chan(chan->chno); |
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break; |
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} |
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|
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kfree(chan->priv); |
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} |
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EXPORT_SYMBOL(pasemi_dma_free_chan); |
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|
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/* pasemi_dma_alloc_ring - Allocate descriptor ring for a channel |
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* @chan: Channel for which to allocate |
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* @ring_size: Ring size in 64-bit (8-byte) words |
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* |
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* Allocate a descriptor ring for a channel. Returns 0 on success, errno |
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* on failure. The passed in struct pasemi_dmachan is updated with the |
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* virtual and DMA addresses of the ring. |
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*/ |
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int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size) |
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{ |
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BUG_ON(chan->ring_virt); |
|
|
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chan->ring_size = ring_size; |
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|
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chan->ring_virt = dma_alloc_coherent(&dma_pdev->dev, |
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ring_size * sizeof(u64), |
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&chan->ring_dma, GFP_KERNEL); |
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|
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if (!chan->ring_virt) |
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return -ENOMEM; |
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|
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return 0; |
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} |
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EXPORT_SYMBOL(pasemi_dma_alloc_ring); |
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|
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/* pasemi_dma_free_ring - Free an allocated descriptor ring for a channel |
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* @chan: Channel for which to free the descriptor ring |
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* |
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* Frees a previously allocated descriptor ring for a channel. |
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*/ |
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void pasemi_dma_free_ring(struct pasemi_dmachan *chan) |
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{ |
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BUG_ON(!chan->ring_virt); |
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|
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dma_free_coherent(&dma_pdev->dev, chan->ring_size * sizeof(u64), |
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chan->ring_virt, chan->ring_dma); |
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chan->ring_virt = NULL; |
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chan->ring_size = 0; |
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chan->ring_dma = 0; |
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} |
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EXPORT_SYMBOL(pasemi_dma_free_ring); |
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|
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/* pasemi_dma_start_chan - Start a DMA channel |
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* @chan: Channel to start |
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* @cmdsta: Additional CCMDSTA/TCMDSTA bits to write |
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* |
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* Enables (starts) a DMA channel with optional additional arguments. |
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*/ |
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void pasemi_dma_start_chan(const struct pasemi_dmachan *chan, const u32 cmdsta) |
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{ |
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if (chan->chan_type == RXCHAN) |
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pasemi_write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno), |
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cmdsta | PAS_DMA_RXCHAN_CCMDSTA_EN); |
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else |
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pasemi_write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno), |
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cmdsta | PAS_DMA_TXCHAN_TCMDSTA_EN); |
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} |
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EXPORT_SYMBOL(pasemi_dma_start_chan); |
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|
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/* pasemi_dma_stop_chan - Stop a DMA channel |
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* @chan: Channel to stop |
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* |
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* Stops (disables) a DMA channel. This is done by setting the ST bit in the |
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* CMDSTA register and waiting on the ACT (active) bit to clear, then |
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* finally disabling the whole channel. |
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* |
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* This function will only try for a short while for the channel to stop, if |
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* it doesn't it will return failure. |
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* |
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* Returns 1 on success, 0 on failure. |
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*/ |
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#define MAX_RETRIES 5000 |
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int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan) |
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{ |
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int reg, retries; |
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u32 sta; |
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|
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if (chan->chan_type == RXCHAN) { |
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reg = PAS_DMA_RXCHAN_CCMDSTA(chan->chno); |
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pasemi_write_dma_reg(reg, PAS_DMA_RXCHAN_CCMDSTA_ST); |
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for (retries = 0; retries < MAX_RETRIES; retries++) { |
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sta = pasemi_read_dma_reg(reg); |
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if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)) { |
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pasemi_write_dma_reg(reg, 0); |
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return 1; |
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} |
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cond_resched(); |
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} |
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} else { |
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reg = PAS_DMA_TXCHAN_TCMDSTA(chan->chno); |
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pasemi_write_dma_reg(reg, PAS_DMA_TXCHAN_TCMDSTA_ST); |
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for (retries = 0; retries < MAX_RETRIES; retries++) { |
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sta = pasemi_read_dma_reg(reg); |
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if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)) { |
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pasemi_write_dma_reg(reg, 0); |
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return 1; |
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} |
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cond_resched(); |
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} |
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} |
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|
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return 0; |
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} |
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EXPORT_SYMBOL(pasemi_dma_stop_chan); |
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|
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/* pasemi_dma_alloc_buf - Allocate a buffer to use for DMA |
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* @chan: Channel to allocate for |
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* @size: Size of buffer in bytes |
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* @handle: DMA handle |
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* |
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* Allocate a buffer to be used by the DMA engine for read/write, |
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* similar to dma_alloc_coherent(). |
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* |
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* Returns the virtual address of the buffer, or NULL in case of failure. |
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*/ |
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void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size, |
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dma_addr_t *handle) |
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{ |
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return dma_alloc_coherent(&dma_pdev->dev, size, handle, GFP_KERNEL); |
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} |
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EXPORT_SYMBOL(pasemi_dma_alloc_buf); |
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|
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/* pasemi_dma_free_buf - Free a buffer used for DMA |
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* @chan: Channel the buffer was allocated for |
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* @size: Size of buffer in bytes |
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* @handle: DMA handle |
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* |
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* Frees a previously allocated buffer. |
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*/ |
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void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size, |
|
dma_addr_t *handle) |
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{ |
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dma_free_coherent(&dma_pdev->dev, size, handle, GFP_KERNEL); |
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} |
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EXPORT_SYMBOL(pasemi_dma_free_buf); |
|
|
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/* pasemi_dma_alloc_flag - Allocate a flag (event) for channel synchronization |
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* |
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* Allocates a flag for use with channel synchronization (event descriptors). |
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* Returns allocated flag (0-63), < 0 on error. |
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*/ |
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int pasemi_dma_alloc_flag(void) |
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{ |
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int bit; |
|
|
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retry: |
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bit = find_next_bit(flags_free, MAX_FLAGS, 0); |
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if (bit >= MAX_FLAGS) |
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return -ENOSPC; |
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if (!test_and_clear_bit(bit, flags_free)) |
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goto retry; |
|
|
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return bit; |
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} |
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EXPORT_SYMBOL(pasemi_dma_alloc_flag); |
|
|
|
|
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/* pasemi_dma_free_flag - Deallocates a flag (event) |
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* @flag: Flag number to deallocate |
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* |
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* Frees up a flag so it can be reused for other purposes. |
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*/ |
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void pasemi_dma_free_flag(int flag) |
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{ |
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BUG_ON(test_bit(flag, flags_free)); |
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BUG_ON(flag >= MAX_FLAGS); |
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set_bit(flag, flags_free); |
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} |
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EXPORT_SYMBOL(pasemi_dma_free_flag); |
|
|
|
|
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/* pasemi_dma_set_flag - Sets a flag (event) to 1 |
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* @flag: Flag number to set active |
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* |
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* Sets the flag provided to 1. |
|
*/ |
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void pasemi_dma_set_flag(int flag) |
|
{ |
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BUG_ON(flag >= MAX_FLAGS); |
|
if (flag < 32) |
|
pasemi_write_dma_reg(PAS_DMA_TXF_SFLG0, 1 << flag); |
|
else |
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pasemi_write_dma_reg(PAS_DMA_TXF_SFLG1, 1 << flag); |
|
} |
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EXPORT_SYMBOL(pasemi_dma_set_flag); |
|
|
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/* pasemi_dma_clear_flag - Sets a flag (event) to 0 |
|
* @flag: Flag number to set inactive |
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* |
|
* Sets the flag provided to 0. |
|
*/ |
|
void pasemi_dma_clear_flag(int flag) |
|
{ |
|
BUG_ON(flag >= MAX_FLAGS); |
|
if (flag < 32) |
|
pasemi_write_dma_reg(PAS_DMA_TXF_CFLG0, 1 << flag); |
|
else |
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pasemi_write_dma_reg(PAS_DMA_TXF_CFLG1, 1 << flag); |
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} |
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EXPORT_SYMBOL(pasemi_dma_clear_flag); |
|
|
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/* pasemi_dma_alloc_fun - Allocate a function engine |
|
* |
|
* Allocates a function engine to use for crypto/checksum offload |
|
* Returns allocated engine (0-8), < 0 on error. |
|
*/ |
|
int pasemi_dma_alloc_fun(void) |
|
{ |
|
int bit; |
|
|
|
retry: |
|
bit = find_next_bit(fun_free, MAX_FLAGS, 0); |
|
if (bit >= MAX_FLAGS) |
|
return -ENOSPC; |
|
if (!test_and_clear_bit(bit, fun_free)) |
|
goto retry; |
|
|
|
return bit; |
|
} |
|
EXPORT_SYMBOL(pasemi_dma_alloc_fun); |
|
|
|
|
|
/* pasemi_dma_free_fun - Deallocates a function engine |
|
* @flag: Engine number to deallocate |
|
* |
|
* Frees up a function engine so it can be used for other purposes. |
|
*/ |
|
void pasemi_dma_free_fun(int fun) |
|
{ |
|
BUG_ON(test_bit(fun, fun_free)); |
|
BUG_ON(fun >= MAX_FLAGS); |
|
set_bit(fun, fun_free); |
|
} |
|
EXPORT_SYMBOL(pasemi_dma_free_fun); |
|
|
|
|
|
static void *map_onedev(struct pci_dev *p, int index) |
|
{ |
|
struct device_node *dn; |
|
void __iomem *ret; |
|
|
|
dn = pci_device_to_OF_node(p); |
|
if (!dn) |
|
goto fallback; |
|
|
|
ret = of_iomap(dn, index); |
|
if (!ret) |
|
goto fallback; |
|
|
|
return ret; |
|
fallback: |
|
/* This is hardcoded and ugly, but we have some firmware versions |
|
* that don't provide the register space in the device tree. Luckily |
|
* they are at well-known locations so we can just do the math here. |
|
*/ |
|
return ioremap(0xe0000000 + (p->devfn << 12), 0x2000); |
|
} |
|
|
|
/* pasemi_dma_init - Initialize the PA Semi DMA library |
|
* |
|
* This function initializes the DMA library. It must be called before |
|
* any other function in the library. |
|
* |
|
* Returns 0 on success, errno on failure. |
|
*/ |
|
int pasemi_dma_init(void) |
|
{ |
|
static DEFINE_SPINLOCK(init_lock); |
|
struct pci_dev *iob_pdev; |
|
struct pci_dev *pdev; |
|
struct resource res; |
|
struct device_node *dn; |
|
int i, intf, err = 0; |
|
unsigned long timeout; |
|
u32 tmp; |
|
|
|
if (!machine_is(pasemi)) |
|
return -ENODEV; |
|
|
|
spin_lock(&init_lock); |
|
|
|
/* Make sure we haven't already initialized */ |
|
if (dma_pdev) |
|
goto out; |
|
|
|
iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); |
|
if (!iob_pdev) { |
|
BUG(); |
|
pr_warn("Can't find I/O Bridge\n"); |
|
err = -ENODEV; |
|
goto out; |
|
} |
|
iob_regs = map_onedev(iob_pdev, 0); |
|
|
|
dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL); |
|
if (!dma_pdev) { |
|
BUG(); |
|
pr_warn("Can't find DMA controller\n"); |
|
err = -ENODEV; |
|
goto out; |
|
} |
|
dma_regs = map_onedev(dma_pdev, 0); |
|
base_hw_irq = virq_to_hw(dma_pdev->irq); |
|
|
|
pci_read_config_dword(dma_pdev, PAS_DMA_CAP_TXCH, &tmp); |
|
num_txch = (tmp & PAS_DMA_CAP_TXCH_TCHN_M) >> PAS_DMA_CAP_TXCH_TCHN_S; |
|
|
|
pci_read_config_dword(dma_pdev, PAS_DMA_CAP_RXCH, &tmp); |
|
num_rxch = (tmp & PAS_DMA_CAP_RXCH_RCHN_M) >> PAS_DMA_CAP_RXCH_RCHN_S; |
|
|
|
intf = 0; |
|
for (pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa006, NULL); |
|
pdev; |
|
pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa006, pdev)) |
|
mac_regs[intf++] = map_onedev(pdev, 0); |
|
|
|
pci_dev_put(pdev); |
|
|
|
for (pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa005, NULL); |
|
pdev; |
|
pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa005, pdev)) |
|
mac_regs[intf++] = map_onedev(pdev, 0); |
|
|
|
pci_dev_put(pdev); |
|
|
|
dn = pci_device_to_OF_node(iob_pdev); |
|
if (dn) |
|
err = of_address_to_resource(dn, 1, &res); |
|
if (!dn || err) { |
|
/* Fallback for old firmware */ |
|
res.start = 0xfd800000; |
|
res.end = res.start + 0x1000; |
|
} |
|
dma_status = ioremap_cache(res.start, resource_size(&res)); |
|
pci_dev_put(iob_pdev); |
|
|
|
for (i = 0; i < MAX_TXCH; i++) |
|
__set_bit(i, txch_free); |
|
|
|
for (i = 0; i < MAX_RXCH; i++) |
|
__set_bit(i, rxch_free); |
|
|
|
timeout = jiffies + HZ; |
|
pasemi_write_dma_reg(PAS_DMA_COM_RXCMD, 0); |
|
while (pasemi_read_dma_reg(PAS_DMA_COM_RXSTA) & 1) { |
|
if (time_after(jiffies, timeout)) { |
|
pr_warn("Warning: Could not disable RX section\n"); |
|
break; |
|
} |
|
} |
|
|
|
timeout = jiffies + HZ; |
|
pasemi_write_dma_reg(PAS_DMA_COM_TXCMD, 0); |
|
while (pasemi_read_dma_reg(PAS_DMA_COM_TXSTA) & 1) { |
|
if (time_after(jiffies, timeout)) { |
|
pr_warn("Warning: Could not disable TX section\n"); |
|
break; |
|
} |
|
} |
|
|
|
/* setup resource allocations for the different DMA sections */ |
|
tmp = pasemi_read_dma_reg(PAS_DMA_COM_CFG); |
|
pasemi_write_dma_reg(PAS_DMA_COM_CFG, tmp | 0x18000000); |
|
|
|
/* enable tx section */ |
|
pasemi_write_dma_reg(PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); |
|
|
|
/* enable rx section */ |
|
pasemi_write_dma_reg(PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN); |
|
|
|
for (i = 0; i < MAX_FLAGS; i++) |
|
__set_bit(i, flags_free); |
|
|
|
for (i = 0; i < MAX_FUN; i++) |
|
__set_bit(i, fun_free); |
|
|
|
/* clear all status flags */ |
|
pasemi_write_dma_reg(PAS_DMA_TXF_CFLG0, 0xffffffff); |
|
pasemi_write_dma_reg(PAS_DMA_TXF_CFLG1, 0xffffffff); |
|
|
|
pr_info("PA Semi PWRficient DMA library initialized " |
|
"(%d tx, %d rx channels)\n", num_txch, num_rxch); |
|
|
|
out: |
|
spin_unlock(&init_lock); |
|
return err; |
|
} |
|
EXPORT_SYMBOL(pasemi_dma_init);
|
|
|