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162 lines
3.6 KiB
162 lines
3.6 KiB
#include <linux/kernel.h> |
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#include <linux/stddef.h> |
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#include <linux/sched.h> |
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#include <linux/signal.h> |
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#include <linux/irq.h> |
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#include <linux/dma-mapping.h> |
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#include <asm/prom.h> |
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#include <asm/irq.h> |
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#include <asm/io.h> |
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#include <asm/8xx_immap.h> |
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#include "pic.h" |
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#define PIC_VEC_SPURRIOUS 15 |
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extern int cpm_get_irq(struct pt_regs *regs); |
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static struct irq_domain *mpc8xx_pic_host; |
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static unsigned long mpc8xx_cached_irq_mask; |
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static sysconf8xx_t __iomem *siu_reg; |
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static inline unsigned long mpc8xx_irqd_to_bit(struct irq_data *d) |
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{ |
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return 0x80000000 >> irqd_to_hwirq(d); |
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} |
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static void mpc8xx_unmask_irq(struct irq_data *d) |
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{ |
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mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d); |
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out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask); |
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} |
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static void mpc8xx_mask_irq(struct irq_data *d) |
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{ |
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mpc8xx_cached_irq_mask &= ~mpc8xx_irqd_to_bit(d); |
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out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask); |
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} |
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static void mpc8xx_ack(struct irq_data *d) |
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{ |
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out_be32(&siu_reg->sc_sipend, mpc8xx_irqd_to_bit(d)); |
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} |
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static void mpc8xx_end_irq(struct irq_data *d) |
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{ |
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mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d); |
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out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask); |
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} |
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static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type) |
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{ |
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/* only external IRQ senses are programmable */ |
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if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !(irqd_to_hwirq(d) & 1)) { |
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unsigned int siel = in_be32(&siu_reg->sc_siel); |
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siel |= mpc8xx_irqd_to_bit(d); |
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out_be32(&siu_reg->sc_siel, siel); |
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irq_set_handler_locked(d, handle_edge_irq); |
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} |
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return 0; |
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} |
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static struct irq_chip mpc8xx_pic = { |
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.name = "8XX SIU", |
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.irq_unmask = mpc8xx_unmask_irq, |
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.irq_mask = mpc8xx_mask_irq, |
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.irq_ack = mpc8xx_ack, |
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.irq_eoi = mpc8xx_end_irq, |
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.irq_set_type = mpc8xx_set_irq_type, |
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}; |
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unsigned int mpc8xx_get_irq(void) |
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{ |
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int irq; |
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/* For MPC8xx, read the SIVEC register and shift the bits down |
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* to get the irq number. |
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*/ |
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irq = in_be32(&siu_reg->sc_sivec) >> 26; |
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if (irq == PIC_VEC_SPURRIOUS) |
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return 0; |
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return irq_linear_revmap(mpc8xx_pic_host, irq); |
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} |
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static int mpc8xx_pic_host_map(struct irq_domain *h, unsigned int virq, |
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irq_hw_number_t hw) |
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{ |
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pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw); |
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/* Set default irq handle */ |
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irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq); |
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return 0; |
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} |
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static int mpc8xx_pic_host_xlate(struct irq_domain *h, struct device_node *ct, |
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const u32 *intspec, unsigned int intsize, |
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irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
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{ |
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static unsigned char map_pic_senses[4] = { |
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IRQ_TYPE_EDGE_RISING, |
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IRQ_TYPE_LEVEL_LOW, |
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IRQ_TYPE_LEVEL_HIGH, |
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IRQ_TYPE_EDGE_FALLING, |
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}; |
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if (intspec[0] > 0x1f) |
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return 0; |
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*out_hwirq = intspec[0]; |
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if (intsize > 1 && intspec[1] < 4) |
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*out_flags = map_pic_senses[intspec[1]]; |
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else |
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*out_flags = IRQ_TYPE_NONE; |
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return 0; |
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} |
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static const struct irq_domain_ops mpc8xx_pic_host_ops = { |
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.map = mpc8xx_pic_host_map, |
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.xlate = mpc8xx_pic_host_xlate, |
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}; |
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int __init mpc8xx_pic_init(void) |
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{ |
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struct resource res; |
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struct device_node *np; |
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int ret; |
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np = of_find_compatible_node(NULL, NULL, "fsl,pq1-pic"); |
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if (np == NULL) |
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np = of_find_node_by_type(NULL, "mpc8xx-pic"); |
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if (np == NULL) { |
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printk(KERN_ERR "Could not find fsl,pq1-pic node\n"); |
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return -ENOMEM; |
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} |
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ret = of_address_to_resource(np, 0, &res); |
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if (ret) |
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goto out; |
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siu_reg = ioremap(res.start, resource_size(&res)); |
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if (siu_reg == NULL) { |
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ret = -EINVAL; |
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goto out; |
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} |
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mpc8xx_pic_host = irq_domain_add_linear(np, 64, &mpc8xx_pic_host_ops, NULL); |
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if (mpc8xx_pic_host == NULL) { |
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printk(KERN_ERR "MPC8xx PIC: failed to allocate irq host!\n"); |
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ret = -ENOMEM; |
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} |
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ret = 0; |
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out: |
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of_node_put(np); |
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return ret; |
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}
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