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428 lines
12 KiB
428 lines
12 KiB
/* |
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* PCI code for the Freescale MPC52xx embedded CPU. |
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* |
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* Copyright (C) 2006 Secret Lab Technologies Ltd. |
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* Grant Likely <[email protected]> |
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* Copyright (C) 2004 Sylvain Munaut <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public License |
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* version 2. This program is licensed "as is" without any warranty of any |
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* kind, whether express or implied. |
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*/ |
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#undef DEBUG |
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#include <linux/pci.h> |
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#include <asm/mpc52xx.h> |
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#include <asm/delay.h> |
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#include <asm/machdep.h> |
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#include <linux/kernel.h> |
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/* ======================================================================== */ |
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/* Structures mapping & Defines for PCI Unit */ |
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/* ======================================================================== */ |
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#define MPC52xx_PCI_GSCR_BM 0x40000000 |
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#define MPC52xx_PCI_GSCR_PE 0x20000000 |
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#define MPC52xx_PCI_GSCR_SE 0x10000000 |
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#define MPC52xx_PCI_GSCR_XLB2PCI_MASK 0x07000000 |
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#define MPC52xx_PCI_GSCR_XLB2PCI_SHIFT 24 |
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#define MPC52xx_PCI_GSCR_IPG2PCI_MASK 0x00070000 |
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#define MPC52xx_PCI_GSCR_IPG2PCI_SHIFT 16 |
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#define MPC52xx_PCI_GSCR_BME 0x00004000 |
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#define MPC52xx_PCI_GSCR_PEE 0x00002000 |
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#define MPC52xx_PCI_GSCR_SEE 0x00001000 |
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#define MPC52xx_PCI_GSCR_PR 0x00000001 |
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#define MPC52xx_PCI_IWBTAR_TRANSLATION(proc_ad,pci_ad,size) \ |
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( ( (proc_ad) & 0xff000000 ) | \ |
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( (((size) - 1) >> 8) & 0x00ff0000 ) | \ |
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( ((pci_ad) >> 16) & 0x0000ff00 ) ) |
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#define MPC52xx_PCI_IWCR_PACK(win0,win1,win2) (((win0) << 24) | \ |
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((win1) << 16) | \ |
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((win2) << 8)) |
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#define MPC52xx_PCI_IWCR_DISABLE 0x0 |
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#define MPC52xx_PCI_IWCR_ENABLE 0x1 |
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#define MPC52xx_PCI_IWCR_READ 0x0 |
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#define MPC52xx_PCI_IWCR_READ_LINE 0x2 |
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#define MPC52xx_PCI_IWCR_READ_MULTI 0x4 |
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#define MPC52xx_PCI_IWCR_MEM 0x0 |
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#define MPC52xx_PCI_IWCR_IO 0x8 |
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#define MPC52xx_PCI_TCR_P 0x01000000 |
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#define MPC52xx_PCI_TCR_LD 0x00010000 |
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#define MPC52xx_PCI_TCR_WCT8 0x00000008 |
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#define MPC52xx_PCI_TBATR_DISABLE 0x0 |
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#define MPC52xx_PCI_TBATR_ENABLE 0x1 |
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struct mpc52xx_pci { |
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u32 idr; /* PCI + 0x00 */ |
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u32 scr; /* PCI + 0x04 */ |
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u32 ccrir; /* PCI + 0x08 */ |
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u32 cr1; /* PCI + 0x0C */ |
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u32 bar0; /* PCI + 0x10 */ |
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u32 bar1; /* PCI + 0x14 */ |
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u8 reserved1[16]; /* PCI + 0x18 */ |
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u32 ccpr; /* PCI + 0x28 */ |
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u32 sid; /* PCI + 0x2C */ |
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u32 erbar; /* PCI + 0x30 */ |
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u32 cpr; /* PCI + 0x34 */ |
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u8 reserved2[4]; /* PCI + 0x38 */ |
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u32 cr2; /* PCI + 0x3C */ |
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u8 reserved3[32]; /* PCI + 0x40 */ |
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u32 gscr; /* PCI + 0x60 */ |
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u32 tbatr0; /* PCI + 0x64 */ |
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u32 tbatr1; /* PCI + 0x68 */ |
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u32 tcr; /* PCI + 0x6C */ |
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u32 iw0btar; /* PCI + 0x70 */ |
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u32 iw1btar; /* PCI + 0x74 */ |
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u32 iw2btar; /* PCI + 0x78 */ |
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u8 reserved4[4]; /* PCI + 0x7C */ |
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u32 iwcr; /* PCI + 0x80 */ |
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u32 icr; /* PCI + 0x84 */ |
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u32 isr; /* PCI + 0x88 */ |
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u32 arb; /* PCI + 0x8C */ |
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u8 reserved5[104]; /* PCI + 0x90 */ |
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u32 car; /* PCI + 0xF8 */ |
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u8 reserved6[4]; /* PCI + 0xFC */ |
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}; |
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/* MPC5200 device tree match tables */ |
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const struct of_device_id mpc52xx_pci_ids[] __initconst = { |
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{ .type = "pci", .compatible = "fsl,mpc5200-pci", }, |
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{ .type = "pci", .compatible = "mpc5200-pci", }, |
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{} |
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}; |
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/* ======================================================================== */ |
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/* PCI configuration access */ |
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/* ======================================================================== */ |
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static int |
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mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, |
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int offset, int len, u32 *val) |
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{ |
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struct pci_controller *hose = pci_bus_to_host(bus); |
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u32 value; |
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if (ppc_md.pci_exclude_device) |
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if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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out_be32(hose->cfg_addr, |
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(1 << 31) | |
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(bus->number << 16) | |
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(devfn << 8) | |
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(offset & 0xfc)); |
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mb(); |
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#if defined(CONFIG_PPC_MPC5200_BUGFIX) |
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if (bus->number) { |
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/* workaround for the bug 435 of the MPC5200 (L25R); |
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* Don't do 32 bits config access during type-1 cycles */ |
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switch (len) { |
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case 1: |
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value = in_8(((u8 __iomem *)hose->cfg_data) + |
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(offset & 3)); |
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break; |
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case 2: |
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value = in_le16(((u16 __iomem *)hose->cfg_data) + |
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((offset>>1) & 1)); |
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break; |
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default: |
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value = in_le16((u16 __iomem *)hose->cfg_data) | |
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(in_le16(((u16 __iomem *)hose->cfg_data) + 1) << 16); |
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break; |
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} |
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} |
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else |
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#endif |
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{ |
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value = in_le32(hose->cfg_data); |
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if (len != 4) { |
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value >>= ((offset & 0x3) << 3); |
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value &= 0xffffffff >> (32 - (len << 3)); |
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} |
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} |
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*val = value; |
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out_be32(hose->cfg_addr, 0); |
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mb(); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int |
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mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, |
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int offset, int len, u32 val) |
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{ |
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struct pci_controller *hose = pci_bus_to_host(bus); |
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u32 value, mask; |
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if (ppc_md.pci_exclude_device) |
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if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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out_be32(hose->cfg_addr, |
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(1 << 31) | |
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(bus->number << 16) | |
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(devfn << 8) | |
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(offset & 0xfc)); |
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mb(); |
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#if defined(CONFIG_PPC_MPC5200_BUGFIX) |
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if (bus->number) { |
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/* workaround for the bug 435 of the MPC5200 (L25R); |
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* Don't do 32 bits config access during type-1 cycles */ |
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switch (len) { |
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case 1: |
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out_8(((u8 __iomem *)hose->cfg_data) + |
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(offset & 3), val); |
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break; |
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case 2: |
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out_le16(((u16 __iomem *)hose->cfg_data) + |
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((offset>>1) & 1), val); |
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break; |
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default: |
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out_le16((u16 __iomem *)hose->cfg_data, |
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(u16)val); |
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out_le16(((u16 __iomem *)hose->cfg_data) + 1, |
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(u16)(val>>16)); |
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break; |
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} |
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} |
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else |
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#endif |
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{ |
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if (len != 4) { |
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value = in_le32(hose->cfg_data); |
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offset = (offset & 0x3) << 3; |
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mask = (0xffffffff >> (32 - (len << 3))); |
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mask <<= offset; |
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value &= ~mask; |
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val = value | ((val << offset) & mask); |
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} |
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out_le32(hose->cfg_data, val); |
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} |
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mb(); |
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out_be32(hose->cfg_addr, 0); |
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mb(); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static struct pci_ops mpc52xx_pci_ops = { |
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.read = mpc52xx_pci_read_config, |
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.write = mpc52xx_pci_write_config |
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}; |
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/* ======================================================================== */ |
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/* PCI setup */ |
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/* ======================================================================== */ |
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static void __init |
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mpc52xx_pci_setup(struct pci_controller *hose, |
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struct mpc52xx_pci __iomem *pci_regs, phys_addr_t pci_phys) |
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{ |
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struct resource *res; |
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u32 tmp; |
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int iwcr0 = 0, iwcr1 = 0, iwcr2 = 0; |
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pr_debug("mpc52xx_pci_setup(hose=%p, pci_regs=%p)\n", hose, pci_regs); |
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/* pci_process_bridge_OF_ranges() found all our addresses for us; |
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* now store them in the right places */ |
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hose->cfg_addr = &pci_regs->car; |
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hose->cfg_data = hose->io_base_virt; |
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/* Control regs */ |
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tmp = in_be32(&pci_regs->scr); |
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tmp |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
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out_be32(&pci_regs->scr, tmp); |
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/* Memory windows */ |
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res = &hose->mem_resources[0]; |
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if (res->flags) { |
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pr_debug("mem_resource[0] = " |
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"{.start=%llx, .end=%llx, .flags=%llx}\n", |
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(unsigned long long)res->start, |
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(unsigned long long)res->end, |
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(unsigned long long)res->flags); |
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out_be32(&pci_regs->iw0btar, |
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MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start, |
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resource_size(res))); |
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iwcr0 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_MEM; |
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if (res->flags & IORESOURCE_PREFETCH) |
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iwcr0 |= MPC52xx_PCI_IWCR_READ_MULTI; |
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else |
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iwcr0 |= MPC52xx_PCI_IWCR_READ; |
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} |
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res = &hose->mem_resources[1]; |
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if (res->flags) { |
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pr_debug("mem_resource[1] = {.start=%x, .end=%x, .flags=%lx}\n", |
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res->start, res->end, res->flags); |
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out_be32(&pci_regs->iw1btar, |
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MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start, |
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resource_size(res))); |
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iwcr1 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_MEM; |
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if (res->flags & IORESOURCE_PREFETCH) |
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iwcr1 |= MPC52xx_PCI_IWCR_READ_MULTI; |
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else |
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iwcr1 |= MPC52xx_PCI_IWCR_READ; |
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} |
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/* IO resources */ |
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res = &hose->io_resource; |
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if (!res) { |
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printk(KERN_ERR "%s: Didn't find IO resources\n", __FILE__); |
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return; |
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} |
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pr_debug(".io_resource={.start=%llx,.end=%llx,.flags=%llx} " |
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".io_base_phys=0x%p\n", |
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(unsigned long long)res->start, |
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(unsigned long long)res->end, |
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(unsigned long long)res->flags, (void*)hose->io_base_phys); |
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out_be32(&pci_regs->iw2btar, |
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MPC52xx_PCI_IWBTAR_TRANSLATION(hose->io_base_phys, |
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res->start, |
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resource_size(res))); |
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iwcr2 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_IO; |
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/* Set all the IWCR fields at once; they're in the same reg */ |
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out_be32(&pci_regs->iwcr, MPC52xx_PCI_IWCR_PACK(iwcr0, iwcr1, iwcr2)); |
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/* Map IMMR onto PCI bus */ |
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pci_phys &= 0xfffc0000; /* bar0 has only 14 significant bits */ |
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out_be32(&pci_regs->tbatr0, MPC52xx_PCI_TBATR_ENABLE | pci_phys); |
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out_be32(&pci_regs->bar0, PCI_BASE_ADDRESS_MEM_PREFETCH | pci_phys); |
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/* Map memory onto PCI bus */ |
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out_be32(&pci_regs->tbatr1, MPC52xx_PCI_TBATR_ENABLE); |
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out_be32(&pci_regs->bar1, PCI_BASE_ADDRESS_MEM_PREFETCH); |
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out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD | MPC52xx_PCI_TCR_WCT8); |
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tmp = in_be32(&pci_regs->gscr); |
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#if 0 |
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/* Reset the exteral bus ( internal PCI controller is NOT reset ) */ |
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/* Not necessary and can be a bad thing if for example the bootloader |
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is displaying a splash screen or ... Just left here for |
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documentation purpose if anyone need it */ |
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out_be32(&pci_regs->gscr, tmp | MPC52xx_PCI_GSCR_PR); |
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udelay(50); |
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#endif |
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/* Make sure the PCI bridge is out of reset */ |
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out_be32(&pci_regs->gscr, tmp & ~MPC52xx_PCI_GSCR_PR); |
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} |
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static void |
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mpc52xx_pci_fixup_resources(struct pci_dev *dev) |
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{ |
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int i; |
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pr_debug("mpc52xx_pci_fixup_resources() %.4x:%.4x\n", |
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dev->vendor, dev->device); |
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/* We don't rely on boot loader for PCI and resets all |
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devices */ |
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
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struct resource *res = &dev->resource[i]; |
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if (res->end > res->start) { /* Only valid resources */ |
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res->end -= res->start; |
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res->start = 0; |
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res->flags |= IORESOURCE_UNSET; |
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} |
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} |
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/* The PCI Host bridge of MPC52xx has a prefetch memory resource |
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fixed to 1Gb. Doesn't fit in the resource system so we remove it */ |
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if ( (dev->vendor == PCI_VENDOR_ID_MOTOROLA) && |
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( dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200 |
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|| dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200B) ) { |
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struct resource *res = &dev->resource[1]; |
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res->start = res->end = res->flags = 0; |
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} |
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} |
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int __init |
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mpc52xx_add_bridge(struct device_node *node) |
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{ |
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int len; |
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struct mpc52xx_pci __iomem *pci_regs; |
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struct pci_controller *hose; |
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const int *bus_range; |
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struct resource rsrc; |
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pr_debug("Adding MPC52xx PCI host bridge %pOF\n", node); |
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pci_add_flags(PCI_REASSIGN_ALL_BUS); |
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if (of_address_to_resource(node, 0, &rsrc) != 0) { |
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printk(KERN_ERR "Can't get %pOF resources\n", node); |
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return -EINVAL; |
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} |
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bus_range = of_get_property(node, "bus-range", &len); |
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if (bus_range == NULL || len < 2 * sizeof(int)) { |
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printk(KERN_WARNING "Can't get %pOF bus-range, assume bus 0\n", |
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node); |
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bus_range = NULL; |
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} |
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/* There are some PCI quirks on the 52xx, register the hook to |
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* fix them. */ |
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ppc_md.pcibios_fixup_resources = mpc52xx_pci_fixup_resources; |
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/* Alloc and initialize the pci controller. Values in the device |
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* tree are needed to configure the 52xx PCI controller. Rather |
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* than parse the tree here, let pci_process_bridge_OF_ranges() |
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* do it for us and extract the values after the fact */ |
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hose = pcibios_alloc_controller(node); |
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if (!hose) |
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return -ENOMEM; |
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hose->first_busno = bus_range ? bus_range[0] : 0; |
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hose->last_busno = bus_range ? bus_range[1] : 0xff; |
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hose->ops = &mpc52xx_pci_ops; |
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pci_regs = ioremap(rsrc.start, resource_size(&rsrc)); |
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if (!pci_regs) |
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return -ENOMEM; |
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pci_process_bridge_OF_ranges(hose, node, 1); |
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/* Finish setting up PCI using values obtained by |
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* pci_proces_bridge_OF_ranges */ |
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mpc52xx_pci_setup(hose, pci_regs, rsrc.start); |
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return 0; |
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} |
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void __init mpc52xx_setup_pci(void) |
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{ |
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struct device_node *pci; |
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pci = of_find_matching_node(NULL, mpc52xx_pci_ids); |
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if (!pci) |
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return; |
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mpc52xx_add_bridge(pci); |
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of_node_put(pci); |
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}
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