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1108 lines
33 KiB
1108 lines
33 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* eBPF JIT compiler for PPC32 |
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* |
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* Copyright 2020 Christophe Leroy <[email protected]> |
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* CS GROUP France |
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* |
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* Based on PPC64 eBPF JIT compiler by Naveen N. Rao |
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*/ |
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#include <linux/moduleloader.h> |
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#include <asm/cacheflush.h> |
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#include <asm/asm-compat.h> |
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#include <linux/netdevice.h> |
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#include <linux/filter.h> |
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#include <linux/if_vlan.h> |
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#include <asm/kprobes.h> |
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#include <linux/bpf.h> |
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|
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#include "bpf_jit.h" |
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|
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/* |
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* Stack layout: |
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* |
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* [ prev sp ] <------------- |
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* [ nv gpr save area ] 16 * 4 | |
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* fp (r31) --> [ ebpf stack space ] upto 512 | |
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* [ frame header ] 16 | |
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* sp (r1) ---> [ stack pointer ] -------------- |
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*/ |
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|
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/* for gpr non volatile registers r17 to r31 (14) + tail call */ |
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#define BPF_PPC_STACK_SAVE (15 * 4 + 4) |
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/* stack frame, ensure this is quadword aligned */ |
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#define BPF_PPC_STACKFRAME(ctx) (STACK_FRAME_MIN_SIZE + BPF_PPC_STACK_SAVE + (ctx)->stack_size) |
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|
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/* BPF register usage */ |
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#define TMP_REG (MAX_BPF_JIT_REG + 0) |
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|
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/* BPF to ppc register mappings */ |
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const int b2p[MAX_BPF_JIT_REG + 1] = { |
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/* function return value */ |
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[BPF_REG_0] = 12, |
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/* function arguments */ |
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[BPF_REG_1] = 4, |
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[BPF_REG_2] = 6, |
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[BPF_REG_3] = 8, |
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[BPF_REG_4] = 10, |
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[BPF_REG_5] = 22, |
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/* non volatile registers */ |
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[BPF_REG_6] = 24, |
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[BPF_REG_7] = 26, |
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[BPF_REG_8] = 28, |
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[BPF_REG_9] = 30, |
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/* frame pointer aka BPF_REG_10 */ |
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[BPF_REG_FP] = 18, |
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/* eBPF jit internal registers */ |
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[BPF_REG_AX] = 20, |
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[TMP_REG] = 31, /* 32 bits */ |
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}; |
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|
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static int bpf_to_ppc(struct codegen_context *ctx, int reg) |
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{ |
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return ctx->b2p[reg]; |
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} |
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|
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/* PPC NVR range -- update this if we ever use NVRs below r17 */ |
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#define BPF_PPC_NVR_MIN 17 |
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#define BPF_PPC_TC 16 |
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|
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static int bpf_jit_stack_offsetof(struct codegen_context *ctx, int reg) |
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{ |
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if ((reg >= BPF_PPC_NVR_MIN && reg < 32) || reg == BPF_PPC_TC) |
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return BPF_PPC_STACKFRAME(ctx) - 4 * (32 - reg); |
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|
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WARN(true, "BPF JIT is asking about unknown registers, will crash the stack"); |
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/* Use the hole we have left for alignment */ |
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return BPF_PPC_STACKFRAME(ctx) - 4; |
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} |
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|
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void bpf_jit_realloc_regs(struct codegen_context *ctx) |
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{ |
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if (ctx->seen & SEEN_FUNC) |
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return; |
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|
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while (ctx->seen & SEEN_NVREG_MASK && |
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(ctx->seen & SEEN_VREG_MASK) != SEEN_VREG_MASK) { |
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int old = 32 - fls(ctx->seen & (SEEN_NVREG_MASK & 0xaaaaaaab)); |
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int new = 32 - fls(~ctx->seen & (SEEN_VREG_MASK & 0xaaaaaaaa)); |
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int i; |
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|
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for (i = BPF_REG_0; i <= TMP_REG; i++) { |
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if (ctx->b2p[i] != old) |
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continue; |
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ctx->b2p[i] = new; |
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bpf_set_seen_register(ctx, new); |
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bpf_clear_seen_register(ctx, old); |
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if (i != TMP_REG) { |
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bpf_set_seen_register(ctx, new - 1); |
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bpf_clear_seen_register(ctx, old - 1); |
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} |
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break; |
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} |
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} |
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} |
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|
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void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx) |
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{ |
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int i; |
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|
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/* First arg comes in as a 32 bits pointer. */ |
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EMIT(PPC_RAW_MR(bpf_to_ppc(ctx, BPF_REG_1), _R3)); |
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EMIT(PPC_RAW_LI(bpf_to_ppc(ctx, BPF_REG_1) - 1, 0)); |
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EMIT(PPC_RAW_STWU(_R1, _R1, -BPF_PPC_STACKFRAME(ctx))); |
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|
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/* |
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* Initialize tail_call_cnt in stack frame if we do tail calls. |
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* Otherwise, put in NOPs so that it can be skipped when we are |
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* invoked through a tail call. |
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*/ |
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if (ctx->seen & SEEN_TAILCALL) |
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EMIT(PPC_RAW_STW(bpf_to_ppc(ctx, BPF_REG_1) - 1, _R1, |
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bpf_jit_stack_offsetof(ctx, BPF_PPC_TC))); |
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else |
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EMIT(PPC_RAW_NOP()); |
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|
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#define BPF_TAILCALL_PROLOGUE_SIZE 16 |
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|
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/* |
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* We need a stack frame, but we don't necessarily need to |
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* save/restore LR unless we call other functions |
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*/ |
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if (ctx->seen & SEEN_FUNC) |
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EMIT(PPC_RAW_MFLR(_R0)); |
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|
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/* |
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* Back up non-volatile regs -- registers r18-r31 |
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*/ |
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for (i = BPF_PPC_NVR_MIN; i <= 31; i++) |
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if (bpf_is_seen_register(ctx, i)) |
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EMIT(PPC_RAW_STW(i, _R1, bpf_jit_stack_offsetof(ctx, i))); |
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|
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/* If needed retrieve arguments 9 and 10, ie 5th 64 bits arg.*/ |
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if (bpf_is_seen_register(ctx, bpf_to_ppc(ctx, BPF_REG_5))) { |
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EMIT(PPC_RAW_LWZ(bpf_to_ppc(ctx, BPF_REG_5) - 1, _R1, BPF_PPC_STACKFRAME(ctx)) + 8); |
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EMIT(PPC_RAW_LWZ(bpf_to_ppc(ctx, BPF_REG_5), _R1, BPF_PPC_STACKFRAME(ctx)) + 12); |
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} |
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|
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/* Setup frame pointer to point to the bpf stack area */ |
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if (bpf_is_seen_register(ctx, bpf_to_ppc(ctx, BPF_REG_FP))) { |
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EMIT(PPC_RAW_LI(bpf_to_ppc(ctx, BPF_REG_FP) - 1, 0)); |
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EMIT(PPC_RAW_ADDI(bpf_to_ppc(ctx, BPF_REG_FP), _R1, |
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STACK_FRAME_MIN_SIZE + ctx->stack_size)); |
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} |
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|
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if (ctx->seen & SEEN_FUNC) |
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EMIT(PPC_RAW_STW(_R0, _R1, BPF_PPC_STACKFRAME(ctx) + PPC_LR_STKOFF)); |
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} |
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|
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static void bpf_jit_emit_common_epilogue(u32 *image, struct codegen_context *ctx) |
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{ |
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int i; |
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|
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/* Restore NVRs */ |
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for (i = BPF_PPC_NVR_MIN; i <= 31; i++) |
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if (bpf_is_seen_register(ctx, i)) |
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EMIT(PPC_RAW_LWZ(i, _R1, bpf_jit_stack_offsetof(ctx, i))); |
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} |
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|
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void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx) |
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{ |
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EMIT(PPC_RAW_MR(_R3, bpf_to_ppc(ctx, BPF_REG_0))); |
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|
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bpf_jit_emit_common_epilogue(image, ctx); |
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|
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/* Tear down our stack frame */ |
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if (ctx->seen & SEEN_FUNC) |
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EMIT(PPC_RAW_LWZ(_R0, _R1, BPF_PPC_STACKFRAME(ctx) + PPC_LR_STKOFF)); |
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EMIT(PPC_RAW_ADDI(_R1, _R1, BPF_PPC_STACKFRAME(ctx))); |
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if (ctx->seen & SEEN_FUNC) |
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EMIT(PPC_RAW_MTLR(_R0)); |
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|
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EMIT(PPC_RAW_BLR()); |
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} |
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|
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void bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 func) |
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{ |
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s32 rel = (s32)func - (s32)(image + ctx->idx); |
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|
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if (image && rel < 0x2000000 && rel >= -0x2000000) { |
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PPC_BL_ABS(func); |
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} else { |
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/* Load function address into r0 */ |
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EMIT(PPC_RAW_LIS(_R0, IMM_H(func))); |
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EMIT(PPC_RAW_ORI(_R0, _R0, IMM_L(func))); |
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EMIT(PPC_RAW_MTCTR(_R0)); |
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EMIT(PPC_RAW_BCTRL()); |
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} |
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} |
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|
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static void bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 out) |
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{ |
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/* |
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* By now, the eBPF program has already setup parameters in r3-r6 |
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* r3-r4/BPF_REG_1 - pointer to ctx -- passed as is to the next bpf program |
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* r5-r6/BPF_REG_2 - pointer to bpf_array |
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* r7-r8/BPF_REG_3 - index in bpf_array |
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*/ |
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int b2p_bpf_array = bpf_to_ppc(ctx, BPF_REG_2); |
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int b2p_index = bpf_to_ppc(ctx, BPF_REG_3); |
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|
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/* |
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* if (index >= array->map.max_entries) |
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* goto out; |
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*/ |
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EMIT(PPC_RAW_LWZ(_R0, b2p_bpf_array, offsetof(struct bpf_array, map.max_entries))); |
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EMIT(PPC_RAW_CMPLW(b2p_index, _R0)); |
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EMIT(PPC_RAW_LWZ(_R0, _R1, bpf_jit_stack_offsetof(ctx, BPF_PPC_TC))); |
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PPC_BCC(COND_GE, out); |
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|
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/* |
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* if (tail_call_cnt > MAX_TAIL_CALL_CNT) |
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* goto out; |
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*/ |
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EMIT(PPC_RAW_CMPLWI(_R0, MAX_TAIL_CALL_CNT)); |
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/* tail_call_cnt++; */ |
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EMIT(PPC_RAW_ADDIC(_R0, _R0, 1)); |
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PPC_BCC(COND_GT, out); |
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|
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/* prog = array->ptrs[index]; */ |
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EMIT(PPC_RAW_RLWINM(_R3, b2p_index, 2, 0, 29)); |
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EMIT(PPC_RAW_ADD(_R3, _R3, b2p_bpf_array)); |
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EMIT(PPC_RAW_LWZ(_R3, _R3, offsetof(struct bpf_array, ptrs))); |
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EMIT(PPC_RAW_STW(_R0, _R1, bpf_jit_stack_offsetof(ctx, BPF_PPC_TC))); |
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|
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/* |
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* if (prog == NULL) |
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* goto out; |
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*/ |
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EMIT(PPC_RAW_CMPLWI(_R3, 0)); |
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PPC_BCC(COND_EQ, out); |
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|
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/* goto *(prog->bpf_func + prologue_size); */ |
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EMIT(PPC_RAW_LWZ(_R3, _R3, offsetof(struct bpf_prog, bpf_func))); |
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if (ctx->seen & SEEN_FUNC) |
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EMIT(PPC_RAW_LWZ(_R0, _R1, BPF_PPC_STACKFRAME(ctx) + PPC_LR_STKOFF)); |
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EMIT(PPC_RAW_ADDIC(_R3, _R3, BPF_TAILCALL_PROLOGUE_SIZE)); |
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if (ctx->seen & SEEN_FUNC) |
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EMIT(PPC_RAW_MTLR(_R0)); |
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EMIT(PPC_RAW_MTCTR(_R3)); |
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EMIT(PPC_RAW_MR(_R3, bpf_to_ppc(ctx, BPF_REG_1))); |
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/* tear restore NVRs, ... */ |
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bpf_jit_emit_common_epilogue(image, ctx); |
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EMIT(PPC_RAW_BCTR()); |
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/* out: */ |
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} |
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|
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/* Assemble the body code between the prologue & epilogue */ |
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int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *ctx, |
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u32 *addrs, bool extra_pass) |
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{ |
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const struct bpf_insn *insn = fp->insnsi; |
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int flen = fp->len; |
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int i, ret; |
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|
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/* Start of epilogue code - will only be valid 2nd pass onwards */ |
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u32 exit_addr = addrs[flen]; |
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for (i = 0; i < flen; i++) { |
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u32 code = insn[i].code; |
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u32 dst_reg = bpf_to_ppc(ctx, insn[i].dst_reg); |
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u32 dst_reg_h = dst_reg - 1; |
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u32 src_reg = bpf_to_ppc(ctx, insn[i].src_reg); |
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u32 src_reg_h = src_reg - 1; |
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u32 tmp_reg = bpf_to_ppc(ctx, TMP_REG); |
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s16 off = insn[i].off; |
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s32 imm = insn[i].imm; |
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bool func_addr_fixed; |
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u64 func_addr; |
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u32 true_cond; |
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|
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/* |
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* addrs[] maps a BPF bytecode address into a real offset from |
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* the start of the body code. |
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*/ |
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addrs[i] = ctx->idx * 4; |
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|
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/* |
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* As an optimization, we note down which registers |
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* are used so that we can only save/restore those in our |
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* prologue and epilogue. We do this here regardless of whether |
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* the actual BPF instruction uses src/dst registers or not |
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* (for instance, BPF_CALL does not use them). The expectation |
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* is that those instructions will have src_reg/dst_reg set to |
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* 0. Even otherwise, we just lose some prologue/epilogue |
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* optimization but everything else should work without |
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* any issues. |
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*/ |
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if (dst_reg >= 3 && dst_reg < 32) { |
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bpf_set_seen_register(ctx, dst_reg); |
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bpf_set_seen_register(ctx, dst_reg_h); |
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} |
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|
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if (src_reg >= 3 && src_reg < 32) { |
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bpf_set_seen_register(ctx, src_reg); |
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bpf_set_seen_register(ctx, src_reg_h); |
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} |
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|
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switch (code) { |
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/* |
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* Arithmetic operations: ADD/SUB/MUL/DIV/MOD/NEG |
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*/ |
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case BPF_ALU | BPF_ADD | BPF_X: /* (u32) dst += (u32) src */ |
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EMIT(PPC_RAW_ADD(dst_reg, dst_reg, src_reg)); |
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break; |
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case BPF_ALU64 | BPF_ADD | BPF_X: /* dst += src */ |
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EMIT(PPC_RAW_ADDC(dst_reg, dst_reg, src_reg)); |
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EMIT(PPC_RAW_ADDE(dst_reg_h, dst_reg_h, src_reg_h)); |
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break; |
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case BPF_ALU | BPF_SUB | BPF_X: /* (u32) dst -= (u32) src */ |
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EMIT(PPC_RAW_SUB(dst_reg, dst_reg, src_reg)); |
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break; |
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case BPF_ALU64 | BPF_SUB | BPF_X: /* dst -= src */ |
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EMIT(PPC_RAW_SUBFC(dst_reg, src_reg, dst_reg)); |
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EMIT(PPC_RAW_SUBFE(dst_reg_h, src_reg_h, dst_reg_h)); |
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break; |
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case BPF_ALU | BPF_SUB | BPF_K: /* (u32) dst -= (u32) imm */ |
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imm = -imm; |
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fallthrough; |
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case BPF_ALU | BPF_ADD | BPF_K: /* (u32) dst += (u32) imm */ |
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if (IMM_HA(imm) & 0xffff) |
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EMIT(PPC_RAW_ADDIS(dst_reg, dst_reg, IMM_HA(imm))); |
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if (IMM_L(imm)) |
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EMIT(PPC_RAW_ADDI(dst_reg, dst_reg, IMM_L(imm))); |
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break; |
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case BPF_ALU64 | BPF_SUB | BPF_K: /* dst -= imm */ |
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imm = -imm; |
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fallthrough; |
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case BPF_ALU64 | BPF_ADD | BPF_K: /* dst += imm */ |
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if (!imm) |
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break; |
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|
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if (imm >= -32768 && imm < 32768) { |
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EMIT(PPC_RAW_ADDIC(dst_reg, dst_reg, imm)); |
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} else { |
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PPC_LI32(_R0, imm); |
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EMIT(PPC_RAW_ADDC(dst_reg, dst_reg, _R0)); |
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} |
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if (imm >= 0) |
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EMIT(PPC_RAW_ADDZE(dst_reg_h, dst_reg_h)); |
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else |
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EMIT(PPC_RAW_ADDME(dst_reg_h, dst_reg_h)); |
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break; |
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case BPF_ALU64 | BPF_MUL | BPF_X: /* dst *= src */ |
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bpf_set_seen_register(ctx, tmp_reg); |
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EMIT(PPC_RAW_MULW(_R0, dst_reg, src_reg_h)); |
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EMIT(PPC_RAW_MULW(dst_reg_h, dst_reg_h, src_reg)); |
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EMIT(PPC_RAW_MULHWU(tmp_reg, dst_reg, src_reg)); |
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EMIT(PPC_RAW_MULW(dst_reg, dst_reg, src_reg)); |
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EMIT(PPC_RAW_ADD(dst_reg_h, dst_reg_h, _R0)); |
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EMIT(PPC_RAW_ADD(dst_reg_h, dst_reg_h, tmp_reg)); |
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break; |
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case BPF_ALU | BPF_MUL | BPF_X: /* (u32) dst *= (u32) src */ |
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EMIT(PPC_RAW_MULW(dst_reg, dst_reg, src_reg)); |
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break; |
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case BPF_ALU | BPF_MUL | BPF_K: /* (u32) dst *= (u32) imm */ |
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if (imm >= -32768 && imm < 32768) { |
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EMIT(PPC_RAW_MULI(dst_reg, dst_reg, imm)); |
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} else { |
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PPC_LI32(_R0, imm); |
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EMIT(PPC_RAW_MULW(dst_reg, dst_reg, _R0)); |
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} |
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break; |
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case BPF_ALU64 | BPF_MUL | BPF_K: /* dst *= imm */ |
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if (!imm) { |
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PPC_LI32(dst_reg, 0); |
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PPC_LI32(dst_reg_h, 0); |
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break; |
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} |
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if (imm == 1) |
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break; |
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if (imm == -1) { |
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EMIT(PPC_RAW_SUBFIC(dst_reg, dst_reg, 0)); |
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EMIT(PPC_RAW_SUBFZE(dst_reg_h, dst_reg_h)); |
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break; |
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} |
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bpf_set_seen_register(ctx, tmp_reg); |
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PPC_LI32(tmp_reg, imm); |
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EMIT(PPC_RAW_MULW(dst_reg_h, dst_reg_h, tmp_reg)); |
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if (imm < 0) |
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EMIT(PPC_RAW_SUB(dst_reg_h, dst_reg_h, dst_reg)); |
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EMIT(PPC_RAW_MULHWU(_R0, dst_reg, tmp_reg)); |
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EMIT(PPC_RAW_MULW(dst_reg, dst_reg, tmp_reg)); |
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EMIT(PPC_RAW_ADD(dst_reg_h, dst_reg_h, _R0)); |
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break; |
|
case BPF_ALU | BPF_DIV | BPF_X: /* (u32) dst /= (u32) src */ |
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EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, src_reg)); |
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break; |
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case BPF_ALU | BPF_MOD | BPF_X: /* (u32) dst %= (u32) src */ |
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EMIT(PPC_RAW_DIVWU(_R0, dst_reg, src_reg)); |
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EMIT(PPC_RAW_MULW(_R0, src_reg, _R0)); |
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EMIT(PPC_RAW_SUB(dst_reg, dst_reg, _R0)); |
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break; |
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case BPF_ALU64 | BPF_DIV | BPF_X: /* dst /= src */ |
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return -EOPNOTSUPP; |
|
case BPF_ALU64 | BPF_MOD | BPF_X: /* dst %= src */ |
|
return -EOPNOTSUPP; |
|
case BPF_ALU | BPF_DIV | BPF_K: /* (u32) dst /= (u32) imm */ |
|
if (!imm) |
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return -EINVAL; |
|
if (imm == 1) |
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break; |
|
|
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PPC_LI32(_R0, imm); |
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EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, _R0)); |
|
break; |
|
case BPF_ALU | BPF_MOD | BPF_K: /* (u32) dst %= (u32) imm */ |
|
if (!imm) |
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return -EINVAL; |
|
|
|
if (!is_power_of_2((u32)imm)) { |
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bpf_set_seen_register(ctx, tmp_reg); |
|
PPC_LI32(tmp_reg, imm); |
|
EMIT(PPC_RAW_DIVWU(_R0, dst_reg, tmp_reg)); |
|
EMIT(PPC_RAW_MULW(_R0, tmp_reg, _R0)); |
|
EMIT(PPC_RAW_SUB(dst_reg, dst_reg, _R0)); |
|
break; |
|
} |
|
if (imm == 1) |
|
EMIT(PPC_RAW_LI(dst_reg, 0)); |
|
else |
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EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, 32 - ilog2((u32)imm), 31)); |
|
|
|
break; |
|
case BPF_ALU64 | BPF_MOD | BPF_K: /* dst %= imm */ |
|
if (!imm) |
|
return -EINVAL; |
|
if (imm < 0) |
|
imm = -imm; |
|
if (!is_power_of_2(imm)) |
|
return -EOPNOTSUPP; |
|
if (imm == 1) |
|
EMIT(PPC_RAW_LI(dst_reg, 0)); |
|
else |
|
EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, 32 - ilog2(imm), 31)); |
|
EMIT(PPC_RAW_LI(dst_reg_h, 0)); |
|
break; |
|
case BPF_ALU64 | BPF_DIV | BPF_K: /* dst /= imm */ |
|
if (!imm) |
|
return -EINVAL; |
|
if (!is_power_of_2(abs(imm))) |
|
return -EOPNOTSUPP; |
|
|
|
if (imm < 0) { |
|
EMIT(PPC_RAW_SUBFIC(dst_reg, dst_reg, 0)); |
|
EMIT(PPC_RAW_SUBFZE(dst_reg_h, dst_reg_h)); |
|
imm = -imm; |
|
} |
|
if (imm == 1) |
|
break; |
|
imm = ilog2(imm); |
|
EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 32 - imm, imm, 31)); |
|
EMIT(PPC_RAW_RLWIMI(dst_reg, dst_reg_h, 32 - imm, 0, imm - 1)); |
|
EMIT(PPC_RAW_SRAWI(dst_reg_h, dst_reg_h, imm)); |
|
break; |
|
case BPF_ALU | BPF_NEG: /* (u32) dst = -dst */ |
|
EMIT(PPC_RAW_NEG(dst_reg, dst_reg)); |
|
break; |
|
case BPF_ALU64 | BPF_NEG: /* dst = -dst */ |
|
EMIT(PPC_RAW_SUBFIC(dst_reg, dst_reg, 0)); |
|
EMIT(PPC_RAW_SUBFZE(dst_reg_h, dst_reg_h)); |
|
break; |
|
|
|
/* |
|
* Logical operations: AND/OR/XOR/[A]LSH/[A]RSH |
|
*/ |
|
case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */ |
|
EMIT(PPC_RAW_AND(dst_reg, dst_reg, src_reg)); |
|
EMIT(PPC_RAW_AND(dst_reg_h, dst_reg_h, src_reg_h)); |
|
break; |
|
case BPF_ALU | BPF_AND | BPF_X: /* (u32) dst = dst & src */ |
|
EMIT(PPC_RAW_AND(dst_reg, dst_reg, src_reg)); |
|
break; |
|
case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */ |
|
if (imm >= 0) |
|
EMIT(PPC_RAW_LI(dst_reg_h, 0)); |
|
fallthrough; |
|
case BPF_ALU | BPF_AND | BPF_K: /* (u32) dst = dst & imm */ |
|
if (!IMM_H(imm)) { |
|
EMIT(PPC_RAW_ANDI(dst_reg, dst_reg, IMM_L(imm))); |
|
} else if (!IMM_L(imm)) { |
|
EMIT(PPC_RAW_ANDIS(dst_reg, dst_reg, IMM_H(imm))); |
|
} else if (imm == (((1 << fls(imm)) - 1) ^ ((1 << (ffs(i) - 1)) - 1))) { |
|
EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, |
|
32 - fls(imm), 32 - ffs(imm))); |
|
} else { |
|
PPC_LI32(_R0, imm); |
|
EMIT(PPC_RAW_AND(dst_reg, dst_reg, _R0)); |
|
} |
|
break; |
|
case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */ |
|
EMIT(PPC_RAW_OR(dst_reg, dst_reg, src_reg)); |
|
EMIT(PPC_RAW_OR(dst_reg_h, dst_reg_h, src_reg_h)); |
|
break; |
|
case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */ |
|
EMIT(PPC_RAW_OR(dst_reg, dst_reg, src_reg)); |
|
break; |
|
case BPF_ALU64 | BPF_OR | BPF_K:/* dst = dst | imm */ |
|
/* Sign-extended */ |
|
if (imm < 0) |
|
EMIT(PPC_RAW_LI(dst_reg_h, -1)); |
|
fallthrough; |
|
case BPF_ALU | BPF_OR | BPF_K:/* dst = (u32) dst | (u32) imm */ |
|
if (IMM_L(imm)) |
|
EMIT(PPC_RAW_ORI(dst_reg, dst_reg, IMM_L(imm))); |
|
if (IMM_H(imm)) |
|
EMIT(PPC_RAW_ORIS(dst_reg, dst_reg, IMM_H(imm))); |
|
break; |
|
case BPF_ALU64 | BPF_XOR | BPF_X: /* dst ^= src */ |
|
if (dst_reg == src_reg) { |
|
EMIT(PPC_RAW_LI(dst_reg, 0)); |
|
EMIT(PPC_RAW_LI(dst_reg_h, 0)); |
|
} else { |
|
EMIT(PPC_RAW_XOR(dst_reg, dst_reg, src_reg)); |
|
EMIT(PPC_RAW_XOR(dst_reg_h, dst_reg_h, src_reg_h)); |
|
} |
|
break; |
|
case BPF_ALU | BPF_XOR | BPF_X: /* (u32) dst ^= src */ |
|
if (dst_reg == src_reg) |
|
EMIT(PPC_RAW_LI(dst_reg, 0)); |
|
else |
|
EMIT(PPC_RAW_XOR(dst_reg, dst_reg, src_reg)); |
|
break; |
|
case BPF_ALU64 | BPF_XOR | BPF_K: /* dst ^= imm */ |
|
if (imm < 0) |
|
EMIT(PPC_RAW_NOR(dst_reg_h, dst_reg_h, dst_reg_h)); |
|
fallthrough; |
|
case BPF_ALU | BPF_XOR | BPF_K: /* (u32) dst ^= (u32) imm */ |
|
if (IMM_L(imm)) |
|
EMIT(PPC_RAW_XORI(dst_reg, dst_reg, IMM_L(imm))); |
|
if (IMM_H(imm)) |
|
EMIT(PPC_RAW_XORIS(dst_reg, dst_reg, IMM_H(imm))); |
|
break; |
|
case BPF_ALU | BPF_LSH | BPF_X: /* (u32) dst <<= (u32) src */ |
|
EMIT(PPC_RAW_SLW(dst_reg, dst_reg, src_reg)); |
|
break; |
|
case BPF_ALU64 | BPF_LSH | BPF_X: /* dst <<= src; */ |
|
bpf_set_seen_register(ctx, tmp_reg); |
|
EMIT(PPC_RAW_SUBFIC(_R0, src_reg, 32)); |
|
EMIT(PPC_RAW_SLW(dst_reg_h, dst_reg_h, src_reg)); |
|
EMIT(PPC_RAW_ADDI(tmp_reg, src_reg, 32)); |
|
EMIT(PPC_RAW_SRW(_R0, dst_reg, _R0)); |
|
EMIT(PPC_RAW_SLW(tmp_reg, dst_reg, tmp_reg)); |
|
EMIT(PPC_RAW_OR(dst_reg_h, dst_reg_h, _R0)); |
|
EMIT(PPC_RAW_SLW(dst_reg, dst_reg, src_reg)); |
|
EMIT(PPC_RAW_OR(dst_reg_h, dst_reg_h, tmp_reg)); |
|
break; |
|
case BPF_ALU | BPF_LSH | BPF_K: /* (u32) dst <<= (u32) imm */ |
|
if (!imm) |
|
break; |
|
EMIT(PPC_RAW_SLWI(dst_reg, dst_reg, imm)); |
|
break; |
|
case BPF_ALU64 | BPF_LSH | BPF_K: /* dst <<= imm */ |
|
if (imm < 0) |
|
return -EINVAL; |
|
if (!imm) |
|
break; |
|
if (imm < 32) { |
|
EMIT(PPC_RAW_RLWINM(dst_reg_h, dst_reg_h, imm, 0, 31 - imm)); |
|
EMIT(PPC_RAW_RLWIMI(dst_reg_h, dst_reg, imm, 32 - imm, 31)); |
|
EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, imm, 0, 31 - imm)); |
|
break; |
|
} |
|
if (imm < 64) |
|
EMIT(PPC_RAW_RLWINM(dst_reg_h, dst_reg, imm, 0, 31 - imm)); |
|
else |
|
EMIT(PPC_RAW_LI(dst_reg_h, 0)); |
|
EMIT(PPC_RAW_LI(dst_reg, 0)); |
|
break; |
|
case BPF_ALU | BPF_RSH | BPF_X: /* (u32) dst >>= (u32) src */ |
|
EMIT(PPC_RAW_SRW(dst_reg, dst_reg, src_reg)); |
|
break; |
|
case BPF_ALU64 | BPF_RSH | BPF_X: /* dst >>= src */ |
|
bpf_set_seen_register(ctx, tmp_reg); |
|
EMIT(PPC_RAW_SUBFIC(_R0, src_reg, 32)); |
|
EMIT(PPC_RAW_SRW(dst_reg, dst_reg, src_reg)); |
|
EMIT(PPC_RAW_ADDI(tmp_reg, src_reg, 32)); |
|
EMIT(PPC_RAW_SLW(_R0, dst_reg_h, _R0)); |
|
EMIT(PPC_RAW_SRW(tmp_reg, dst_reg_h, tmp_reg)); |
|
EMIT(PPC_RAW_OR(dst_reg, dst_reg, _R0)); |
|
EMIT(PPC_RAW_SRW(dst_reg_h, dst_reg_h, src_reg)); |
|
EMIT(PPC_RAW_OR(dst_reg, dst_reg, tmp_reg)); |
|
break; |
|
case BPF_ALU | BPF_RSH | BPF_K: /* (u32) dst >>= (u32) imm */ |
|
if (!imm) |
|
break; |
|
EMIT(PPC_RAW_SRWI(dst_reg, dst_reg, imm)); |
|
break; |
|
case BPF_ALU64 | BPF_RSH | BPF_K: /* dst >>= imm */ |
|
if (imm < 0) |
|
return -EINVAL; |
|
if (!imm) |
|
break; |
|
if (imm < 32) { |
|
EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 32 - imm, imm, 31)); |
|
EMIT(PPC_RAW_RLWIMI(dst_reg, dst_reg_h, 32 - imm, 0, imm - 1)); |
|
EMIT(PPC_RAW_RLWINM(dst_reg_h, dst_reg_h, 32 - imm, imm, 31)); |
|
break; |
|
} |
|
if (imm < 64) |
|
EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg_h, 64 - imm, imm - 32, 31)); |
|
else |
|
EMIT(PPC_RAW_LI(dst_reg, 0)); |
|
EMIT(PPC_RAW_LI(dst_reg_h, 0)); |
|
break; |
|
case BPF_ALU | BPF_ARSH | BPF_X: /* (s32) dst >>= src */ |
|
EMIT(PPC_RAW_SRAW(dst_reg_h, dst_reg, src_reg)); |
|
break; |
|
case BPF_ALU64 | BPF_ARSH | BPF_X: /* (s64) dst >>= src */ |
|
bpf_set_seen_register(ctx, tmp_reg); |
|
EMIT(PPC_RAW_SUBFIC(_R0, src_reg, 32)); |
|
EMIT(PPC_RAW_SRW(dst_reg, dst_reg, src_reg)); |
|
EMIT(PPC_RAW_SLW(_R0, dst_reg_h, _R0)); |
|
EMIT(PPC_RAW_ADDI(tmp_reg, src_reg, 32)); |
|
EMIT(PPC_RAW_OR(dst_reg, dst_reg, _R0)); |
|
EMIT(PPC_RAW_RLWINM(_R0, tmp_reg, 0, 26, 26)); |
|
EMIT(PPC_RAW_SRAW(tmp_reg, dst_reg_h, tmp_reg)); |
|
EMIT(PPC_RAW_SRAW(dst_reg_h, dst_reg_h, src_reg)); |
|
EMIT(PPC_RAW_SLW(tmp_reg, tmp_reg, _R0)); |
|
EMIT(PPC_RAW_OR(dst_reg, dst_reg, tmp_reg)); |
|
break; |
|
case BPF_ALU | BPF_ARSH | BPF_K: /* (s32) dst >>= imm */ |
|
if (!imm) |
|
break; |
|
EMIT(PPC_RAW_SRAWI(dst_reg, dst_reg, imm)); |
|
break; |
|
case BPF_ALU64 | BPF_ARSH | BPF_K: /* (s64) dst >>= imm */ |
|
if (imm < 0) |
|
return -EINVAL; |
|
if (!imm) |
|
break; |
|
if (imm < 32) { |
|
EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 32 - imm, imm, 31)); |
|
EMIT(PPC_RAW_RLWIMI(dst_reg, dst_reg_h, 32 - imm, 0, imm - 1)); |
|
EMIT(PPC_RAW_SRAWI(dst_reg_h, dst_reg_h, imm)); |
|
break; |
|
} |
|
if (imm < 64) |
|
EMIT(PPC_RAW_SRAWI(dst_reg, dst_reg_h, imm - 32)); |
|
else |
|
EMIT(PPC_RAW_SRAWI(dst_reg, dst_reg_h, 31)); |
|
EMIT(PPC_RAW_SRAWI(dst_reg_h, dst_reg_h, 31)); |
|
break; |
|
|
|
/* |
|
* MOV |
|
*/ |
|
case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */ |
|
if (dst_reg == src_reg) |
|
break; |
|
EMIT(PPC_RAW_MR(dst_reg, src_reg)); |
|
EMIT(PPC_RAW_MR(dst_reg_h, src_reg_h)); |
|
break; |
|
case BPF_ALU | BPF_MOV | BPF_X: /* (u32) dst = src */ |
|
/* special mov32 for zext */ |
|
if (imm == 1) |
|
EMIT(PPC_RAW_LI(dst_reg_h, 0)); |
|
else if (dst_reg != src_reg) |
|
EMIT(PPC_RAW_MR(dst_reg, src_reg)); |
|
break; |
|
case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = (s64) imm */ |
|
PPC_LI32(dst_reg, imm); |
|
PPC_EX32(dst_reg_h, imm); |
|
break; |
|
case BPF_ALU | BPF_MOV | BPF_K: /* (u32) dst = imm */ |
|
PPC_LI32(dst_reg, imm); |
|
break; |
|
|
|
/* |
|
* BPF_FROM_BE/LE |
|
*/ |
|
case BPF_ALU | BPF_END | BPF_FROM_LE: |
|
switch (imm) { |
|
case 16: |
|
/* Copy 16 bits to upper part */ |
|
EMIT(PPC_RAW_RLWIMI(dst_reg, dst_reg, 16, 0, 15)); |
|
/* Rotate 8 bits right & mask */ |
|
EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 24, 16, 31)); |
|
break; |
|
case 32: |
|
/* |
|
* Rotate word left by 8 bits: |
|
* 2 bytes are already in their final position |
|
* -- byte 2 and 4 (of bytes 1, 2, 3 and 4) |
|
*/ |
|
EMIT(PPC_RAW_RLWINM(_R0, dst_reg, 8, 0, 31)); |
|
/* Rotate 24 bits and insert byte 1 */ |
|
EMIT(PPC_RAW_RLWIMI(_R0, dst_reg, 24, 0, 7)); |
|
/* Rotate 24 bits and insert byte 3 */ |
|
EMIT(PPC_RAW_RLWIMI(_R0, dst_reg, 24, 16, 23)); |
|
EMIT(PPC_RAW_MR(dst_reg, _R0)); |
|
break; |
|
case 64: |
|
bpf_set_seen_register(ctx, tmp_reg); |
|
EMIT(PPC_RAW_RLWINM(tmp_reg, dst_reg, 8, 0, 31)); |
|
EMIT(PPC_RAW_RLWINM(_R0, dst_reg_h, 8, 0, 31)); |
|
/* Rotate 24 bits and insert byte 1 */ |
|
EMIT(PPC_RAW_RLWIMI(tmp_reg, dst_reg, 24, 0, 7)); |
|
EMIT(PPC_RAW_RLWIMI(_R0, dst_reg_h, 24, 0, 7)); |
|
/* Rotate 24 bits and insert byte 3 */ |
|
EMIT(PPC_RAW_RLWIMI(tmp_reg, dst_reg, 24, 16, 23)); |
|
EMIT(PPC_RAW_RLWIMI(_R0, dst_reg_h, 24, 16, 23)); |
|
EMIT(PPC_RAW_MR(dst_reg, _R0)); |
|
EMIT(PPC_RAW_MR(dst_reg_h, tmp_reg)); |
|
break; |
|
} |
|
break; |
|
case BPF_ALU | BPF_END | BPF_FROM_BE: |
|
switch (imm) { |
|
case 16: |
|
/* zero-extend 16 bits into 32 bits */ |
|
EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, 16, 31)); |
|
break; |
|
case 32: |
|
case 64: |
|
/* nop */ |
|
break; |
|
} |
|
break; |
|
|
|
/* |
|
* BPF_ST(X) |
|
*/ |
|
case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src */ |
|
EMIT(PPC_RAW_STB(src_reg, dst_reg, off)); |
|
break; |
|
case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */ |
|
PPC_LI32(_R0, imm); |
|
EMIT(PPC_RAW_STB(_R0, dst_reg, off)); |
|
break; |
|
case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */ |
|
EMIT(PPC_RAW_STH(src_reg, dst_reg, off)); |
|
break; |
|
case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */ |
|
PPC_LI32(_R0, imm); |
|
EMIT(PPC_RAW_STH(_R0, dst_reg, off)); |
|
break; |
|
case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */ |
|
EMIT(PPC_RAW_STW(src_reg, dst_reg, off)); |
|
break; |
|
case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */ |
|
PPC_LI32(_R0, imm); |
|
EMIT(PPC_RAW_STW(_R0, dst_reg, off)); |
|
break; |
|
case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */ |
|
EMIT(PPC_RAW_STW(src_reg_h, dst_reg, off)); |
|
EMIT(PPC_RAW_STW(src_reg, dst_reg, off + 4)); |
|
break; |
|
case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */ |
|
PPC_LI32(_R0, imm); |
|
EMIT(PPC_RAW_STW(_R0, dst_reg, off + 4)); |
|
PPC_EX32(_R0, imm); |
|
EMIT(PPC_RAW_STW(_R0, dst_reg, off)); |
|
break; |
|
|
|
/* |
|
* BPF_STX ATOMIC (atomic ops) |
|
*/ |
|
case BPF_STX | BPF_ATOMIC | BPF_W: |
|
if (imm != BPF_ADD) { |
|
pr_err_ratelimited("eBPF filter atomic op code %02x (@%d) unsupported\n", |
|
code, i); |
|
return -ENOTSUPP; |
|
} |
|
|
|
/* *(u32 *)(dst + off) += src */ |
|
|
|
bpf_set_seen_register(ctx, tmp_reg); |
|
/* Get offset into TMP_REG */ |
|
EMIT(PPC_RAW_LI(tmp_reg, off)); |
|
/* load value from memory into r0 */ |
|
EMIT(PPC_RAW_LWARX(_R0, tmp_reg, dst_reg, 0)); |
|
/* add value from src_reg into this */ |
|
EMIT(PPC_RAW_ADD(_R0, _R0, src_reg)); |
|
/* store result back */ |
|
EMIT(PPC_RAW_STWCX(_R0, tmp_reg, dst_reg)); |
|
/* we're done if this succeeded */ |
|
PPC_BCC_SHORT(COND_NE, (ctx->idx - 3) * 4); |
|
break; |
|
|
|
case BPF_STX | BPF_ATOMIC | BPF_DW: /* *(u64 *)(dst + off) += src */ |
|
return -EOPNOTSUPP; |
|
|
|
/* |
|
* BPF_LDX |
|
*/ |
|
case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */ |
|
EMIT(PPC_RAW_LBZ(dst_reg, src_reg, off)); |
|
if (!fp->aux->verifier_zext) |
|
EMIT(PPC_RAW_LI(dst_reg_h, 0)); |
|
break; |
|
case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */ |
|
EMIT(PPC_RAW_LHZ(dst_reg, src_reg, off)); |
|
if (!fp->aux->verifier_zext) |
|
EMIT(PPC_RAW_LI(dst_reg_h, 0)); |
|
break; |
|
case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */ |
|
EMIT(PPC_RAW_LWZ(dst_reg, src_reg, off)); |
|
if (!fp->aux->verifier_zext) |
|
EMIT(PPC_RAW_LI(dst_reg_h, 0)); |
|
break; |
|
case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */ |
|
EMIT(PPC_RAW_LWZ(dst_reg_h, src_reg, off)); |
|
EMIT(PPC_RAW_LWZ(dst_reg, src_reg, off + 4)); |
|
break; |
|
|
|
/* |
|
* Doubleword load |
|
* 16 byte instruction that uses two 'struct bpf_insn' |
|
*/ |
|
case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */ |
|
PPC_LI32(dst_reg_h, (u32)insn[i + 1].imm); |
|
PPC_LI32(dst_reg, (u32)insn[i].imm); |
|
/* Adjust for two bpf instructions */ |
|
addrs[++i] = ctx->idx * 4; |
|
break; |
|
|
|
/* |
|
* Return/Exit |
|
*/ |
|
case BPF_JMP | BPF_EXIT: |
|
/* |
|
* If this isn't the very last instruction, branch to |
|
* the epilogue. If we _are_ the last instruction, |
|
* we'll just fall through to the epilogue. |
|
*/ |
|
if (i != flen - 1) |
|
PPC_JMP(exit_addr); |
|
/* else fall through to the epilogue */ |
|
break; |
|
|
|
/* |
|
* Call kernel helper or bpf function |
|
*/ |
|
case BPF_JMP | BPF_CALL: |
|
ctx->seen |= SEEN_FUNC; |
|
|
|
ret = bpf_jit_get_func_addr(fp, &insn[i], extra_pass, |
|
&func_addr, &func_addr_fixed); |
|
if (ret < 0) |
|
return ret; |
|
|
|
if (bpf_is_seen_register(ctx, bpf_to_ppc(ctx, BPF_REG_5))) { |
|
EMIT(PPC_RAW_STW(bpf_to_ppc(ctx, BPF_REG_5) - 1, _R1, 8)); |
|
EMIT(PPC_RAW_STW(bpf_to_ppc(ctx, BPF_REG_5), _R1, 12)); |
|
} |
|
|
|
bpf_jit_emit_func_call_rel(image, ctx, func_addr); |
|
|
|
EMIT(PPC_RAW_MR(bpf_to_ppc(ctx, BPF_REG_0) - 1, _R3)); |
|
EMIT(PPC_RAW_MR(bpf_to_ppc(ctx, BPF_REG_0), _R4)); |
|
break; |
|
|
|
/* |
|
* Jumps and branches |
|
*/ |
|
case BPF_JMP | BPF_JA: |
|
PPC_JMP(addrs[i + 1 + off]); |
|
break; |
|
|
|
case BPF_JMP | BPF_JGT | BPF_K: |
|
case BPF_JMP | BPF_JGT | BPF_X: |
|
case BPF_JMP | BPF_JSGT | BPF_K: |
|
case BPF_JMP | BPF_JSGT | BPF_X: |
|
case BPF_JMP32 | BPF_JGT | BPF_K: |
|
case BPF_JMP32 | BPF_JGT | BPF_X: |
|
case BPF_JMP32 | BPF_JSGT | BPF_K: |
|
case BPF_JMP32 | BPF_JSGT | BPF_X: |
|
true_cond = COND_GT; |
|
goto cond_branch; |
|
case BPF_JMP | BPF_JLT | BPF_K: |
|
case BPF_JMP | BPF_JLT | BPF_X: |
|
case BPF_JMP | BPF_JSLT | BPF_K: |
|
case BPF_JMP | BPF_JSLT | BPF_X: |
|
case BPF_JMP32 | BPF_JLT | BPF_K: |
|
case BPF_JMP32 | BPF_JLT | BPF_X: |
|
case BPF_JMP32 | BPF_JSLT | BPF_K: |
|
case BPF_JMP32 | BPF_JSLT | BPF_X: |
|
true_cond = COND_LT; |
|
goto cond_branch; |
|
case BPF_JMP | BPF_JGE | BPF_K: |
|
case BPF_JMP | BPF_JGE | BPF_X: |
|
case BPF_JMP | BPF_JSGE | BPF_K: |
|
case BPF_JMP | BPF_JSGE | BPF_X: |
|
case BPF_JMP32 | BPF_JGE | BPF_K: |
|
case BPF_JMP32 | BPF_JGE | BPF_X: |
|
case BPF_JMP32 | BPF_JSGE | BPF_K: |
|
case BPF_JMP32 | BPF_JSGE | BPF_X: |
|
true_cond = COND_GE; |
|
goto cond_branch; |
|
case BPF_JMP | BPF_JLE | BPF_K: |
|
case BPF_JMP | BPF_JLE | BPF_X: |
|
case BPF_JMP | BPF_JSLE | BPF_K: |
|
case BPF_JMP | BPF_JSLE | BPF_X: |
|
case BPF_JMP32 | BPF_JLE | BPF_K: |
|
case BPF_JMP32 | BPF_JLE | BPF_X: |
|
case BPF_JMP32 | BPF_JSLE | BPF_K: |
|
case BPF_JMP32 | BPF_JSLE | BPF_X: |
|
true_cond = COND_LE; |
|
goto cond_branch; |
|
case BPF_JMP | BPF_JEQ | BPF_K: |
|
case BPF_JMP | BPF_JEQ | BPF_X: |
|
case BPF_JMP32 | BPF_JEQ | BPF_K: |
|
case BPF_JMP32 | BPF_JEQ | BPF_X: |
|
true_cond = COND_EQ; |
|
goto cond_branch; |
|
case BPF_JMP | BPF_JNE | BPF_K: |
|
case BPF_JMP | BPF_JNE | BPF_X: |
|
case BPF_JMP32 | BPF_JNE | BPF_K: |
|
case BPF_JMP32 | BPF_JNE | BPF_X: |
|
true_cond = COND_NE; |
|
goto cond_branch; |
|
case BPF_JMP | BPF_JSET | BPF_K: |
|
case BPF_JMP | BPF_JSET | BPF_X: |
|
case BPF_JMP32 | BPF_JSET | BPF_K: |
|
case BPF_JMP32 | BPF_JSET | BPF_X: |
|
true_cond = COND_NE; |
|
/* fallthrough; */ |
|
|
|
cond_branch: |
|
switch (code) { |
|
case BPF_JMP | BPF_JGT | BPF_X: |
|
case BPF_JMP | BPF_JLT | BPF_X: |
|
case BPF_JMP | BPF_JGE | BPF_X: |
|
case BPF_JMP | BPF_JLE | BPF_X: |
|
case BPF_JMP | BPF_JEQ | BPF_X: |
|
case BPF_JMP | BPF_JNE | BPF_X: |
|
/* unsigned comparison */ |
|
EMIT(PPC_RAW_CMPLW(dst_reg_h, src_reg_h)); |
|
PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4); |
|
EMIT(PPC_RAW_CMPLW(dst_reg, src_reg)); |
|
break; |
|
case BPF_JMP32 | BPF_JGT | BPF_X: |
|
case BPF_JMP32 | BPF_JLT | BPF_X: |
|
case BPF_JMP32 | BPF_JGE | BPF_X: |
|
case BPF_JMP32 | BPF_JLE | BPF_X: |
|
case BPF_JMP32 | BPF_JEQ | BPF_X: |
|
case BPF_JMP32 | BPF_JNE | BPF_X: |
|
/* unsigned comparison */ |
|
EMIT(PPC_RAW_CMPLW(dst_reg, src_reg)); |
|
break; |
|
case BPF_JMP | BPF_JSGT | BPF_X: |
|
case BPF_JMP | BPF_JSLT | BPF_X: |
|
case BPF_JMP | BPF_JSGE | BPF_X: |
|
case BPF_JMP | BPF_JSLE | BPF_X: |
|
/* signed comparison */ |
|
EMIT(PPC_RAW_CMPW(dst_reg_h, src_reg_h)); |
|
PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4); |
|
EMIT(PPC_RAW_CMPLW(dst_reg, src_reg)); |
|
break; |
|
case BPF_JMP32 | BPF_JSGT | BPF_X: |
|
case BPF_JMP32 | BPF_JSLT | BPF_X: |
|
case BPF_JMP32 | BPF_JSGE | BPF_X: |
|
case BPF_JMP32 | BPF_JSLE | BPF_X: |
|
/* signed comparison */ |
|
EMIT(PPC_RAW_CMPW(dst_reg, src_reg)); |
|
break; |
|
case BPF_JMP | BPF_JSET | BPF_X: |
|
EMIT(PPC_RAW_AND_DOT(_R0, dst_reg_h, src_reg_h)); |
|
PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4); |
|
EMIT(PPC_RAW_AND_DOT(_R0, dst_reg, src_reg)); |
|
break; |
|
case BPF_JMP32 | BPF_JSET | BPF_X: { |
|
EMIT(PPC_RAW_AND_DOT(_R0, dst_reg, src_reg)); |
|
break; |
|
case BPF_JMP | BPF_JNE | BPF_K: |
|
case BPF_JMP | BPF_JEQ | BPF_K: |
|
case BPF_JMP | BPF_JGT | BPF_K: |
|
case BPF_JMP | BPF_JLT | BPF_K: |
|
case BPF_JMP | BPF_JGE | BPF_K: |
|
case BPF_JMP | BPF_JLE | BPF_K: |
|
/* |
|
* Need sign-extended load, so only positive |
|
* values can be used as imm in cmplwi |
|
*/ |
|
if (imm >= 0 && imm < 32768) { |
|
EMIT(PPC_RAW_CMPLWI(dst_reg_h, 0)); |
|
PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4); |
|
EMIT(PPC_RAW_CMPLWI(dst_reg, imm)); |
|
} else { |
|
/* sign-extending load ... but unsigned comparison */ |
|
PPC_EX32(_R0, imm); |
|
EMIT(PPC_RAW_CMPLW(dst_reg_h, _R0)); |
|
PPC_LI32(_R0, imm); |
|
PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4); |
|
EMIT(PPC_RAW_CMPLW(dst_reg, _R0)); |
|
} |
|
break; |
|
case BPF_JMP32 | BPF_JNE | BPF_K: |
|
case BPF_JMP32 | BPF_JEQ | BPF_K: |
|
case BPF_JMP32 | BPF_JGT | BPF_K: |
|
case BPF_JMP32 | BPF_JLT | BPF_K: |
|
case BPF_JMP32 | BPF_JGE | BPF_K: |
|
case BPF_JMP32 | BPF_JLE | BPF_K: |
|
if (imm >= 0 && imm < 65536) { |
|
EMIT(PPC_RAW_CMPLWI(dst_reg, imm)); |
|
} else { |
|
PPC_LI32(_R0, imm); |
|
EMIT(PPC_RAW_CMPLW(dst_reg, _R0)); |
|
} |
|
break; |
|
} |
|
case BPF_JMP | BPF_JSGT | BPF_K: |
|
case BPF_JMP | BPF_JSLT | BPF_K: |
|
case BPF_JMP | BPF_JSGE | BPF_K: |
|
case BPF_JMP | BPF_JSLE | BPF_K: |
|
if (imm >= 0 && imm < 65536) { |
|
EMIT(PPC_RAW_CMPWI(dst_reg_h, imm < 0 ? -1 : 0)); |
|
PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4); |
|
EMIT(PPC_RAW_CMPLWI(dst_reg, imm)); |
|
} else { |
|
/* sign-extending load */ |
|
EMIT(PPC_RAW_CMPWI(dst_reg_h, imm < 0 ? -1 : 0)); |
|
PPC_LI32(_R0, imm); |
|
PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4); |
|
EMIT(PPC_RAW_CMPLW(dst_reg, _R0)); |
|
} |
|
break; |
|
case BPF_JMP32 | BPF_JSGT | BPF_K: |
|
case BPF_JMP32 | BPF_JSLT | BPF_K: |
|
case BPF_JMP32 | BPF_JSGE | BPF_K: |
|
case BPF_JMP32 | BPF_JSLE | BPF_K: |
|
/* |
|
* signed comparison, so any 16-bit value |
|
* can be used in cmpwi |
|
*/ |
|
if (imm >= -32768 && imm < 32768) { |
|
EMIT(PPC_RAW_CMPWI(dst_reg, imm)); |
|
} else { |
|
/* sign-extending load */ |
|
PPC_LI32(_R0, imm); |
|
EMIT(PPC_RAW_CMPW(dst_reg, _R0)); |
|
} |
|
break; |
|
case BPF_JMP | BPF_JSET | BPF_K: |
|
/* andi does not sign-extend the immediate */ |
|
if (imm >= 0 && imm < 32768) { |
|
/* PPC_ANDI is _only/always_ dot-form */ |
|
EMIT(PPC_RAW_ANDI(_R0, dst_reg, imm)); |
|
} else { |
|
PPC_LI32(_R0, imm); |
|
if (imm < 0) { |
|
EMIT(PPC_RAW_CMPWI(dst_reg_h, 0)); |
|
PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4); |
|
} |
|
EMIT(PPC_RAW_AND_DOT(_R0, dst_reg, _R0)); |
|
} |
|
break; |
|
case BPF_JMP32 | BPF_JSET | BPF_K: |
|
/* andi does not sign-extend the immediate */ |
|
if (imm >= -32768 && imm < 32768) { |
|
/* PPC_ANDI is _only/always_ dot-form */ |
|
EMIT(PPC_RAW_ANDI(_R0, dst_reg, imm)); |
|
} else { |
|
PPC_LI32(_R0, imm); |
|
EMIT(PPC_RAW_AND_DOT(_R0, dst_reg, _R0)); |
|
} |
|
break; |
|
} |
|
PPC_BCC(true_cond, addrs[i + 1 + off]); |
|
break; |
|
|
|
/* |
|
* Tail call |
|
*/ |
|
case BPF_JMP | BPF_TAIL_CALL: |
|
ctx->seen |= SEEN_TAILCALL; |
|
bpf_jit_emit_tail_call(image, ctx, addrs[i + 1]); |
|
break; |
|
|
|
default: |
|
/* |
|
* The filter contains something cruel & unusual. |
|
* We don't handle it, but also there shouldn't be |
|
* anything missing from our list. |
|
*/ |
|
pr_err_ratelimited("eBPF filter opcode %04x (@%d) unsupported\n", code, i); |
|
return -EOPNOTSUPP; |
|
} |
|
if (BPF_CLASS(code) == BPF_ALU && !fp->aux->verifier_zext && |
|
!insn_is_zext(&insn[i + 1])) |
|
EMIT(PPC_RAW_LI(dst_reg_h, 0)); |
|
} |
|
|
|
/* Set end-of-body-code address for exit. */ |
|
addrs[i] = ctx->idx * 4; |
|
|
|
return 0; |
|
}
|
|
|