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930 lines
24 KiB
930 lines
24 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* native hashtable management. |
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* |
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* SMP scalability work: |
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* Copyright (C) 2001 Anton Blanchard <[email protected]>, IBM |
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*/ |
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|
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#undef DEBUG_LOW |
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|
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#include <linux/spinlock.h> |
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#include <linux/bitops.h> |
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#include <linux/of.h> |
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#include <linux/processor.h> |
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#include <linux/threads.h> |
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#include <linux/smp.h> |
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#include <linux/pgtable.h> |
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#include <asm/machdep.h> |
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#include <asm/mmu.h> |
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#include <asm/mmu_context.h> |
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#include <asm/trace.h> |
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#include <asm/tlb.h> |
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#include <asm/cputable.h> |
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#include <asm/udbg.h> |
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#include <asm/kexec.h> |
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#include <asm/ppc-opcode.h> |
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#include <asm/feature-fixups.h> |
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#include <misc/cxl-base.h> |
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#ifdef DEBUG_LOW |
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#define DBG_LOW(fmt...) udbg_printf(fmt) |
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#else |
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#define DBG_LOW(fmt...) |
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#endif |
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#ifdef __BIG_ENDIAN__ |
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#define HPTE_LOCK_BIT 3 |
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#else |
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#define HPTE_LOCK_BIT (56+3) |
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#endif |
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static DEFINE_RAW_SPINLOCK(native_tlbie_lock); |
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static inline void tlbiel_hash_set_isa206(unsigned int set, unsigned int is) |
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{ |
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unsigned long rb; |
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rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIFT(53)); |
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asm volatile("tlbiel %0" : : "r" (rb)); |
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} |
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/* |
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* tlbiel instruction for hash, set invalidation |
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* i.e., r=1 and is=01 or is=10 or is=11 |
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*/ |
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static __always_inline void tlbiel_hash_set_isa300(unsigned int set, unsigned int is, |
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unsigned int pid, |
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unsigned int ric, unsigned int prs) |
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{ |
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unsigned long rb; |
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unsigned long rs; |
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unsigned int r = 0; /* hash format */ |
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rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIFT(53)); |
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rs = ((unsigned long)pid << PPC_BITLSHIFT(31)); |
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asm volatile(PPC_TLBIEL(%0, %1, %2, %3, %4) |
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: : "r"(rb), "r"(rs), "i"(ric), "i"(prs), "i"(r) |
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: "memory"); |
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} |
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static void tlbiel_all_isa206(unsigned int num_sets, unsigned int is) |
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{ |
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unsigned int set; |
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asm volatile("ptesync": : :"memory"); |
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for (set = 0; set < num_sets; set++) |
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tlbiel_hash_set_isa206(set, is); |
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ppc_after_tlbiel_barrier(); |
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} |
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static void tlbiel_all_isa300(unsigned int num_sets, unsigned int is) |
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{ |
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unsigned int set; |
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asm volatile("ptesync": : :"memory"); |
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/* |
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* Flush the partition table cache if this is HV mode. |
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*/ |
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if (early_cpu_has_feature(CPU_FTR_HVMODE)) |
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tlbiel_hash_set_isa300(0, is, 0, 2, 0); |
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/* |
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* Now invalidate the process table cache. UPRT=0 HPT modes (what |
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* current hardware implements) do not use the process table, but |
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* add the flushes anyway. |
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* |
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* From ISA v3.0B p. 1078: |
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* The following forms are invalid. |
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* * PRS=1, R=0, and RIC!=2 (The only process-scoped |
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* HPT caching is of the Process Table.) |
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*/ |
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tlbiel_hash_set_isa300(0, is, 0, 2, 1); |
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/* |
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* Then flush the sets of the TLB proper. Hash mode uses |
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* partition scoped TLB translations, which may be flushed |
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* in !HV mode. |
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*/ |
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for (set = 0; set < num_sets; set++) |
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tlbiel_hash_set_isa300(set, is, 0, 0, 0); |
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ppc_after_tlbiel_barrier(); |
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asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT "; isync" : : :"memory"); |
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} |
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void hash__tlbiel_all(unsigned int action) |
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{ |
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unsigned int is; |
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switch (action) { |
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case TLB_INVAL_SCOPE_GLOBAL: |
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is = 3; |
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break; |
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case TLB_INVAL_SCOPE_LPID: |
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is = 2; |
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break; |
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default: |
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BUG(); |
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} |
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if (early_cpu_has_feature(CPU_FTR_ARCH_300)) |
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tlbiel_all_isa300(POWER9_TLB_SETS_HASH, is); |
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else if (early_cpu_has_feature(CPU_FTR_ARCH_207S)) |
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tlbiel_all_isa206(POWER8_TLB_SETS, is); |
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else if (early_cpu_has_feature(CPU_FTR_ARCH_206)) |
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tlbiel_all_isa206(POWER7_TLB_SETS, is); |
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else |
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WARN(1, "%s called on pre-POWER7 CPU\n", __func__); |
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} |
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static inline unsigned long ___tlbie(unsigned long vpn, int psize, |
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int apsize, int ssize) |
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{ |
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unsigned long va; |
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unsigned int penc; |
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unsigned long sllp; |
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/* |
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* We need 14 to 65 bits of va for a tlibe of 4K page |
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* With vpn we ignore the lower VPN_SHIFT bits already. |
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* And top two bits are already ignored because we can |
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* only accomodate 76 bits in a 64 bit vpn with a VPN_SHIFT |
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* of 12. |
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*/ |
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va = vpn << VPN_SHIFT; |
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/* |
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* clear top 16 bits of 64bit va, non SLS segment |
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* Older versions of the architecture (2.02 and earler) require the |
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* masking of the top 16 bits. |
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*/ |
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if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA)) |
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va &= ~(0xffffULL << 48); |
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switch (psize) { |
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case MMU_PAGE_4K: |
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/* clear out bits after (52) [0....52.....63] */ |
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va &= ~((1ul << (64 - 52)) - 1); |
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va |= ssize << 8; |
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sllp = get_sllp_encoding(apsize); |
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va |= sllp << 5; |
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asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2) |
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: : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) |
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: "memory"); |
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break; |
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default: |
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/* We need 14 to 14 + i bits of va */ |
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penc = mmu_psize_defs[psize].penc[apsize]; |
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va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1); |
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va |= penc << 12; |
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va |= ssize << 8; |
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/* |
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* AVAL bits: |
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* We don't need all the bits, but rest of the bits |
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* must be ignored by the processor. |
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* vpn cover upto 65 bits of va. (0...65) and we need |
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* 58..64 bits of va. |
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*/ |
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va |= (vpn & 0xfe); /* AVAL */ |
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va |= 1; /* L */ |
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asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2) |
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: : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) |
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: "memory"); |
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break; |
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} |
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return va; |
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} |
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static inline void fixup_tlbie_vpn(unsigned long vpn, int psize, |
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int apsize, int ssize) |
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{ |
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if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) { |
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/* Radix flush for a hash guest */ |
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unsigned long rb,rs,prs,r,ric; |
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rb = PPC_BIT(52); /* IS = 2 */ |
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rs = 0; /* lpid = 0 */ |
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prs = 0; /* partition scoped */ |
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r = 1; /* radix format */ |
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ric = 0; /* RIC_FLSUH_TLB */ |
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/* |
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* Need the extra ptesync to make sure we don't |
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* re-order the tlbie |
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*/ |
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asm volatile("ptesync": : :"memory"); |
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asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1) |
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: : "r"(rb), "i"(r), "i"(prs), |
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"i"(ric), "r"(rs) : "memory"); |
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} |
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if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) { |
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/* Need the extra ptesync to ensure we don't reorder tlbie*/ |
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asm volatile("ptesync": : :"memory"); |
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___tlbie(vpn, psize, apsize, ssize); |
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} |
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} |
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static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize) |
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{ |
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unsigned long rb; |
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rb = ___tlbie(vpn, psize, apsize, ssize); |
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trace_tlbie(0, 0, rb, 0, 0, 0, 0); |
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} |
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static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize) |
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{ |
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unsigned long va; |
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unsigned int penc; |
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unsigned long sllp; |
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/* VPN_SHIFT can be atmost 12 */ |
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va = vpn << VPN_SHIFT; |
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/* |
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* clear top 16 bits of 64 bit va, non SLS segment |
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* Older versions of the architecture (2.02 and earler) require the |
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* masking of the top 16 bits. |
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*/ |
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if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA)) |
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va &= ~(0xffffULL << 48); |
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switch (psize) { |
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case MMU_PAGE_4K: |
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/* clear out bits after(52) [0....52.....63] */ |
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va &= ~((1ul << (64 - 52)) - 1); |
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va |= ssize << 8; |
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sllp = get_sllp_encoding(apsize); |
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va |= sllp << 5; |
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asm volatile(ASM_FTR_IFSET("tlbiel %0", "tlbiel %0,0", %1) |
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: : "r" (va), "i" (CPU_FTR_ARCH_206) |
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: "memory"); |
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break; |
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default: |
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/* We need 14 to 14 + i bits of va */ |
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penc = mmu_psize_defs[psize].penc[apsize]; |
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va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1); |
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va |= penc << 12; |
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va |= ssize << 8; |
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/* |
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* AVAL bits: |
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* We don't need all the bits, but rest of the bits |
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* must be ignored by the processor. |
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* vpn cover upto 65 bits of va. (0...65) and we need |
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* 58..64 bits of va. |
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*/ |
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va |= (vpn & 0xfe); |
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va |= 1; /* L */ |
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asm volatile(ASM_FTR_IFSET("tlbiel %0", "tlbiel %0,1", %1) |
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: : "r" (va), "i" (CPU_FTR_ARCH_206) |
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: "memory"); |
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break; |
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} |
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trace_tlbie(0, 1, va, 0, 0, 0, 0); |
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} |
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static inline void tlbie(unsigned long vpn, int psize, int apsize, |
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int ssize, int local) |
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{ |
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unsigned int use_local; |
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int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); |
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use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) && !cxl_ctx_in_use(); |
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if (use_local) |
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use_local = mmu_psize_defs[psize].tlbiel; |
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if (lock_tlbie && !use_local) |
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raw_spin_lock(&native_tlbie_lock); |
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asm volatile("ptesync": : :"memory"); |
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if (use_local) { |
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__tlbiel(vpn, psize, apsize, ssize); |
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ppc_after_tlbiel_barrier(); |
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} else { |
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__tlbie(vpn, psize, apsize, ssize); |
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fixup_tlbie_vpn(vpn, psize, apsize, ssize); |
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asm volatile("eieio; tlbsync; ptesync": : :"memory"); |
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} |
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if (lock_tlbie && !use_local) |
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raw_spin_unlock(&native_tlbie_lock); |
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} |
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static inline void native_lock_hpte(struct hash_pte *hptep) |
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{ |
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unsigned long *word = (unsigned long *)&hptep->v; |
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while (1) { |
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if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word)) |
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break; |
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spin_begin(); |
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while(test_bit(HPTE_LOCK_BIT, word)) |
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spin_cpu_relax(); |
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spin_end(); |
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} |
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} |
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static inline void native_unlock_hpte(struct hash_pte *hptep) |
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{ |
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unsigned long *word = (unsigned long *)&hptep->v; |
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clear_bit_unlock(HPTE_LOCK_BIT, word); |
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} |
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static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn, |
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unsigned long pa, unsigned long rflags, |
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unsigned long vflags, int psize, int apsize, int ssize) |
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{ |
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struct hash_pte *hptep = htab_address + hpte_group; |
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unsigned long hpte_v, hpte_r; |
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int i; |
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if (!(vflags & HPTE_V_BOLTED)) { |
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DBG_LOW(" insert(group=%lx, vpn=%016lx, pa=%016lx," |
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" rflags=%lx, vflags=%lx, psize=%d)\n", |
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hpte_group, vpn, pa, rflags, vflags, psize); |
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} |
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for (i = 0; i < HPTES_PER_GROUP; i++) { |
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if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID)) { |
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/* retry with lock held */ |
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native_lock_hpte(hptep); |
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if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID)) |
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break; |
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native_unlock_hpte(hptep); |
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} |
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hptep++; |
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} |
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if (i == HPTES_PER_GROUP) |
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return -1; |
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hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID; |
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hpte_r = hpte_encode_r(pa, psize, apsize) | rflags; |
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if (!(vflags & HPTE_V_BOLTED)) { |
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DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n", |
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i, hpte_v, hpte_r); |
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} |
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if (cpu_has_feature(CPU_FTR_ARCH_300)) { |
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hpte_r = hpte_old_to_new_r(hpte_v, hpte_r); |
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hpte_v = hpte_old_to_new_v(hpte_v); |
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} |
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hptep->r = cpu_to_be64(hpte_r); |
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/* Guarantee the second dword is visible before the valid bit */ |
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eieio(); |
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/* |
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* Now set the first dword including the valid bit |
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* NOTE: this also unlocks the hpte |
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*/ |
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hptep->v = cpu_to_be64(hpte_v); |
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__asm__ __volatile__ ("ptesync" : : : "memory"); |
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return i | (!!(vflags & HPTE_V_SECONDARY) << 3); |
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} |
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static long native_hpte_remove(unsigned long hpte_group) |
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{ |
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struct hash_pte *hptep; |
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int i; |
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int slot_offset; |
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unsigned long hpte_v; |
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DBG_LOW(" remove(group=%lx)\n", hpte_group); |
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/* pick a random entry to start at */ |
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slot_offset = mftb() & 0x7; |
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for (i = 0; i < HPTES_PER_GROUP; i++) { |
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hptep = htab_address + hpte_group + slot_offset; |
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hpte_v = be64_to_cpu(hptep->v); |
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if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) { |
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/* retry with lock held */ |
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native_lock_hpte(hptep); |
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hpte_v = be64_to_cpu(hptep->v); |
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if ((hpte_v & HPTE_V_VALID) |
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&& !(hpte_v & HPTE_V_BOLTED)) |
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break; |
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native_unlock_hpte(hptep); |
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} |
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slot_offset++; |
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slot_offset &= 0x7; |
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} |
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if (i == HPTES_PER_GROUP) |
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return -1; |
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/* Invalidate the hpte. NOTE: this also unlocks it */ |
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hptep->v = 0; |
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return i; |
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} |
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static long native_hpte_updatepp(unsigned long slot, unsigned long newpp, |
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unsigned long vpn, int bpsize, |
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int apsize, int ssize, unsigned long flags) |
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{ |
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struct hash_pte *hptep = htab_address + slot; |
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unsigned long hpte_v, want_v; |
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int ret = 0, local = 0; |
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want_v = hpte_encode_avpn(vpn, bpsize, ssize); |
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DBG_LOW(" update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)", |
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vpn, want_v & HPTE_V_AVPN, slot, newpp); |
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hpte_v = hpte_get_old_v(hptep); |
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/* |
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* We need to invalidate the TLB always because hpte_remove doesn't do |
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* a tlb invalidate. If a hash bucket gets full, we "evict" a more/less |
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* random entry from it. When we do that we don't invalidate the TLB |
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* (hpte_remove) because we assume the old translation is still |
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* technically "valid". |
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*/ |
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if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) { |
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DBG_LOW(" -> miss\n"); |
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ret = -1; |
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} else { |
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native_lock_hpte(hptep); |
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/* recheck with locks held */ |
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hpte_v = hpte_get_old_v(hptep); |
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if (unlikely(!HPTE_V_COMPARE(hpte_v, want_v) || |
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!(hpte_v & HPTE_V_VALID))) { |
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ret = -1; |
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} else { |
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DBG_LOW(" -> hit\n"); |
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/* Update the HPTE */ |
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hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) & |
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~(HPTE_R_PPP | HPTE_R_N)) | |
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(newpp & (HPTE_R_PPP | HPTE_R_N | |
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HPTE_R_C))); |
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} |
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native_unlock_hpte(hptep); |
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} |
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|
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if (flags & HPTE_LOCAL_UPDATE) |
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local = 1; |
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/* |
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* Ensure it is out of the tlb too if it is not a nohpte fault |
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*/ |
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if (!(flags & HPTE_NOHPTE_UPDATE)) |
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tlbie(vpn, bpsize, apsize, ssize, local); |
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|
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return ret; |
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} |
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|
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static long __native_hpte_find(unsigned long want_v, unsigned long slot) |
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{ |
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struct hash_pte *hptep; |
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unsigned long hpte_v; |
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unsigned long i; |
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for (i = 0; i < HPTES_PER_GROUP; i++) { |
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hptep = htab_address + slot; |
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hpte_v = hpte_get_old_v(hptep); |
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if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) |
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/* HPTE matches */ |
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return slot; |
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++slot; |
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} |
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|
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return -1; |
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} |
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static long native_hpte_find(unsigned long vpn, int psize, int ssize) |
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{ |
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unsigned long hpte_group; |
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unsigned long want_v; |
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unsigned long hash; |
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long slot; |
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hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize); |
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want_v = hpte_encode_avpn(vpn, psize, ssize); |
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|
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/* |
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* We try to keep bolted entries always in primary hash |
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* But in some case we can find them in secondary too. |
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*/ |
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hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP; |
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slot = __native_hpte_find(want_v, hpte_group); |
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if (slot < 0) { |
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/* Try in secondary */ |
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hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP; |
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slot = __native_hpte_find(want_v, hpte_group); |
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if (slot < 0) |
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return -1; |
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} |
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|
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return slot; |
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} |
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|
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/* |
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* Update the page protection bits. Intended to be used to create |
|
* guard pages for kernel data structures on pages which are bolted |
|
* in the HPT. Assumes pages being operated on will not be stolen. |
|
* |
|
* No need to lock here because we should be the only user. |
|
*/ |
|
static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea, |
|
int psize, int ssize) |
|
{ |
|
unsigned long vpn; |
|
unsigned long vsid; |
|
long slot; |
|
struct hash_pte *hptep; |
|
|
|
vsid = get_kernel_vsid(ea, ssize); |
|
vpn = hpt_vpn(ea, vsid, ssize); |
|
|
|
slot = native_hpte_find(vpn, psize, ssize); |
|
if (slot == -1) |
|
panic("could not find page to bolt\n"); |
|
hptep = htab_address + slot; |
|
|
|
/* Update the HPTE */ |
|
hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) & |
|
~(HPTE_R_PPP | HPTE_R_N)) | |
|
(newpp & (HPTE_R_PPP | HPTE_R_N))); |
|
/* |
|
* Ensure it is out of the tlb too. Bolted entries base and |
|
* actual page size will be same. |
|
*/ |
|
tlbie(vpn, psize, psize, ssize, 0); |
|
} |
|
|
|
/* |
|
* Remove a bolted kernel entry. Memory hotplug uses this. |
|
* |
|
* No need to lock here because we should be the only user. |
|
*/ |
|
static int native_hpte_removebolted(unsigned long ea, int psize, int ssize) |
|
{ |
|
unsigned long vpn; |
|
unsigned long vsid; |
|
long slot; |
|
struct hash_pte *hptep; |
|
|
|
vsid = get_kernel_vsid(ea, ssize); |
|
vpn = hpt_vpn(ea, vsid, ssize); |
|
|
|
slot = native_hpte_find(vpn, psize, ssize); |
|
if (slot == -1) |
|
return -ENOENT; |
|
|
|
hptep = htab_address + slot; |
|
|
|
VM_WARN_ON(!(be64_to_cpu(hptep->v) & HPTE_V_BOLTED)); |
|
|
|
/* Invalidate the hpte */ |
|
hptep->v = 0; |
|
|
|
/* Invalidate the TLB */ |
|
tlbie(vpn, psize, psize, ssize, 0); |
|
return 0; |
|
} |
|
|
|
|
|
static void native_hpte_invalidate(unsigned long slot, unsigned long vpn, |
|
int bpsize, int apsize, int ssize, int local) |
|
{ |
|
struct hash_pte *hptep = htab_address + slot; |
|
unsigned long hpte_v; |
|
unsigned long want_v; |
|
unsigned long flags; |
|
|
|
local_irq_save(flags); |
|
|
|
DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot); |
|
|
|
want_v = hpte_encode_avpn(vpn, bpsize, ssize); |
|
hpte_v = hpte_get_old_v(hptep); |
|
|
|
if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) { |
|
native_lock_hpte(hptep); |
|
/* recheck with locks held */ |
|
hpte_v = hpte_get_old_v(hptep); |
|
|
|
if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) |
|
/* Invalidate the hpte. NOTE: this also unlocks it */ |
|
hptep->v = 0; |
|
else |
|
native_unlock_hpte(hptep); |
|
} |
|
/* |
|
* We need to invalidate the TLB always because hpte_remove doesn't do |
|
* a tlb invalidate. If a hash bucket gets full, we "evict" a more/less |
|
* random entry from it. When we do that we don't invalidate the TLB |
|
* (hpte_remove) because we assume the old translation is still |
|
* technically "valid". |
|
*/ |
|
tlbie(vpn, bpsize, apsize, ssize, local); |
|
|
|
local_irq_restore(flags); |
|
} |
|
|
|
#ifdef CONFIG_TRANSPARENT_HUGEPAGE |
|
static void native_hugepage_invalidate(unsigned long vsid, |
|
unsigned long addr, |
|
unsigned char *hpte_slot_array, |
|
int psize, int ssize, int local) |
|
{ |
|
int i; |
|
struct hash_pte *hptep; |
|
int actual_psize = MMU_PAGE_16M; |
|
unsigned int max_hpte_count, valid; |
|
unsigned long flags, s_addr = addr; |
|
unsigned long hpte_v, want_v, shift; |
|
unsigned long hidx, vpn = 0, hash, slot; |
|
|
|
shift = mmu_psize_defs[psize].shift; |
|
max_hpte_count = 1U << (PMD_SHIFT - shift); |
|
|
|
local_irq_save(flags); |
|
for (i = 0; i < max_hpte_count; i++) { |
|
valid = hpte_valid(hpte_slot_array, i); |
|
if (!valid) |
|
continue; |
|
hidx = hpte_hash_index(hpte_slot_array, i); |
|
|
|
/* get the vpn */ |
|
addr = s_addr + (i * (1ul << shift)); |
|
vpn = hpt_vpn(addr, vsid, ssize); |
|
hash = hpt_hash(vpn, shift, ssize); |
|
if (hidx & _PTEIDX_SECONDARY) |
|
hash = ~hash; |
|
|
|
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; |
|
slot += hidx & _PTEIDX_GROUP_IX; |
|
|
|
hptep = htab_address + slot; |
|
want_v = hpte_encode_avpn(vpn, psize, ssize); |
|
hpte_v = hpte_get_old_v(hptep); |
|
|
|
/* Even if we miss, we need to invalidate the TLB */ |
|
if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) { |
|
/* recheck with locks held */ |
|
native_lock_hpte(hptep); |
|
hpte_v = hpte_get_old_v(hptep); |
|
|
|
if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) { |
|
/* |
|
* Invalidate the hpte. NOTE: this also unlocks it |
|
*/ |
|
|
|
hptep->v = 0; |
|
} else |
|
native_unlock_hpte(hptep); |
|
} |
|
/* |
|
* We need to do tlb invalidate for all the address, tlbie |
|
* instruction compares entry_VA in tlb with the VA specified |
|
* here |
|
*/ |
|
tlbie(vpn, psize, actual_psize, ssize, local); |
|
} |
|
local_irq_restore(flags); |
|
} |
|
#else |
|
static void native_hugepage_invalidate(unsigned long vsid, |
|
unsigned long addr, |
|
unsigned char *hpte_slot_array, |
|
int psize, int ssize, int local) |
|
{ |
|
WARN(1, "%s called without THP support\n", __func__); |
|
} |
|
#endif |
|
|
|
static void hpte_decode(struct hash_pte *hpte, unsigned long slot, |
|
int *psize, int *apsize, int *ssize, unsigned long *vpn) |
|
{ |
|
unsigned long avpn, pteg, vpi; |
|
unsigned long hpte_v = be64_to_cpu(hpte->v); |
|
unsigned long hpte_r = be64_to_cpu(hpte->r); |
|
unsigned long vsid, seg_off; |
|
int size, a_size, shift; |
|
/* Look at the 8 bit LP value */ |
|
unsigned int lp = (hpte_r >> LP_SHIFT) & ((1 << LP_BITS) - 1); |
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_300)) { |
|
hpte_v = hpte_new_to_old_v(hpte_v, hpte_r); |
|
hpte_r = hpte_new_to_old_r(hpte_r); |
|
} |
|
if (!(hpte_v & HPTE_V_LARGE)) { |
|
size = MMU_PAGE_4K; |
|
a_size = MMU_PAGE_4K; |
|
} else { |
|
size = hpte_page_sizes[lp] & 0xf; |
|
a_size = hpte_page_sizes[lp] >> 4; |
|
} |
|
/* This works for all page sizes, and for 256M and 1T segments */ |
|
*ssize = hpte_v >> HPTE_V_SSIZE_SHIFT; |
|
shift = mmu_psize_defs[size].shift; |
|
|
|
avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm); |
|
pteg = slot / HPTES_PER_GROUP; |
|
if (hpte_v & HPTE_V_SECONDARY) |
|
pteg = ~pteg; |
|
|
|
switch (*ssize) { |
|
case MMU_SEGSIZE_256M: |
|
/* We only have 28 - 23 bits of seg_off in avpn */ |
|
seg_off = (avpn & 0x1f) << 23; |
|
vsid = avpn >> 5; |
|
/* We can find more bits from the pteg value */ |
|
if (shift < 23) { |
|
vpi = (vsid ^ pteg) & htab_hash_mask; |
|
seg_off |= vpi << shift; |
|
} |
|
*vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT; |
|
break; |
|
case MMU_SEGSIZE_1T: |
|
/* We only have 40 - 23 bits of seg_off in avpn */ |
|
seg_off = (avpn & 0x1ffff) << 23; |
|
vsid = avpn >> 17; |
|
if (shift < 23) { |
|
vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask; |
|
seg_off |= vpi << shift; |
|
} |
|
*vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT; |
|
break; |
|
default: |
|
*vpn = size = 0; |
|
} |
|
*psize = size; |
|
*apsize = a_size; |
|
} |
|
|
|
/* |
|
* clear all mappings on kexec. All cpus are in real mode (or they will |
|
* be when they isi), and we are the only one left. We rely on our kernel |
|
* mapping being 0xC0's and the hardware ignoring those two real bits. |
|
* |
|
* This must be called with interrupts disabled. |
|
* |
|
* Taking the native_tlbie_lock is unsafe here due to the possibility of |
|
* lockdep being on. On pre POWER5 hardware, not taking the lock could |
|
* cause deadlock. POWER5 and newer not taking the lock is fine. This only |
|
* gets called during boot before secondary CPUs have come up and during |
|
* crashdump and all bets are off anyway. |
|
* |
|
* TODO: add batching support when enabled. remember, no dynamic memory here, |
|
* although there is the control page available... |
|
*/ |
|
static void native_hpte_clear(void) |
|
{ |
|
unsigned long vpn = 0; |
|
unsigned long slot, slots; |
|
struct hash_pte *hptep = htab_address; |
|
unsigned long hpte_v; |
|
unsigned long pteg_count; |
|
int psize, apsize, ssize; |
|
|
|
pteg_count = htab_hash_mask + 1; |
|
|
|
slots = pteg_count * HPTES_PER_GROUP; |
|
|
|
for (slot = 0; slot < slots; slot++, hptep++) { |
|
/* |
|
* we could lock the pte here, but we are the only cpu |
|
* running, right? and for crash dump, we probably |
|
* don't want to wait for a maybe bad cpu. |
|
*/ |
|
hpte_v = be64_to_cpu(hptep->v); |
|
|
|
/* |
|
* Call __tlbie() here rather than tlbie() since we can't take the |
|
* native_tlbie_lock. |
|
*/ |
|
if (hpte_v & HPTE_V_VALID) { |
|
hpte_decode(hptep, slot, &psize, &apsize, &ssize, &vpn); |
|
hptep->v = 0; |
|
___tlbie(vpn, psize, apsize, ssize); |
|
} |
|
} |
|
|
|
asm volatile("eieio; tlbsync; ptesync":::"memory"); |
|
} |
|
|
|
/* |
|
* Batched hash table flush, we batch the tlbie's to avoid taking/releasing |
|
* the lock all the time |
|
*/ |
|
static void native_flush_hash_range(unsigned long number, int local) |
|
{ |
|
unsigned long vpn = 0; |
|
unsigned long hash, index, hidx, shift, slot; |
|
struct hash_pte *hptep; |
|
unsigned long hpte_v; |
|
unsigned long want_v; |
|
unsigned long flags; |
|
real_pte_t pte; |
|
struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch); |
|
unsigned long psize = batch->psize; |
|
int ssize = batch->ssize; |
|
int i; |
|
unsigned int use_local; |
|
|
|
use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) && |
|
mmu_psize_defs[psize].tlbiel && !cxl_ctx_in_use(); |
|
|
|
local_irq_save(flags); |
|
|
|
for (i = 0; i < number; i++) { |
|
vpn = batch->vpn[i]; |
|
pte = batch->pte[i]; |
|
|
|
pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { |
|
hash = hpt_hash(vpn, shift, ssize); |
|
hidx = __rpte_to_hidx(pte, index); |
|
if (hidx & _PTEIDX_SECONDARY) |
|
hash = ~hash; |
|
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; |
|
slot += hidx & _PTEIDX_GROUP_IX; |
|
hptep = htab_address + slot; |
|
want_v = hpte_encode_avpn(vpn, psize, ssize); |
|
hpte_v = hpte_get_old_v(hptep); |
|
|
|
if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) |
|
continue; |
|
/* lock and try again */ |
|
native_lock_hpte(hptep); |
|
hpte_v = hpte_get_old_v(hptep); |
|
|
|
if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) |
|
native_unlock_hpte(hptep); |
|
else |
|
hptep->v = 0; |
|
|
|
} pte_iterate_hashed_end(); |
|
} |
|
|
|
if (use_local) { |
|
asm volatile("ptesync":::"memory"); |
|
for (i = 0; i < number; i++) { |
|
vpn = batch->vpn[i]; |
|
pte = batch->pte[i]; |
|
|
|
pte_iterate_hashed_subpages(pte, psize, |
|
vpn, index, shift) { |
|
__tlbiel(vpn, psize, psize, ssize); |
|
} pte_iterate_hashed_end(); |
|
} |
|
ppc_after_tlbiel_barrier(); |
|
} else { |
|
int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); |
|
|
|
if (lock_tlbie) |
|
raw_spin_lock(&native_tlbie_lock); |
|
|
|
asm volatile("ptesync":::"memory"); |
|
for (i = 0; i < number; i++) { |
|
vpn = batch->vpn[i]; |
|
pte = batch->pte[i]; |
|
|
|
pte_iterate_hashed_subpages(pte, psize, |
|
vpn, index, shift) { |
|
__tlbie(vpn, psize, psize, ssize); |
|
} pte_iterate_hashed_end(); |
|
} |
|
/* |
|
* Just do one more with the last used values. |
|
*/ |
|
fixup_tlbie_vpn(vpn, psize, psize, ssize); |
|
asm volatile("eieio; tlbsync; ptesync":::"memory"); |
|
|
|
if (lock_tlbie) |
|
raw_spin_unlock(&native_tlbie_lock); |
|
} |
|
|
|
local_irq_restore(flags); |
|
} |
|
|
|
void __init hpte_init_native(void) |
|
{ |
|
mmu_hash_ops.hpte_invalidate = native_hpte_invalidate; |
|
mmu_hash_ops.hpte_updatepp = native_hpte_updatepp; |
|
mmu_hash_ops.hpte_updateboltedpp = native_hpte_updateboltedpp; |
|
mmu_hash_ops.hpte_removebolted = native_hpte_removebolted; |
|
mmu_hash_ops.hpte_insert = native_hpte_insert; |
|
mmu_hash_ops.hpte_remove = native_hpte_remove; |
|
mmu_hash_ops.hpte_clear_all = native_hpte_clear; |
|
mmu_hash_ops.flush_hash_range = native_flush_hash_range; |
|
mmu_hash_ops.hugepage_invalidate = native_hugepage_invalidate; |
|
}
|
|
|