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494 lines
14 KiB
494 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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#include <linux/regset.h> |
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#include <linux/hw_breakpoint.h> |
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#include "ptrace-decl.h" |
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void user_enable_single_step(struct task_struct *task) |
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{ |
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struct pt_regs *regs = task->thread.regs; |
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if (regs != NULL) { |
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task->thread.debug.dbcr0 &= ~DBCR0_BT; |
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task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; |
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regs_set_return_msr(regs, regs->msr | MSR_DE); |
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} |
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set_tsk_thread_flag(task, TIF_SINGLESTEP); |
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} |
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void user_enable_block_step(struct task_struct *task) |
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{ |
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struct pt_regs *regs = task->thread.regs; |
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if (regs != NULL) { |
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task->thread.debug.dbcr0 &= ~DBCR0_IC; |
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task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT; |
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regs_set_return_msr(regs, regs->msr | MSR_DE); |
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} |
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set_tsk_thread_flag(task, TIF_SINGLESTEP); |
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} |
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void user_disable_single_step(struct task_struct *task) |
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{ |
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struct pt_regs *regs = task->thread.regs; |
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if (regs != NULL) { |
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/* |
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* The logic to disable single stepping should be as |
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* simple as turning off the Instruction Complete flag. |
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* And, after doing so, if all debug flags are off, turn |
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* off DBCR0(IDM) and MSR(DE) .... Torez |
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*/ |
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task->thread.debug.dbcr0 &= ~(DBCR0_IC | DBCR0_BT); |
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/* |
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* Test to see if any of the DBCR_ACTIVE_EVENTS bits are set. |
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*/ |
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if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, |
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task->thread.debug.dbcr1)) { |
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/* |
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* All debug events were off..... |
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*/ |
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task->thread.debug.dbcr0 &= ~DBCR0_IDM; |
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regs_set_return_msr(regs, regs->msr & ~MSR_DE); |
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} |
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} |
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clear_tsk_thread_flag(task, TIF_SINGLESTEP); |
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} |
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void ppc_gethwdinfo(struct ppc_debug_info *dbginfo) |
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{ |
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dbginfo->version = 1; |
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dbginfo->num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS; |
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dbginfo->num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS; |
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dbginfo->num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS; |
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dbginfo->data_bp_alignment = 4; |
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dbginfo->sizeof_condition = 4; |
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dbginfo->features = PPC_DEBUG_FEATURE_INSN_BP_RANGE | |
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PPC_DEBUG_FEATURE_INSN_BP_MASK; |
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if (IS_ENABLED(CONFIG_PPC_ADV_DEBUG_DAC_RANGE)) |
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dbginfo->features |= PPC_DEBUG_FEATURE_DATA_BP_RANGE | |
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PPC_DEBUG_FEATURE_DATA_BP_MASK; |
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} |
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int ptrace_get_debugreg(struct task_struct *child, unsigned long addr, |
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unsigned long __user *datalp) |
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{ |
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/* We only support one DABR and no IABRS at the moment */ |
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if (addr > 0) |
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return -EINVAL; |
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return put_user(child->thread.debug.dac1, datalp); |
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} |
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int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, unsigned long data) |
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{ |
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struct pt_regs *regs = task->thread.regs; |
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#ifdef CONFIG_HAVE_HW_BREAKPOINT |
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int ret; |
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struct thread_struct *thread = &task->thread; |
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struct perf_event *bp; |
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struct perf_event_attr attr; |
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#endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
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/* For ppc64 we support one DABR and no IABR's at the moment (ppc64). |
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* For embedded processors we support one DAC and no IAC's at the |
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* moment. |
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*/ |
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if (addr > 0) |
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return -EINVAL; |
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/* The bottom 3 bits in dabr are flags */ |
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if ((data & ~0x7UL) >= TASK_SIZE) |
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return -EIO; |
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/* As described above, it was assumed 3 bits were passed with the data |
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* address, but we will assume only the mode bits will be passed |
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* as to not cause alignment restrictions for DAC-based processors. |
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*/ |
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/* DAC's hold the whole address without any mode flags */ |
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task->thread.debug.dac1 = data & ~0x3UL; |
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if (task->thread.debug.dac1 == 0) { |
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dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
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if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, |
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task->thread.debug.dbcr1)) { |
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regs_set_return_msr(regs, regs->msr & ~MSR_DE); |
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task->thread.debug.dbcr0 &= ~DBCR0_IDM; |
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} |
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return 0; |
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} |
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/* Read or Write bits must be set */ |
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if (!(data & 0x3UL)) |
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return -EINVAL; |
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/* Set the Internal Debugging flag (IDM bit 1) for the DBCR0 register */ |
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task->thread.debug.dbcr0 |= DBCR0_IDM; |
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/* Check for write and read flags and set DBCR0 accordingly */ |
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dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
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if (data & 0x1UL) |
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dbcr_dac(task) |= DBCR_DAC1R; |
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if (data & 0x2UL) |
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dbcr_dac(task) |= DBCR_DAC1W; |
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regs_set_return_msr(regs, regs->msr | MSR_DE); |
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return 0; |
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} |
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static long set_instruction_bp(struct task_struct *child, |
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struct ppc_hw_breakpoint *bp_info) |
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{ |
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int slot; |
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int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0); |
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int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0); |
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int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0); |
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int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0); |
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if (dbcr_iac_range(child) & DBCR_IAC12MODE) |
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slot2_in_use = 1; |
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if (dbcr_iac_range(child) & DBCR_IAC34MODE) |
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slot4_in_use = 1; |
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if (bp_info->addr >= TASK_SIZE) |
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return -EIO; |
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if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) { |
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/* Make sure range is valid. */ |
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if (bp_info->addr2 >= TASK_SIZE) |
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return -EIO; |
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/* We need a pair of IAC regsisters */ |
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if (!slot1_in_use && !slot2_in_use) { |
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slot = 1; |
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child->thread.debug.iac1 = bp_info->addr; |
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child->thread.debug.iac2 = bp_info->addr2; |
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child->thread.debug.dbcr0 |= DBCR0_IAC1; |
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if (bp_info->addr_mode == |
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PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) |
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dbcr_iac_range(child) |= DBCR_IAC12X; |
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else |
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dbcr_iac_range(child) |= DBCR_IAC12I; |
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#if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
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} else if ((!slot3_in_use) && (!slot4_in_use)) { |
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slot = 3; |
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child->thread.debug.iac3 = bp_info->addr; |
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child->thread.debug.iac4 = bp_info->addr2; |
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child->thread.debug.dbcr0 |= DBCR0_IAC3; |
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if (bp_info->addr_mode == |
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PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) |
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dbcr_iac_range(child) |= DBCR_IAC34X; |
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else |
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dbcr_iac_range(child) |= DBCR_IAC34I; |
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#endif |
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} else { |
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return -ENOSPC; |
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} |
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} else { |
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/* We only need one. If possible leave a pair free in |
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* case a range is needed later |
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*/ |
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if (!slot1_in_use) { |
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/* |
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* Don't use iac1 if iac1-iac2 are free and either |
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* iac3 or iac4 (but not both) are free |
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*/ |
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if (slot2_in_use || slot3_in_use == slot4_in_use) { |
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slot = 1; |
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child->thread.debug.iac1 = bp_info->addr; |
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child->thread.debug.dbcr0 |= DBCR0_IAC1; |
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goto out; |
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} |
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} |
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if (!slot2_in_use) { |
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slot = 2; |
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child->thread.debug.iac2 = bp_info->addr; |
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child->thread.debug.dbcr0 |= DBCR0_IAC2; |
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#if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
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} else if (!slot3_in_use) { |
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slot = 3; |
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child->thread.debug.iac3 = bp_info->addr; |
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child->thread.debug.dbcr0 |= DBCR0_IAC3; |
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} else if (!slot4_in_use) { |
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slot = 4; |
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child->thread.debug.iac4 = bp_info->addr; |
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child->thread.debug.dbcr0 |= DBCR0_IAC4; |
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#endif |
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} else { |
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return -ENOSPC; |
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} |
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} |
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out: |
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child->thread.debug.dbcr0 |= DBCR0_IDM; |
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regs_set_return_msr(child->thread.regs, child->thread.regs->msr | MSR_DE); |
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return slot; |
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} |
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static int del_instruction_bp(struct task_struct *child, int slot) |
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{ |
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switch (slot) { |
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case 1: |
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if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0) |
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return -ENOENT; |
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if (dbcr_iac_range(child) & DBCR_IAC12MODE) { |
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/* address range - clear slots 1 & 2 */ |
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child->thread.debug.iac2 = 0; |
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dbcr_iac_range(child) &= ~DBCR_IAC12MODE; |
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} |
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child->thread.debug.iac1 = 0; |
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child->thread.debug.dbcr0 &= ~DBCR0_IAC1; |
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break; |
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case 2: |
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if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0) |
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return -ENOENT; |
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if (dbcr_iac_range(child) & DBCR_IAC12MODE) |
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/* used in a range */ |
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return -EINVAL; |
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child->thread.debug.iac2 = 0; |
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child->thread.debug.dbcr0 &= ~DBCR0_IAC2; |
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break; |
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#if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
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case 3: |
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if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0) |
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return -ENOENT; |
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if (dbcr_iac_range(child) & DBCR_IAC34MODE) { |
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/* address range - clear slots 3 & 4 */ |
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child->thread.debug.iac4 = 0; |
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dbcr_iac_range(child) &= ~DBCR_IAC34MODE; |
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} |
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child->thread.debug.iac3 = 0; |
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child->thread.debug.dbcr0 &= ~DBCR0_IAC3; |
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break; |
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case 4: |
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if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0) |
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return -ENOENT; |
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if (dbcr_iac_range(child) & DBCR_IAC34MODE) |
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/* Used in a range */ |
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return -EINVAL; |
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child->thread.debug.iac4 = 0; |
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child->thread.debug.dbcr0 &= ~DBCR0_IAC4; |
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break; |
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#endif |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info) |
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{ |
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int byte_enable = |
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(bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT) |
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& 0xf; |
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int condition_mode = |
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bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE; |
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int slot; |
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if (byte_enable && condition_mode == 0) |
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return -EINVAL; |
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if (bp_info->addr >= TASK_SIZE) |
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return -EIO; |
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if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) { |
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slot = 1; |
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if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) |
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dbcr_dac(child) |= DBCR_DAC1R; |
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if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
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dbcr_dac(child) |= DBCR_DAC1W; |
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child->thread.debug.dac1 = (unsigned long)bp_info->addr; |
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#if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
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if (byte_enable) { |
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child->thread.debug.dvc1 = |
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(unsigned long)bp_info->condition_value; |
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child->thread.debug.dbcr2 |= |
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((byte_enable << DBCR2_DVC1BE_SHIFT) | |
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(condition_mode << DBCR2_DVC1M_SHIFT)); |
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} |
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#endif |
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#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE |
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} else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) { |
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/* Both dac1 and dac2 are part of a range */ |
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return -ENOSPC; |
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#endif |
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} else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) { |
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slot = 2; |
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if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) |
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dbcr_dac(child) |= DBCR_DAC2R; |
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if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
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dbcr_dac(child) |= DBCR_DAC2W; |
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child->thread.debug.dac2 = (unsigned long)bp_info->addr; |
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#if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
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if (byte_enable) { |
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child->thread.debug.dvc2 = |
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(unsigned long)bp_info->condition_value; |
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child->thread.debug.dbcr2 |= |
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((byte_enable << DBCR2_DVC2BE_SHIFT) | |
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(condition_mode << DBCR2_DVC2M_SHIFT)); |
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} |
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#endif |
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} else { |
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return -ENOSPC; |
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} |
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child->thread.debug.dbcr0 |= DBCR0_IDM; |
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regs_set_return_msr(child->thread.regs, child->thread.regs->msr | MSR_DE); |
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return slot + 4; |
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} |
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static int del_dac(struct task_struct *child, int slot) |
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{ |
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if (slot == 1) { |
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if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) |
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return -ENOENT; |
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child->thread.debug.dac1 = 0; |
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dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
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#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE |
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if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) { |
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child->thread.debug.dac2 = 0; |
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child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; |
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} |
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child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE); |
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#endif |
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#if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
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child->thread.debug.dvc1 = 0; |
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#endif |
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} else if (slot == 2) { |
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if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) |
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return -ENOENT; |
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#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE |
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if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) |
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/* Part of a range */ |
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return -EINVAL; |
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child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE); |
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#endif |
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#if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
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child->thread.debug.dvc2 = 0; |
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#endif |
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child->thread.debug.dac2 = 0; |
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dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W); |
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} else { |
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return -EINVAL; |
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} |
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return 0; |
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} |
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#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE |
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static int set_dac_range(struct task_struct *child, |
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struct ppc_hw_breakpoint *bp_info) |
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{ |
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int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK; |
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/* We don't allow range watchpoints to be used with DVC */ |
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if (bp_info->condition_mode) |
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return -EINVAL; |
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/* |
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* Best effort to verify the address range. The user/supervisor bits |
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* prevent trapping in kernel space, but let's fail on an obvious bad |
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* range. The simple test on the mask is not fool-proof, and any |
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* exclusive range will spill over into kernel space. |
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*/ |
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if (bp_info->addr >= TASK_SIZE) |
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return -EIO; |
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if (mode == PPC_BREAKPOINT_MODE_MASK) { |
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/* |
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* dac2 is a bitmask. Don't allow a mask that makes a |
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* kernel space address from a valid dac1 value |
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*/ |
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if (~((unsigned long)bp_info->addr2) >= TASK_SIZE) |
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return -EIO; |
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} else { |
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/* |
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* For range breakpoints, addr2 must also be a valid address |
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*/ |
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if (bp_info->addr2 >= TASK_SIZE) |
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return -EIO; |
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} |
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if (child->thread.debug.dbcr0 & |
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(DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)) |
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return -ENOSPC; |
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if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) |
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child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM); |
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if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
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child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM); |
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child->thread.debug.dac1 = bp_info->addr; |
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child->thread.debug.dac2 = bp_info->addr2; |
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if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) |
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child->thread.debug.dbcr2 |= DBCR2_DAC12M; |
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else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) |
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child->thread.debug.dbcr2 |= DBCR2_DAC12MX; |
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else /* PPC_BREAKPOINT_MODE_MASK */ |
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child->thread.debug.dbcr2 |= DBCR2_DAC12MM; |
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regs_set_return_msr(child->thread.regs, child->thread.regs->msr | MSR_DE); |
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return 5; |
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} |
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#endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */ |
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long ppc_set_hwdebug(struct task_struct *child, struct ppc_hw_breakpoint *bp_info) |
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{ |
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if (bp_info->version != 1) |
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return -ENOTSUPP; |
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/* |
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* Check for invalid flags and combinations |
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*/ |
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if (bp_info->trigger_type == 0 || |
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(bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE | |
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PPC_BREAKPOINT_TRIGGER_RW)) || |
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(bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) || |
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(bp_info->condition_mode & |
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~(PPC_BREAKPOINT_CONDITION_MODE | |
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PPC_BREAKPOINT_CONDITION_BE_ALL))) |
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return -EINVAL; |
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#if CONFIG_PPC_ADV_DEBUG_DVCS == 0 |
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if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) |
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return -EINVAL; |
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#endif |
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if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) { |
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if (bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE || |
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bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) |
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return -EINVAL; |
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return set_instruction_bp(child, bp_info); |
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} |
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if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT) |
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return set_dac(child, bp_info); |
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#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE |
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return set_dac_range(child, bp_info); |
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#else |
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return -EINVAL; |
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#endif |
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} |
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long ppc_del_hwdebug(struct task_struct *child, long data) |
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{ |
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int rc; |
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if (data <= 4) |
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rc = del_instruction_bp(child, (int)data); |
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else |
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rc = del_dac(child, (int)data - 4); |
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if (!rc) { |
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if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0, |
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child->thread.debug.dbcr1)) { |
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child->thread.debug.dbcr0 &= ~DBCR0_IDM; |
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regs_set_return_msr(child->thread.regs, |
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child->thread.regs->msr & ~MSR_DE); |
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} |
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} |
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return rc; |
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}
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