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191 lines
4.6 KiB
191 lines
4.6 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* This file contains the power_save function for 6xx & 7xxx CPUs |
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* rewritten in assembler |
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* |
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* Warning ! This code assumes that if your machine has a 750fx |
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* it will have PLL 1 set to low speed mode (used during NAP/DOZE). |
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* if this is not the case some additional changes will have to |
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* be done to check a runtime var (a bit like powersave-nap) |
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*/ |
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#include <linux/threads.h> |
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#include <asm/reg.h> |
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#include <asm/page.h> |
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#include <asm/cputable.h> |
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#include <asm/thread_info.h> |
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#include <asm/ppc_asm.h> |
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#include <asm/asm-offsets.h> |
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#include <asm/feature-fixups.h> |
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.text |
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/* |
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* Init idle, called at early CPU setup time from head.S for each CPU |
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* Make sure no rest of NAP mode remains in HID0, save default |
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* values for some CPU specific registers. Called with r24 |
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* containing CPU number and r3 reloc offset |
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*/ |
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_GLOBAL(init_idle_6xx) |
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BEGIN_FTR_SECTION |
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mfspr r4,SPRN_HID0 |
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rlwinm r4,r4,0,10,8 /* Clear NAP */ |
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mtspr SPRN_HID0, r4 |
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b 1f |
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END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) |
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blr |
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1: |
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slwi r5,r24,2 |
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add r5,r5,r3 |
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BEGIN_FTR_SECTION |
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mfspr r4,SPRN_MSSCR0 |
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addis r6,r5, nap_save_msscr0@ha |
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stw r4,nap_save_msscr0@l(r6) |
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END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR) |
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BEGIN_FTR_SECTION |
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mfspr r4,SPRN_HID1 |
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addis r6,r5,nap_save_hid1@ha |
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stw r4,nap_save_hid1@l(r6) |
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END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX) |
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blr |
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/* |
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* Here is the power_save_6xx function. This could eventually be |
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* split into several functions & changing the function pointer |
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* depending on the various features. |
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*/ |
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_GLOBAL(ppc6xx_idle) |
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/* Check if we can nap or doze, put HID0 mask in r3 |
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*/ |
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lis r3, 0 |
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BEGIN_FTR_SECTION |
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lis r3,HID0_DOZE@h |
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END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE) |
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BEGIN_FTR_SECTION |
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/* We must dynamically check for the NAP feature as it |
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* can be cleared by CPU init after the fixups are done |
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*/ |
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lis r4,cur_cpu_spec@ha |
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lwz r4,cur_cpu_spec@l(r4) |
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lwz r4,CPU_SPEC_FEATURES(r4) |
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andi. r0,r4,CPU_FTR_CAN_NAP |
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beq 1f |
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/* Now check if user or arch enabled NAP mode */ |
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lis r4,powersave_nap@ha |
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lwz r4,powersave_nap@l(r4) |
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cmpwi 0,r4,0 |
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beq 1f |
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lis r3,HID0_NAP@h |
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1: |
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END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) |
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cmpwi 0,r3,0 |
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beqlr |
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/* Some pre-nap cleanups needed on some CPUs */ |
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andis. r0,r3,HID0_NAP@h |
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beq 2f |
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BEGIN_FTR_SECTION |
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/* Disable L2 prefetch on some 745x and try to ensure |
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* L2 prefetch engines are idle. As explained by errata |
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* text, we can't be sure they are, we just hope very hard |
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* that well be enough (sic !). At least I noticed Apple |
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* doesn't even bother doing the dcbf's here... |
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*/ |
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mfspr r4,SPRN_MSSCR0 |
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rlwinm r4,r4,0,0,29 |
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sync |
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mtspr SPRN_MSSCR0,r4 |
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sync |
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isync |
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lis r4,KERNELBASE@h |
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dcbf 0,r4 |
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dcbf 0,r4 |
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dcbf 0,r4 |
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dcbf 0,r4 |
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END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR) |
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2: |
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BEGIN_FTR_SECTION |
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/* Go to low speed mode on some 750FX */ |
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lis r4,powersave_lowspeed@ha |
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lwz r4,powersave_lowspeed@l(r4) |
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cmpwi 0,r4,0 |
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beq 1f |
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mfspr r4,SPRN_HID1 |
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oris r4,r4,0x0001 |
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mtspr SPRN_HID1,r4 |
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1: |
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END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX) |
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/* Go to NAP or DOZE now */ |
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mfspr r4,SPRN_HID0 |
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lis r5,(HID0_NAP|HID0_SLEEP)@h |
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BEGIN_FTR_SECTION |
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oris r5,r5,HID0_DOZE@h |
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END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE) |
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andc r4,r4,r5 |
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or r4,r4,r3 |
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BEGIN_FTR_SECTION |
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oris r4,r4,HID0_DPM@h /* that should be done once for all */ |
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END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM) |
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mtspr SPRN_HID0,r4 |
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BEGIN_FTR_SECTION |
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DSSALL |
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sync |
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
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lwz r8,TI_LOCAL_FLAGS(r2) /* set napping bit */ |
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ori r8,r8,_TLF_NAPPING /* so when we take an exception */ |
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stw r8,TI_LOCAL_FLAGS(r2) /* it will return to our caller */ |
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mfmsr r7 |
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ori r7,r7,MSR_EE |
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oris r7,r7,MSR_POW@h |
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1: sync |
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mtmsr r7 |
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isync |
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b 1b |
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/* |
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* Return from NAP/DOZE mode, restore some CPU specific registers, |
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* R11 points to the exception frame. We have to preserve r10. |
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*/ |
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_GLOBAL(power_save_ppc32_restore) |
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lwz r9,_LINK(r11) /* interrupted in ppc6xx_idle: */ |
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stw r9,_NIP(r11) /* make it do a blr */ |
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#ifdef CONFIG_SMP |
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lwz r11,TASK_CPU(r2) /* get cpu number * 4 */ |
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slwi r11,r11,2 |
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#else |
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li r11,0 |
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#endif |
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/* Todo make sure all these are in the same page |
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* and load r11 (@ha part + CPU offset) only once |
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*/ |
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BEGIN_FTR_SECTION |
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mfspr r9,SPRN_HID0 |
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andis. r9,r9,HID0_NAP@h |
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beq 1f |
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addis r9, r11, nap_save_msscr0@ha |
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lwz r9,nap_save_msscr0@l(r9) |
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mtspr SPRN_MSSCR0, r9 |
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sync |
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isync |
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1: |
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END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR) |
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BEGIN_FTR_SECTION |
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addis r9, r11, nap_save_hid1@ha |
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lwz r9,nap_save_hid1@l(r9) |
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mtspr SPRN_HID1, r9 |
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END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX) |
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blr |
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_ASM_NOKPROBE_SYMBOL(power_save_ppc32_restore) |
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.data |
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_GLOBAL(nap_save_msscr0) |
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.space 4*NR_CPUS |
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_GLOBAL(nap_save_hid1) |
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.space 4*NR_CPUS |
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_GLOBAL(powersave_lowspeed) |
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.long 0
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