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844 lines
19 KiB
844 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
|
/* |
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* HW_breakpoint: a unified kernel/user-space hardware breakpoint facility, |
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* using the CPU's debug registers. Derived from |
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* "arch/x86/kernel/hw_breakpoint.c" |
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* |
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* Copyright 2010 IBM Corporation |
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* Author: K.Prasad <[email protected]> |
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*/ |
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|
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#include <linux/hw_breakpoint.h> |
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#include <linux/notifier.h> |
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#include <linux/kprobes.h> |
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#include <linux/percpu.h> |
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#include <linux/kernel.h> |
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#include <linux/sched.h> |
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#include <linux/smp.h> |
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#include <linux/debugfs.h> |
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#include <linux/init.h> |
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|
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#include <asm/hw_breakpoint.h> |
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#include <asm/processor.h> |
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#include <asm/sstep.h> |
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#include <asm/debug.h> |
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#include <asm/debugfs.h> |
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#include <asm/hvcall.h> |
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#include <asm/inst.h> |
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#include <linux/uaccess.h> |
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|
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/* |
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* Stores the breakpoints currently in use on each breakpoint address |
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* register for every cpu |
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*/ |
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static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM_MAX]); |
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|
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/* |
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* Returns total number of data or instruction breakpoints available. |
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*/ |
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int hw_breakpoint_slots(int type) |
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{ |
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if (type == TYPE_DATA) |
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return nr_wp_slots(); |
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return 0; /* no instruction breakpoints available */ |
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} |
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|
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static bool single_step_pending(void) |
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{ |
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int i; |
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|
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for (i = 0; i < nr_wp_slots(); i++) { |
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if (current->thread.last_hit_ubp[i]) |
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return true; |
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} |
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return false; |
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} |
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|
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/* |
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* Install a perf counter breakpoint. |
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* |
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* We seek a free debug address register and use it for this |
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* breakpoint. |
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* |
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* Atomic: we hold the counter->ctx->lock and we only handle variables |
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* and registers local to this cpu. |
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*/ |
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int arch_install_hw_breakpoint(struct perf_event *bp) |
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{ |
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struct arch_hw_breakpoint *info = counter_arch_bp(bp); |
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struct perf_event **slot; |
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int i; |
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|
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for (i = 0; i < nr_wp_slots(); i++) { |
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slot = this_cpu_ptr(&bp_per_reg[i]); |
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if (!*slot) { |
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*slot = bp; |
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break; |
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} |
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} |
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|
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if (WARN_ONCE(i == nr_wp_slots(), "Can't find any breakpoint slot")) |
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return -EBUSY; |
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|
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/* |
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* Do not install DABR values if the instruction must be single-stepped. |
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* If so, DABR will be populated in single_step_dabr_instruction(). |
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*/ |
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if (!single_step_pending()) |
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__set_breakpoint(i, info); |
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|
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return 0; |
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} |
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|
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/* |
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* Uninstall the breakpoint contained in the given counter. |
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* |
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* First we search the debug address register it uses and then we disable |
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* it. |
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* |
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* Atomic: we hold the counter->ctx->lock and we only handle variables |
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* and registers local to this cpu. |
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*/ |
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void arch_uninstall_hw_breakpoint(struct perf_event *bp) |
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{ |
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struct arch_hw_breakpoint null_brk = {0}; |
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struct perf_event **slot; |
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int i; |
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|
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for (i = 0; i < nr_wp_slots(); i++) { |
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slot = this_cpu_ptr(&bp_per_reg[i]); |
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if (*slot == bp) { |
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*slot = NULL; |
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break; |
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} |
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} |
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|
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if (WARN_ONCE(i == nr_wp_slots(), "Can't find any breakpoint slot")) |
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return; |
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|
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__set_breakpoint(i, &null_brk); |
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} |
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|
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static bool is_ptrace_bp(struct perf_event *bp) |
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{ |
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return bp->overflow_handler == ptrace_triggered; |
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} |
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|
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struct breakpoint { |
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struct list_head list; |
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struct perf_event *bp; |
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bool ptrace_bp; |
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}; |
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|
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static DEFINE_PER_CPU(struct breakpoint *, cpu_bps[HBP_NUM_MAX]); |
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static LIST_HEAD(task_bps); |
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|
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static struct breakpoint *alloc_breakpoint(struct perf_event *bp) |
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{ |
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struct breakpoint *tmp; |
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|
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tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
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if (!tmp) |
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return ERR_PTR(-ENOMEM); |
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tmp->bp = bp; |
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tmp->ptrace_bp = is_ptrace_bp(bp); |
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return tmp; |
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} |
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|
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static bool bp_addr_range_overlap(struct perf_event *bp1, struct perf_event *bp2) |
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{ |
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__u64 bp1_saddr, bp1_eaddr, bp2_saddr, bp2_eaddr; |
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|
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bp1_saddr = ALIGN_DOWN(bp1->attr.bp_addr, HW_BREAKPOINT_SIZE); |
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bp1_eaddr = ALIGN(bp1->attr.bp_addr + bp1->attr.bp_len, HW_BREAKPOINT_SIZE); |
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bp2_saddr = ALIGN_DOWN(bp2->attr.bp_addr, HW_BREAKPOINT_SIZE); |
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bp2_eaddr = ALIGN(bp2->attr.bp_addr + bp2->attr.bp_len, HW_BREAKPOINT_SIZE); |
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|
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return (bp1_saddr < bp2_eaddr && bp1_eaddr > bp2_saddr); |
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} |
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|
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static bool alternate_infra_bp(struct breakpoint *b, struct perf_event *bp) |
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{ |
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return is_ptrace_bp(bp) ? !b->ptrace_bp : b->ptrace_bp; |
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} |
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|
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static bool can_co_exist(struct breakpoint *b, struct perf_event *bp) |
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{ |
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return !(alternate_infra_bp(b, bp) && bp_addr_range_overlap(b->bp, bp)); |
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} |
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|
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static int task_bps_add(struct perf_event *bp) |
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{ |
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struct breakpoint *tmp; |
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|
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tmp = alloc_breakpoint(bp); |
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if (IS_ERR(tmp)) |
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return PTR_ERR(tmp); |
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|
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list_add(&tmp->list, &task_bps); |
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return 0; |
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} |
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|
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static void task_bps_remove(struct perf_event *bp) |
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{ |
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struct list_head *pos, *q; |
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|
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list_for_each_safe(pos, q, &task_bps) { |
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struct breakpoint *tmp = list_entry(pos, struct breakpoint, list); |
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|
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if (tmp->bp == bp) { |
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list_del(&tmp->list); |
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kfree(tmp); |
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break; |
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} |
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} |
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} |
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|
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/* |
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* If any task has breakpoint from alternate infrastructure, |
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* return true. Otherwise return false. |
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*/ |
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static bool all_task_bps_check(struct perf_event *bp) |
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{ |
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struct breakpoint *tmp; |
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|
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list_for_each_entry(tmp, &task_bps, list) { |
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if (!can_co_exist(tmp, bp)) |
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return true; |
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} |
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return false; |
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} |
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|
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/* |
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* If same task has breakpoint from alternate infrastructure, |
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* return true. Otherwise return false. |
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*/ |
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static bool same_task_bps_check(struct perf_event *bp) |
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{ |
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struct breakpoint *tmp; |
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|
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list_for_each_entry(tmp, &task_bps, list) { |
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if (tmp->bp->hw.target == bp->hw.target && |
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!can_co_exist(tmp, bp)) |
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return true; |
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} |
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return false; |
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} |
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|
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static int cpu_bps_add(struct perf_event *bp) |
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{ |
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struct breakpoint **cpu_bp; |
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struct breakpoint *tmp; |
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int i = 0; |
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|
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tmp = alloc_breakpoint(bp); |
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if (IS_ERR(tmp)) |
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return PTR_ERR(tmp); |
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|
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cpu_bp = per_cpu_ptr(cpu_bps, bp->cpu); |
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for (i = 0; i < nr_wp_slots(); i++) { |
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if (!cpu_bp[i]) { |
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cpu_bp[i] = tmp; |
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break; |
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} |
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} |
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return 0; |
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} |
|
|
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static void cpu_bps_remove(struct perf_event *bp) |
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{ |
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struct breakpoint **cpu_bp; |
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int i = 0; |
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|
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cpu_bp = per_cpu_ptr(cpu_bps, bp->cpu); |
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for (i = 0; i < nr_wp_slots(); i++) { |
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if (!cpu_bp[i]) |
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continue; |
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|
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if (cpu_bp[i]->bp == bp) { |
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kfree(cpu_bp[i]); |
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cpu_bp[i] = NULL; |
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break; |
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} |
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} |
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} |
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|
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static bool cpu_bps_check(int cpu, struct perf_event *bp) |
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{ |
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struct breakpoint **cpu_bp; |
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int i; |
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|
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cpu_bp = per_cpu_ptr(cpu_bps, cpu); |
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for (i = 0; i < nr_wp_slots(); i++) { |
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if (cpu_bp[i] && !can_co_exist(cpu_bp[i], bp)) |
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return true; |
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} |
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return false; |
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} |
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|
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static bool all_cpu_bps_check(struct perf_event *bp) |
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{ |
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int cpu; |
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|
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for_each_online_cpu(cpu) { |
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if (cpu_bps_check(cpu, bp)) |
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return true; |
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} |
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return false; |
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} |
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|
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/* |
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* We don't use any locks to serialize accesses to cpu_bps or task_bps |
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* because are already inside nr_bp_mutex. |
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*/ |
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int arch_reserve_bp_slot(struct perf_event *bp) |
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{ |
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int ret; |
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|
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/* ptrace breakpoint */ |
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if (is_ptrace_bp(bp)) { |
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if (all_cpu_bps_check(bp)) |
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return -ENOSPC; |
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|
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if (same_task_bps_check(bp)) |
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return -ENOSPC; |
|
|
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return task_bps_add(bp); |
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} |
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|
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/* perf breakpoint */ |
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if (is_kernel_addr(bp->attr.bp_addr)) |
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return 0; |
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|
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if (bp->hw.target && bp->cpu == -1) { |
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if (same_task_bps_check(bp)) |
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return -ENOSPC; |
|
|
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return task_bps_add(bp); |
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} else if (!bp->hw.target && bp->cpu != -1) { |
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if (all_task_bps_check(bp)) |
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return -ENOSPC; |
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|
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return cpu_bps_add(bp); |
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} |
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|
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if (same_task_bps_check(bp)) |
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return -ENOSPC; |
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|
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ret = cpu_bps_add(bp); |
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if (ret) |
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return ret; |
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ret = task_bps_add(bp); |
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if (ret) |
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cpu_bps_remove(bp); |
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|
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return ret; |
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} |
|
|
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void arch_release_bp_slot(struct perf_event *bp) |
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{ |
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if (!is_kernel_addr(bp->attr.bp_addr)) { |
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if (bp->hw.target) |
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task_bps_remove(bp); |
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if (bp->cpu != -1) |
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cpu_bps_remove(bp); |
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} |
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} |
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|
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/* |
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* Perform cleanup of arch-specific counters during unregistration |
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* of the perf-event |
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*/ |
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void arch_unregister_hw_breakpoint(struct perf_event *bp) |
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{ |
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/* |
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* If the breakpoint is unregistered between a hw_breakpoint_handler() |
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* and the single_step_dabr_instruction(), then cleanup the breakpoint |
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* restoration variables to prevent dangling pointers. |
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* FIXME, this should not be using bp->ctx at all! Sayeth peterz. |
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*/ |
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if (bp->ctx && bp->ctx->task && bp->ctx->task != ((void *)-1L)) { |
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int i; |
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|
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for (i = 0; i < nr_wp_slots(); i++) { |
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if (bp->ctx->task->thread.last_hit_ubp[i] == bp) |
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bp->ctx->task->thread.last_hit_ubp[i] = NULL; |
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} |
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} |
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} |
|
|
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/* |
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* Check for virtual address in kernel space. |
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*/ |
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int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) |
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{ |
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return is_kernel_addr(hw->address); |
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} |
|
|
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int arch_bp_generic_fields(int type, int *gen_bp_type) |
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{ |
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*gen_bp_type = 0; |
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if (type & HW_BRK_TYPE_READ) |
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*gen_bp_type |= HW_BREAKPOINT_R; |
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if (type & HW_BRK_TYPE_WRITE) |
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*gen_bp_type |= HW_BREAKPOINT_W; |
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if (*gen_bp_type == 0) |
|
return -EINVAL; |
|
return 0; |
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} |
|
|
|
/* |
|
* Watchpoint match range is always doubleword(8 bytes) aligned on |
|
* powerpc. If the given range is crossing doubleword boundary, we |
|
* need to increase the length such that next doubleword also get |
|
* covered. Ex, |
|
* |
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* address len = 6 bytes |
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* |=========. |
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* |------------v--|------v--------| |
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* | | | | | | | | | | | | | | | | | |
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* |---------------|---------------| |
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* <---8 bytes---> |
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* |
|
* In this case, we should configure hw as: |
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* start_addr = address & ~(HW_BREAKPOINT_SIZE - 1) |
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* len = 16 bytes |
|
* |
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* @start_addr is inclusive but @end_addr is exclusive. |
|
*/ |
|
static int hw_breakpoint_validate_len(struct arch_hw_breakpoint *hw) |
|
{ |
|
u16 max_len = DABR_MAX_LEN; |
|
u16 hw_len; |
|
unsigned long start_addr, end_addr; |
|
|
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start_addr = ALIGN_DOWN(hw->address, HW_BREAKPOINT_SIZE); |
|
end_addr = ALIGN(hw->address + hw->len, HW_BREAKPOINT_SIZE); |
|
hw_len = end_addr - start_addr; |
|
|
|
if (dawr_enabled()) { |
|
max_len = DAWR_MAX_LEN; |
|
/* DAWR region can't cross 512 bytes boundary on p10 predecessors */ |
|
if (!cpu_has_feature(CPU_FTR_ARCH_31) && |
|
(ALIGN_DOWN(start_addr, SZ_512) != ALIGN_DOWN(end_addr - 1, SZ_512))) |
|
return -EINVAL; |
|
} else if (IS_ENABLED(CONFIG_PPC_8xx)) { |
|
/* 8xx can setup a range without limitation */ |
|
max_len = U16_MAX; |
|
} |
|
|
|
if (hw_len > max_len) |
|
return -EINVAL; |
|
|
|
hw->hw_len = hw_len; |
|
return 0; |
|
} |
|
|
|
/* |
|
* Validate the arch-specific HW Breakpoint register settings |
|
*/ |
|
int hw_breakpoint_arch_parse(struct perf_event *bp, |
|
const struct perf_event_attr *attr, |
|
struct arch_hw_breakpoint *hw) |
|
{ |
|
int ret = -EINVAL; |
|
|
|
if (!bp || !attr->bp_len) |
|
return ret; |
|
|
|
hw->type = HW_BRK_TYPE_TRANSLATE; |
|
if (attr->bp_type & HW_BREAKPOINT_R) |
|
hw->type |= HW_BRK_TYPE_READ; |
|
if (attr->bp_type & HW_BREAKPOINT_W) |
|
hw->type |= HW_BRK_TYPE_WRITE; |
|
if (hw->type == HW_BRK_TYPE_TRANSLATE) |
|
/* must set alteast read or write */ |
|
return ret; |
|
if (!attr->exclude_user) |
|
hw->type |= HW_BRK_TYPE_USER; |
|
if (!attr->exclude_kernel) |
|
hw->type |= HW_BRK_TYPE_KERNEL; |
|
if (!attr->exclude_hv) |
|
hw->type |= HW_BRK_TYPE_HYP; |
|
hw->address = attr->bp_addr; |
|
hw->len = attr->bp_len; |
|
|
|
if (!ppc_breakpoint_available()) |
|
return -ENODEV; |
|
|
|
return hw_breakpoint_validate_len(hw); |
|
} |
|
|
|
/* |
|
* Restores the breakpoint on the debug registers. |
|
* Invoke this function if it is known that the execution context is |
|
* about to change to cause loss of MSR_SE settings. |
|
*/ |
|
void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs) |
|
{ |
|
struct arch_hw_breakpoint *info; |
|
int i; |
|
|
|
for (i = 0; i < nr_wp_slots(); i++) { |
|
if (unlikely(tsk->thread.last_hit_ubp[i])) |
|
goto reset; |
|
} |
|
return; |
|
|
|
reset: |
|
regs_set_return_msr(regs, regs->msr & ~MSR_SE); |
|
for (i = 0; i < nr_wp_slots(); i++) { |
|
info = counter_arch_bp(__this_cpu_read(bp_per_reg[i])); |
|
__set_breakpoint(i, info); |
|
tsk->thread.last_hit_ubp[i] = NULL; |
|
} |
|
} |
|
|
|
static bool is_larx_stcx_instr(int type) |
|
{ |
|
return type == LARX || type == STCX; |
|
} |
|
|
|
static bool is_octword_vsx_instr(int type, int size) |
|
{ |
|
return ((type == LOAD_VSX || type == STORE_VSX) && size == 32); |
|
} |
|
|
|
/* |
|
* We've failed in reliably handling the hw-breakpoint. Unregister |
|
* it and throw a warning message to let the user know about it. |
|
*/ |
|
static void handler_error(struct perf_event *bp, struct arch_hw_breakpoint *info) |
|
{ |
|
WARN(1, "Unable to handle hardware breakpoint. Breakpoint at 0x%lx will be disabled.", |
|
info->address); |
|
perf_event_disable_inatomic(bp); |
|
} |
|
|
|
static void larx_stcx_err(struct perf_event *bp, struct arch_hw_breakpoint *info) |
|
{ |
|
printk_ratelimited("Breakpoint hit on instruction that can't be emulated. Breakpoint at 0x%lx will be disabled.\n", |
|
info->address); |
|
perf_event_disable_inatomic(bp); |
|
} |
|
|
|
static bool stepping_handler(struct pt_regs *regs, struct perf_event **bp, |
|
struct arch_hw_breakpoint **info, int *hit, |
|
struct ppc_inst instr) |
|
{ |
|
int i; |
|
int stepped; |
|
|
|
/* Do not emulate user-space instructions, instead single-step them */ |
|
if (user_mode(regs)) { |
|
for (i = 0; i < nr_wp_slots(); i++) { |
|
if (!hit[i]) |
|
continue; |
|
current->thread.last_hit_ubp[i] = bp[i]; |
|
info[i] = NULL; |
|
} |
|
regs_set_return_msr(regs, regs->msr | MSR_SE); |
|
return false; |
|
} |
|
|
|
stepped = emulate_step(regs, instr); |
|
if (!stepped) { |
|
for (i = 0; i < nr_wp_slots(); i++) { |
|
if (!hit[i]) |
|
continue; |
|
handler_error(bp[i], info[i]); |
|
info[i] = NULL; |
|
} |
|
return false; |
|
} |
|
return true; |
|
} |
|
|
|
static void handle_p10dd1_spurious_exception(struct arch_hw_breakpoint **info, |
|
int *hit, unsigned long ea) |
|
{ |
|
int i; |
|
unsigned long hw_end_addr; |
|
|
|
/* |
|
* Handle spurious exception only when any bp_per_reg is set. |
|
* Otherwise this might be created by xmon and not actually a |
|
* spurious exception. |
|
*/ |
|
for (i = 0; i < nr_wp_slots(); i++) { |
|
if (!info[i]) |
|
continue; |
|
|
|
hw_end_addr = ALIGN(info[i]->address + info[i]->len, HW_BREAKPOINT_SIZE); |
|
|
|
/* |
|
* Ending address of DAWR range is less than starting |
|
* address of op. |
|
*/ |
|
if ((hw_end_addr - 1) >= ea) |
|
continue; |
|
|
|
/* |
|
* Those addresses need to be in the same or in two |
|
* consecutive 512B blocks; |
|
*/ |
|
if (((hw_end_addr - 1) >> 10) != (ea >> 10)) |
|
continue; |
|
|
|
/* |
|
* 'op address + 64B' generates an address that has a |
|
* carry into bit 52 (crosses 2K boundary). |
|
*/ |
|
if ((ea & 0x800) == ((ea + 64) & 0x800)) |
|
continue; |
|
|
|
break; |
|
} |
|
|
|
if (i == nr_wp_slots()) |
|
return; |
|
|
|
for (i = 0; i < nr_wp_slots(); i++) { |
|
if (info[i]) { |
|
hit[i] = 1; |
|
info[i]->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ; |
|
} |
|
} |
|
} |
|
|
|
int hw_breakpoint_handler(struct die_args *args) |
|
{ |
|
bool err = false; |
|
int rc = NOTIFY_STOP; |
|
struct perf_event *bp[HBP_NUM_MAX] = { NULL }; |
|
struct pt_regs *regs = args->regs; |
|
struct arch_hw_breakpoint *info[HBP_NUM_MAX] = { NULL }; |
|
int i; |
|
int hit[HBP_NUM_MAX] = {0}; |
|
int nr_hit = 0; |
|
bool ptrace_bp = false; |
|
struct ppc_inst instr = ppc_inst(0); |
|
int type = 0; |
|
int size = 0; |
|
unsigned long ea; |
|
|
|
/* Disable breakpoints during exception handling */ |
|
hw_breakpoint_disable(); |
|
|
|
/* |
|
* The counter may be concurrently released but that can only |
|
* occur from a call_rcu() path. We can then safely fetch |
|
* the breakpoint, use its callback, touch its counter |
|
* while we are in an rcu_read_lock() path. |
|
*/ |
|
rcu_read_lock(); |
|
|
|
if (!IS_ENABLED(CONFIG_PPC_8xx)) |
|
wp_get_instr_detail(regs, &instr, &type, &size, &ea); |
|
|
|
for (i = 0; i < nr_wp_slots(); i++) { |
|
bp[i] = __this_cpu_read(bp_per_reg[i]); |
|
if (!bp[i]) |
|
continue; |
|
|
|
info[i] = counter_arch_bp(bp[i]); |
|
info[i]->type &= ~HW_BRK_TYPE_EXTRANEOUS_IRQ; |
|
|
|
if (wp_check_constraints(regs, instr, ea, type, size, info[i])) { |
|
if (!IS_ENABLED(CONFIG_PPC_8xx) && |
|
ppc_inst_equal(instr, ppc_inst(0))) { |
|
handler_error(bp[i], info[i]); |
|
info[i] = NULL; |
|
err = 1; |
|
continue; |
|
} |
|
|
|
if (is_ptrace_bp(bp[i])) |
|
ptrace_bp = true; |
|
hit[i] = 1; |
|
nr_hit++; |
|
} |
|
} |
|
|
|
if (err) |
|
goto reset; |
|
|
|
if (!nr_hit) { |
|
/* Workaround for Power10 DD1 */ |
|
if (!IS_ENABLED(CONFIG_PPC_8xx) && mfspr(SPRN_PVR) == 0x800100 && |
|
is_octword_vsx_instr(type, size)) { |
|
handle_p10dd1_spurious_exception(info, hit, ea); |
|
} else { |
|
rc = NOTIFY_DONE; |
|
goto out; |
|
} |
|
} |
|
|
|
/* |
|
* Return early after invoking user-callback function without restoring |
|
* DABR if the breakpoint is from ptrace which always operates in |
|
* one-shot mode. The ptrace-ed process will receive the SIGTRAP signal |
|
* generated in do_dabr(). |
|
*/ |
|
if (ptrace_bp) { |
|
for (i = 0; i < nr_wp_slots(); i++) { |
|
if (!hit[i]) |
|
continue; |
|
perf_bp_event(bp[i], regs); |
|
info[i] = NULL; |
|
} |
|
rc = NOTIFY_DONE; |
|
goto reset; |
|
} |
|
|
|
if (!IS_ENABLED(CONFIG_PPC_8xx)) { |
|
if (is_larx_stcx_instr(type)) { |
|
for (i = 0; i < nr_wp_slots(); i++) { |
|
if (!hit[i]) |
|
continue; |
|
larx_stcx_err(bp[i], info[i]); |
|
info[i] = NULL; |
|
} |
|
goto reset; |
|
} |
|
|
|
if (!stepping_handler(regs, bp, info, hit, instr)) |
|
goto reset; |
|
} |
|
|
|
/* |
|
* As a policy, the callback is invoked in a 'trigger-after-execute' |
|
* fashion |
|
*/ |
|
for (i = 0; i < nr_wp_slots(); i++) { |
|
if (!hit[i]) |
|
continue; |
|
if (!(info[i]->type & HW_BRK_TYPE_EXTRANEOUS_IRQ)) |
|
perf_bp_event(bp[i], regs); |
|
} |
|
|
|
reset: |
|
for (i = 0; i < nr_wp_slots(); i++) { |
|
if (!info[i]) |
|
continue; |
|
__set_breakpoint(i, info[i]); |
|
} |
|
|
|
out: |
|
rcu_read_unlock(); |
|
return rc; |
|
} |
|
NOKPROBE_SYMBOL(hw_breakpoint_handler); |
|
|
|
/* |
|
* Handle single-step exceptions following a DABR hit. |
|
*/ |
|
static int single_step_dabr_instruction(struct die_args *args) |
|
{ |
|
struct pt_regs *regs = args->regs; |
|
struct perf_event *bp = NULL; |
|
struct arch_hw_breakpoint *info; |
|
int i; |
|
bool found = false; |
|
|
|
/* |
|
* Check if we are single-stepping as a result of a |
|
* previous HW Breakpoint exception |
|
*/ |
|
for (i = 0; i < nr_wp_slots(); i++) { |
|
bp = current->thread.last_hit_ubp[i]; |
|
|
|
if (!bp) |
|
continue; |
|
|
|
found = true; |
|
info = counter_arch_bp(bp); |
|
|
|
/* |
|
* We shall invoke the user-defined callback function in the |
|
* single stepping handler to confirm to 'trigger-after-execute' |
|
* semantics |
|
*/ |
|
if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ)) |
|
perf_bp_event(bp, regs); |
|
current->thread.last_hit_ubp[i] = NULL; |
|
} |
|
|
|
if (!found) |
|
return NOTIFY_DONE; |
|
|
|
for (i = 0; i < nr_wp_slots(); i++) { |
|
bp = __this_cpu_read(bp_per_reg[i]); |
|
if (!bp) |
|
continue; |
|
|
|
info = counter_arch_bp(bp); |
|
__set_breakpoint(i, info); |
|
} |
|
|
|
/* |
|
* If the process was being single-stepped by ptrace, let the |
|
* other single-step actions occur (e.g. generate SIGTRAP). |
|
*/ |
|
if (test_thread_flag(TIF_SINGLESTEP)) |
|
return NOTIFY_DONE; |
|
|
|
return NOTIFY_STOP; |
|
} |
|
NOKPROBE_SYMBOL(single_step_dabr_instruction); |
|
|
|
/* |
|
* Handle debug exception notifications. |
|
*/ |
|
int hw_breakpoint_exceptions_notify( |
|
struct notifier_block *unused, unsigned long val, void *data) |
|
{ |
|
int ret = NOTIFY_DONE; |
|
|
|
switch (val) { |
|
case DIE_DABR_MATCH: |
|
ret = hw_breakpoint_handler(data); |
|
break; |
|
case DIE_SSTEP: |
|
ret = single_step_dabr_instruction(data); |
|
break; |
|
} |
|
|
|
return ret; |
|
} |
|
NOKPROBE_SYMBOL(hw_breakpoint_exceptions_notify); |
|
|
|
/* |
|
* Release the user breakpoints used by ptrace |
|
*/ |
|
void flush_ptrace_hw_breakpoint(struct task_struct *tsk) |
|
{ |
|
int i; |
|
struct thread_struct *t = &tsk->thread; |
|
|
|
for (i = 0; i < nr_wp_slots(); i++) { |
|
unregister_hw_breakpoint(t->ptrace_bps[i]); |
|
t->ptrace_bps[i] = NULL; |
|
} |
|
} |
|
|
|
void hw_breakpoint_pmu_read(struct perf_event *bp) |
|
{ |
|
/* TODO */ |
|
} |
|
|
|
void ptrace_triggered(struct perf_event *bp, |
|
struct perf_sample_data *data, struct pt_regs *regs) |
|
{ |
|
struct perf_event_attr attr; |
|
|
|
/* |
|
* Disable the breakpoint request here since ptrace has defined a |
|
* one-shot behaviour for breakpoint exceptions in PPC64. |
|
* The SIGTRAP signal is generated automatically for us in do_dabr(). |
|
* We don't have to do anything about that here |
|
*/ |
|
attr = bp->attr; |
|
attr.disabled = true; |
|
modify_user_hw_breakpoint(bp, &attr); |
|
}
|
|
|